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Publication numberCN1046607 A
Publication typeApplication
Application numberCN 90102465
Publication date31 Oct 1990
Filing date20 Apr 1990
Priority date20 Apr 1989
Also published asCA2030621A1, CA2030621C, DE69017741D1, DE69017741T2, EP0394206A2, EP0394206A3, EP0394206B1, US5148373, WO1990013040A1
Publication number90102465.1, CN 1046607 A, CN 1046607A, CN 90102465, CN-A-1046607, CN1046607 A, CN1046607A, CN90102465, CN90102465.1
Inventors保罗威尔金森登特
Applicant艾利森电话股份有限公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Method and arrangement for accurate digital determination of time or phase position of signal pulse train
CN 1046607 A
Abstract  translated from Chinese
在多个异或门(OR0-OR3)中将脉冲序列与多个在时间上有相互偏移的参考时钟信号(RCLO-RCL3)进行比较,各门的输出信号(MS0-MS3)送入比较电路(CO)以比较各信号的脉冲传号/空号比,由转换器(AD)对所选出的信号进行模数转换,由代码转换器(CC)对该数字形式的脉冲序列和三个最高有效数位进行代码转换。 A plurality of exclusive OR gates (OR0-OR3) in the pulse sequence with a plurality of mutually shifted in time there is a reference clock signal (RCLO-RCL3) comparing the output signal of each door (MS0-MS3) fed Comparison circuit (CO) to compare the signal pulse mark / space ratio, by the converter (AD) of the selected analog to digital signal conversion by the code converter (CC) in digital form of the pulse sequence and three most significant several bits of code conversion. 通过添加或扣除预定的数字序列,所给出的二进制码能够对由脉冲序列的取样频率和/或参考频率和该频率之间的频率差所导致的系统偏差进行修正。 By adding or deducting a predetermined digital sequence, the binary code can be given to the system deviation of the sampling frequency by a frequency difference pulse train and / or between the reference frequency and the frequency of the resulting corrected.
Claims(6)  translated from Chinese
1.一种用于精确数字测定在电信系统中的信号脉冲序列的时间或相位位置的方法,其特征在于:对信号(WT)进行脉冲形成以形成方波脉冲序列,将该脉冲序列与多个相互有时间偏移的方波参考信号(RCL0-RCL3)进行比较,以便由所说的比较结果形成新信号(MS0-MS3);通过所谓的比较最大值中的最小值运算对所说的各新信号进行相互比较;对脉冲传号/空号比最接近于预定脉冲传号/空号比的信号进行模/数转换,以便把所说的数字形式信号转换成二进制码,所说的转换是结合在所说的模/数转换前从所说的信号中选取的数字(B1-B3)一起进行的;通过添加或扣除预定的数字序列的方式,所说的二进制码能够对由脉冲序列的取样频率和/或参考频率和该频率之间的频率差所导致的系统误差进行修正。 1. A method in a telecommunication system of the time or phase position of a signal pulse sequence for measuring the precise figures, wherein: forming a signal (WT) to form a pulse sequence of square wave pulse, the pulse sequence and more a mutual time shift of the square wave reference signals (RCL0-RCL3) is compared, so as to form new signals (MS0-MS3) from said comparison result; by comparing the maximum value of the so-called minimum-value operation to said Each new signals compared with each other; pulse mark / space ratio is closest to a predetermined pulse mark / space ratio of the signal analog / digital conversion, in order to convert said digital signal into a binary code form, said Before the conversion is a combination of said analog / digital conversion of the signal from said selected number (B1-B3) together; the manner by adding or deducting a predetermined sequence of numbers, said binary code by the pulse can be system error frequency difference sampling frequency sequence and / or the reference frequency and the frequency between the resulting corrected.
2.一种采用如权利要求1所述方法精确数字测定电信系统中的信号脉冲序列的时间或相位位置的装置,其特征在于:将信号(WT)提供给用于脉冲形成的限制器(L)的输入端;所得到的方波形脉冲序列由限制器的输出端传输给多个异或门(OR0-OR3)的第一输入端,参考时钟信号(RCL0-RCL3)提供至每一个门的第二输入端,所说时钟信号彼此之间在时间上依次有偏移,各门电路的每一输出端产生具有一定频率和一定传号/空号比的输出信号,所说的脉冲传号/空号比随所说的第一和第二输入端的输入信号之比的不同而不同;从所说的门电路(OR0-OR3)输出的信号(MS0-MS3)提供至多路调制器(M)和比较电路(CO)的输入端,在该比较电路中进行比较最大值中的最小值(MIN of MAX)的运算;比较各输出信号(MS0-MS3)的脉冲传号/空号比;随后,所说输出信号中其脉冲传号/空号比最接近预定脉冲传号/空号比的信号,从所说脉冲序列的输出端,通过所说的多路调制器(M),提供至模/数转换器(AD)的输入端,并且还以数字形式提供至代码转换器(CC)的第一输入端;代码转换器的第二输入端接收由在所说的模/数转换前的脉冲序列确定的信号数位(B1-B3);从代码转换器的第一和第二输入端输入的信号将转换成二进制形式,并由转换器的输出端输出。 2. A precision digital measurement device using such time or phase position of the telecommunication system signals a pulse sequence, characterized in that the method of claim 1 wherein: the signal (WT) is supplied to the limiter for pulse forming (L ) input terminal; a first input terminal of the square wave pulse sequence obtained from the output of the limiter transmitted to a plurality of exclusive OR gates (OR0-OR3), the reference clock signal (RCL0-RCL3) is supplied to each gate a second input terminal, each of said clock signal are sequentially offset in time, each output of each gate circuit generates a certain frequency and a certain mark / space ratio of the output signal, said pulse mark / ratio varies with the ratio of said number of empty input signals of the first and second input terminal; modulator provided to the multiplexer (M) from said gate signal (OR0-OR3) output (MS0-MS3) and a comparator circuit (CO) input terminal, compares the maximum value of the minimum value (MIN of MAX) operation in the comparing circuit; comparing the output signals (MS0-MS3) pulse mark / space ratio; subsequently , said output pulse signal whose mark / space ratio is closest to a predetermined pulse mark / space ratio of the signal from the output terminal of said pulse sequence, through said multiplexer (M), to provide analog / digital converter (AD) input terminal, and also in digital form to the code converter (CC) a first input terminal; transcoder is received by the second input terminal prior to said A / D converter pulse sequence determines the number of bits of the signal (B1-B3); a first transcoder and a second input signal from the input terminal is converted into binary form, and output by the output terminal of the converter.
3.如权利要求2所述的装置,其特征在于:所说的已确定的信号数位(B1-B3)构成该脉冲序列的三个最高有效位。 3. The apparatus according to claim, wherein: said digital signal has been determined (B1-B3) constitute the three most significant bits of the pulse sequence.
4.如权利要求2所述的装置,其特征在于:所说的预定脉冲传号/空号比的值为50/50。 4. The apparatus according to claim 2, wherein: said predetermined pulse mark / space ratio is 50/50.
5.如权利要求2所述的装置,其特征在于:当具有参考频率的信号的总数为N时,所说的各参考频率信号间的时间偏移为N分之一个计时周期。 5. The apparatus according to claim 2, characterized in that: When the number of a signal having a reference frequency is N, each of said time offset between the reference frequency signal for a per N ticks.
6.如权利要求2所述的装置,其特征在于:为了更精确地测定所说的脉冲传号/空号比,门电路(OR0-OR3)的输出端与相应的低通滤波器(LP0-LP3)的输入端相连,而滤波器的输出端再与比较电路(CO)和多路调制器(M)的输入端相连。 6. The apparatus according to claim 2, characterized in that: in order to more accurately determine said pulse mark / space ratio, gate circuits (OR0-OR3) with the corresponding output terminal of the low-pass filter (LP0 -LP3) connected to the input, and the output of the filter is then connected to the comparator circuit (CO) and a multiplexer (M) of the input terminal.
Description  translated from Chinese

本发明涉及一种用于精确数字测定信号脉冲序列相对于某固定时间或参考频率的时间或相位位置的方法和装置。 The present invention relates to a relatively fixed time or a certain time or phase method and apparatus for accurate digital determination of the position of a pulse sequence used for the reference signal frequency. 测量时,本发明的装置可给出相应于某一时间的测量值的相应的数字,并在其输出端直接给出所说的测量值。 When the measuring apparatus of the present invention can be given a certain time corresponding to the measured values of the corresponding number, and the measured value of said given directly at its output.

在已有技术中,主要有两种测定信号脉冲序列的时间或相位位置的方法,它们分别是零交叉测时法和复合矢量法。 In the prior art, the main method of the time or phase position of the two measurement signal pulse sequence, which are measured when the zero-crossing method and the complex vector method.

使用零交叉法时,是通过在脉冲序列发生符号变化的那些时刻,用参考分频器链记录它们的位置,从而获得所需的时间信息。 When using zero-crossing method, is sign change by those moments in the pulse sequence, using the reference divider chain of their position to obtain the time information required.

采用这种方法所获得的时间分辨率,仅仅是产生在参考分频器链输入端的最高参考频率信号的一个周期。 Using time resolution obtained by this method, only one cycle is generated at the input of the reference divider chain of the highest reference frequency signal. 例如,若要测定重复频率为1兆赫、分辨率为1度的脉冲序列的相位位置,就必须在分频器链的输入端施加频率为360兆赫的信号。 For example, to measuring a repetition frequency of 1 MHz, a resolution of 1 degree phase position of the pulse sequence, then a frequency of 360 MHz the signal must be applied to the input of divider chain. 因此,即使对于具有中等分辨率的低频脉冲序列,也需要使用动作非常快的逻辑组件来测定其相位。 Thus, even for low-frequency pulse sequence having a medium-resolution, but also need to be measured very quickly using the logical operation of the phase component.

使用复合矢量法时,若所需的信息包含在脉冲序列的正弦基频分量中,则需通过平衡混频器分析正、余弦参考频率的相关性,从而滤出这个正弦分量并把其分解成两个正交分量。 When using complex vector method, if required information is included in the sinusoidal base frequency components of the pulse sequence, you need to balance the mixer by analyzing the correlation of sine and cosine reference frequency, which filter out the sinusoidal component and put it down into two orthogonal components. 因此,为了测定相位,接下来需要对这两个结果进行数字化处理,并用计算机计算它们之比的反正切。 Therefore, in order to measure the phase, followed by the results of the two need to digitize, and calculating the ratio thereof by computer arctangent.

上述第一种方法存在的问题是,即使在进行相对简单的相位测量时,也需要使用非常高级的逻辑组件。 The first method of the above problems is that even when relatively simple phase measurements, the need to use very high-level logic components.

上述第二种方法存在的问题是,由于模拟相关器自身的不完善,使该方法的使用受到很大的限制,而且,该方法还需要在计算机中计算反正切,从而大大增加了该方法的复杂性。 The above-described second method there is a problem, since the analog correlator own imperfections, so that this method is severely limited, and the method further requires calculating the arc tangent in the computer, thereby greatly increasing the method complexity.

本发明的装置的特征在于权利要求所述的那些创造性特点和对上述问题的解决。 Characterized in that the apparatus of the present invention is that the characteristics and creative solution to the above problem of claim. 本发明的装置的特征还在于,在使用时,是将脉冲序列提供至脉冲形成器(限制器),后者给出传号/空号比约为50/50的方波;该方波和N个(比如说,4个)参考频率方波信号一起提供给N个异或电路,这些参考信号在时间上依次相差N分之一个周期;或是从高频开始对所说的频率向下进行分频,或是使用延迟线,都能得到所需的依次的时间差,至于采用这些方法中的哪一个,是不重要的;用比较电路对异或电路给出的N个输出信号的传号/空号比进行相互比较,以确定信号相位位于N个相位区中的哪一个;随后,选择脉冲传号/空号比最接近50/50的信号,通过低通滤波器滤波,并通过模数转换器进行数字化处理以形成二进制码,该二进制码给出在已确定的相位区内的更精细的相位信息。 Apparatus of the present invention is characterized in that, in use, is to provide a pulse train to a pulse former (limiter), which provides a mark / space ratio of about 50/50 square wave; and the square wave N number (for example, 4) the reference frequency of the square wave signal provided to the N exclusive-OR circuits, these reference signals in the time difference of one turn per cycle N; or from the beginning of the high frequency of said frequency down dividing the frequency, or use a delay line, can be obtained successively the difference between the time required, as the use of these methods in which one, is unimportant; N output signal pass comparator circuit with an exclusive OR circuit given mark / space ratio compared with each other to determine the phase of the signal is located in the N phase region which; Subsequently, the selection pulse mark / space ratio signal closest to 50/50, through a low pass filter, and by ADC digitized to form a binary code, the binary code is given in a finer phase information determined phase region. 本发明的装置所具有的超过已有技术的优点是,它能够以比参考时钟所可能达到的最高频率的一个周期更大的精确度来测量或测定时间,同时,无需配置特别高速的逻辑组件就能够提高该装置的工作频率,而且,参考时钟频率可以不与被测脉冲序列的频率精确相应。 Advantages of the apparatus of the present invention over the prior art has is that it can be greater than one period of the reference clock frequency of the highest possible degree of accuracy measured or determined time, the same time, eliminating the need of special high-speed logic components it is possible to increase the operating frequency of the device, and the reference clock frequency can not be measured with the pulse train frequencies corresponding precision.

一种精确数字测定电信系统中信号脉冲序列的时间或相位位置的方法,其特征在于:对信号(WT)进行脉冲形成以形成方波脉冲序列;将该脉冲序列与多个相互有时间偏移的方波参考信号(RCL0-RCL3)进行比较,以便根据所说的比较结果形成新信号(MS0-MS3);通过所谓的比较最大值中的最小值(MIN of MAX)的运算对所说的各新信号进行相互比较;对其脉冲传号/空号比最接近预定脉冲传号/空号比的信号进行模/数转换,以把所说的数字形式信号转换成二进制码,所说的转换是结合在所说的模数转换前从所说的信号中选取的数字(B1-B3)一起进行的;通过添加或扣除预定的数字序列的方式,所说的二进制码能够对由脉冲序列的取样频率和/或参考频率和该频率之间的频率差所导致的系统误差进行修正。 A precision digital measurement method telecommunication system time or phase position of a signal pulse sequence, characterized in that: a signal (WT) to form a pulse forming a square wave pulse sequence; the pulse sequence and a plurality of mutually time-shifted The square wave reference signals (RCL0-RCL3) is compared, so as to form new signals (MS0-MS3) according to said comparison result; the maximum value by comparing the so-called minimum value (MIN of MAX) operation of said Each new signals compared with each other; their pulse mark / space ratio is closest to a predetermined pulse mark / space ratio of the signal analog / digital converter to convert said digital signal into a binary code form, said Before the conversion is a combination of said analog to digital conversion of the signal from said selected number (B1-B3) carried out together; manner by adding or deducting a predetermined sequence of numbers, said binary code by the pulse sequence can be systematic error frequency difference sampling frequency and / or frequency between the reference frequency and the resulting corrected.

下面,参考本发明的实施例和附图,对本发明的装置进行更详细的描述。 Next, the embodiment of the present invention with reference to examples and the accompanying drawings, of apparatus of the present invention will be described in more detail.

图1示出的是信号的脉冲形成和时间偏移。 Figure 1 shows a pulse signal is formed and the time offset.

图2示出的是在异或电路的输出端脉冲传号/空号比(占空比)的变化。 Figure 2 shows that at the output of the exclusive OR circuit pulse mark / ratio (duty ratio) changes empty.

图3示出了本发明的比较电路的示意图。 Figure 3 shows a schematic diagram of the comparator circuit of the present invention.

图4示出了本发明的装置的方框图。 Figure 4 shows a block diagram of apparatus according to the present invention.

正如图1所明显示出的那样,模拟形式的脉冲序列WT提供至限制器L的输入端,由限制器形成脉冲型信号,以便在限制器的输出端产生脉冲传号/空号比为50/50的方波。 As explicitly shown in Figure 1 above, the pulse train WT in analogue form is supplied to the input of the limiter L, is formed by a pulse-type signal limiter, so that at the output of the limiter pulse mark / space ratio of 50 / square wave 50. 该方波提供给N个异或门的每一个的第一输入端,在这一实施例中为4个门,其参考标记分别为OR0-OR3。 A first input terminal of the square wave is supplied N exclusive OR gates each of a, in this embodiment four gates, which reference marks are OR0-OR3. 参考时钟信号RCL0-RCL3提供至所说每一个门的第二输入端。 Reference clock signal RCL0-RCL3 supplied to said second input of each gate. 各参考时钟信号均为方波信号,而且在时间上依次相差1/N个周期。 Each reference clock signals are square wave signal, and the difference in time sequentially 1 / N cycles. 正如图2所明显示出的那样,每一个异或门的输出信号均为方波信号MS0-MS3中的一个,且其频率为相应门的输入信号频率的两倍,其传号/空号比取决于该异或门的两个输入信号的相互间的时间。 As explicitly shown in Figure 2 above, the output signal of each XOR gate are square wave signals MS0-MS3 one, and whose frequency is twice the input signal frequency of respective gates, whose mark / space ratio depends on the time between them the two input signals of the exclusive OR gate. 该图示出了由各异或门OR0-OR3输出的信号MS0-MS3的传号/空号比的变化,该变化是脉冲序列计时与参考时钟计时间关系的函数。 The figure shows a mark / space ratio changes by varying the output of OR gates OR0-OR3 signals MS0-MS3, which changes the timing and the reference pulse sequence is a function of the count of the time clock.

由于尚不能明确确定包含该相位的180度的范围,所以要从一个信号异或门的输出信号中获得两个输入信号间的时间,尚有一些不确定的因素。 Since not yet clearly defined range of 180 degrees including the phase, so that a signal from the XOR gate output signal to obtain the time between the two input signals, there is some uncertainty. 但是,通过对多个异或门的输出信号进行比较,可以解决这个问题。 However, by a plurality of exclusive OR gate output signal are compared, can solve this problem. 例如在这一实施例中,N=4,因而能够立刻确定出在参考时钟计时周期的哪八分之一周期中发生有输入信号的转变。 For example, in this embodiment, N = 4, it is possible to determine immediately the occurrence of the reference clock ticks one eighth period in which there is a change of the input signal. 这是通过下述的比较最大值中的最小值(MIN of MAX)的运算,对各门OR0-OR3的输出信号的传号/空号比进行比较来实现的。 This is done by comparing the maximum value below the minimum value (MIN of MAX) operation, the output signals of the gates OR0-OR3 of mark / space ratio is compared to achieve.

表1若MS0>MS2,则取B1=0,否则,取B1=1; Table 1 if MS0> MS2, then take the B1 = 0, otherwise, take B1 = 1;

若MS1>MS3,则取B2=0,否则,取B2=1; If MS1> MS3, then take B2 = 0, otherwise, take B2 = 1;

若MAX(MS0,MS2)>MAX(MS1,MS3),则取B3=0,否则,取B3=1。 If MAX (MS0, MS2)> MAX (MS1, MS3), then take B3 = 0, otherwise, take B3 = 1. 在通过适当的代码转换把格雷码转换为二进制码或其它输出信号码之后,在所需时间测量过程中,B1、B2、B3确定着三个最高有效位。 After passing through the appropriate code conversion to gray code into a binary code or other output channel number, the time required for the measurement process, B1, B2, B3 determine the three most significant bits.

在信号的零交叉计时所在的八分园内,三位数位B1、B2、B3与该八分园1∶1相对应。 In the zero-crossing signal timing where the eighth park, three-digit bits B1, B2, B3 and the eighth of the park 1:1 correspond.

借助如图3所示的这种NPN和PNP射极跟随器的组合电路能够实现上述所谓的比较最大值中的最小值的运算,尽管借助比较电路(比较器)、开关和逻辑电路也能够实现上述的运算。 Such as shown in FIG. 3 by means of NPN and PNP emitter follower circuit achieves the above combination of the so-called maximum value minimum value comparison operation, although by means of the comparison circuit (comparator), switches and logic circuits can be realized the above-described operation. 因此,图3示出了一种根据表1确定有效测量值的三个最高有效位的方法。 Thus, Figure 3 shows a method for the three most significant bits determine the effective measurement values in Table 1 based.

在测量时,为了能够确定三个最低有效位LSB,需要更加精确地确定在异或门OR0-OR3中的至少一个门输出的输出信号的传号/空号比。 In the measurement, in order to be able to determine the three least significant bit LSB, needs to be more accurately determine the mark / space ratio in XOR gate OR0-OR3 least one gate output of the output signal. 实际上,选择其信号传号/空号比尽可能接近50/50的门是有益处的,因为这种脉冲形式对于由慢速逻辑硬件的有限上升时间所导致的失真不太敏感。 In fact, selecting its signal mark / space ratio of 50/50 as close door is beneficial, since this pulse form for the logical hardware limited by the slow rise time is less sensitive to distortion caused. 在这种情况下,根据上述方法而确定的三个最高有效位B1、B2、B3可以用来选择具有这种特性的、可进行更精细分析的脉冲,该脉冲是在进行比较最大值中的最小值的运算后得到的脉冲。 In this case, the three most significant bits B1 determined according to the method described above, B2, B3 can be used to select having such characteristics, may be finer analysis of pulse, which is the maximum value of engaging in comparison After calculating the minimum value of the pulse obtained.

正如图4所示,对传号/空号比的更精细的测量,是利用低通滤波器LP0-LP3获取信号的平均值,然后利用模/数转换器AD进行模数转换来实现的。 As shown, a finer measurement of the mark / space ratio of 4, using a low pass filter LP0-LP3 average of the signal acquired, and then use the A / D converter analog to digital converter AD to achieve. 在应用于高速运行的情况下,可以使用,比如说,“FLASH”型这样的4位模数转换器。 In the case for high-speed operation, can be used, for example, "FLASH" type like four ADC. 各低通滤波器的输入端与相应的异或电路OR0-OR3的输出端相连。 The input to each low pass filter with the corresponding output terminal of the exclusive OR circuits OR0-OR3 is connected. 滤波器的输出端与比较电路CO的输入端相连接,并与多路调制器M的输入端相连接。 Input terminal of the output filter and a comparison circuit CO is connected, and is connected to the multiplexer input terminal M. 比较电路的输出,即最高有效位B1、B2、B3,提供至多路调制器M的输入端,以控制对脉冲传号/空号比最接近于50/50的异或门输出信号(MS0-MS3)的选择。 The output of the comparison circuit, i.e. the most significant bits B1, B2, B3, to provide inputs to the multiplexer M of the modulator to control the pulse mark / space ratio is closest to the output signal of the exclusive OR gate in 50/50 (MS0- MS3) selection. 最高有效位的值还提供至代码转换器CC的输入端。 Value of the most significant bit is also provided to the input of the transcoder CC. 代码转换器可以由分立的逻辑门构成,亦可以由ROM存储器中的查找表构成。 The transcoder may be constituted by discrete logic gates, also may be constituted by a ROM memory look-up table. 该存储器地址包括三个数位B1、B2、B3和用于所说模/数转换结果的数位(第四位或更多的位)。 The memory address includes three digits B1, B2, B3, and for said A / D conversion result of the number of bits (the fourth bit or more bits). 存储器的内容包括与每一可能的输入位阵形式相对应的所需的输出码。 Contents of the memory comprises for each possible input bit array corresponding to the form of the desired output code. 多路调制器输出的信号提供给所说模/数转换器AD的输入端,模/数转换器的输出端与所说代码转换器CC相应的输入端相连,而代码转换器的输出为二进制代码信号。 Modulator output signal supplied to said multiplexer / D converter AD input of the A / D converter and the output of said code converter CC is connected to respective input terminals, and the output of the transcoder binary code signal. 当四位模/数转换器以这种方式与三个最高有效位B1、B2、B3相结合时,在相位测量过程中能够得到7个数位的精度。 When the four analog / digital converter in this way in combination with the three most significant bits B1, B2, B3, the phase measurement accuracy can be obtained during the 7-bit number. 因此,无需采用高于1兆赫的参考时钟频率,就能够以1/128微秒(8毫微秒)的时间分辨率测定重复频率为1兆赫的脉冲序列的运行时间。 Thus, without the use of higher than 1 MHz reference clock frequency, it is possible to 1/128 sec (8 ns) time resolution measurement run time repetition frequency of 1 MHz pulse train.

如果需要用常规的二进制码给出时间测量的结果,三个最高有效位需要由格雷码转换成二进制码,而且需要在交变八分园(alter nating octanes)内补足三个最低有效位LSB。 The results, if required by the conventional binary code given time measurement, the three most significant bits required by the Gray code into binary code, and need to make up three LSB of alternating eighth Park (alter nating octanes) inside. 这一工作可以通过常规的逻辑运算、查存储表或软件来实现。 This work can be achieved by conventional logic operations, check storage table or software.

对于脉冲序列的预计频率和参考计时频率之间的任何差异,二进制代码输出将有助予输出值的修正。 For expect any differences between the frequency and the reference clock frequency pulse sequence, binary code output will help to correct the output values. 若假设脉冲序列的预计正常频率为1000003赫兹,而所用的参考计时频率恰好为1000000赫兹。 If we assume that the normal frequency of the pulse train is expected to 1,000,003 hertz, while the reference clock frequency used exactly as 1,000,000 hertz. 为简单起见,假设测量精度为7个数位,每秒测量128次。 For simplicity, assume that the measurement precision of 7 digits, measuring 128 times per second. 那么,在修正前,二进制数值的序列将有如下的排列:……59,62,65……,122,125,0,3,6,9……这表明由于所说的频率差为3,所以每步增量为3,模为128。 So, before correction, the sequence of binary values will have the following order: ...... ...... 59,62,65, 122,125,0,3,6,9 ...... This indicates that due to said frequency difference is 3, So every step increments of 3, 128 die. 若采用其内容在每次采样时增量为3,模为128的7位外存储器,则能够对其加以修正,即在输出信号输出之前,从测量值中将这个值扣除掉。 The use of its content at each sampling time increments of 3, modulo 128 7 external memory, it is possible to them to be amended before the output signal that is output from the measured value will be deducted from the value of the swap.

当采样周期与参考时钟偏置之间的关系更为复杂时,亦可以采用类似的技术进行处理,该技术包括,比如说,在存储器中存储整个周期的修正值,或是增加具有部分参数的存储器的字长。 When the sampling period and the relationship between the reference clock biases are more complex, they can be processed using a similar technique, the technique including, for example, the correction value stored in the memory of the cycle, or to increase the portion having parameters word length memory.

这表明,能够使用已物化在逻辑软件或硬件中的算术运算来补偿脉冲序列的测量频率(取样率)、参考时钟和中频之间的非整数关系。 This indicates, can be used has been materialized in the software or hardware logic arithmetic operation to compensate the measurement pulse train frequency (sampling rate), the reference clock and non-integer relationship between the intermediate frequency.

正如上面已明显示出的那样,本发明的装置无需使用非常高速的逻辑组件,就能够有效的提高所获得的测量精度。 As already explicitly shown above, the apparatus of the present invention without the use of very high-speed logic components, it is possible to effectively improve the measurement accuracy obtained.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
CN101082642B4 Jun 20074 Jul 2012施耐德电器工业公司Method and device for sampling electric signals of a multiphase electric installation
Classifications
International ClassificationG01R25/00
Cooperative ClassificationG01R25/00
European ClassificationG01R25/00
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