CN104515947A - Rapid configuration and test method for programmable logic device in system programming - Google Patents
Rapid configuration and test method for programmable logic device in system programming Download PDFInfo
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Abstract
The invention discloses a rapid configuration and test method for a programmable logic device in system programming. According to the method, ISP (in-system programmable) state machine configuration codes are acquired by one-time programming and four-time transcoding. The rapid configuration and test method includes the steps of conducting test configuration program development in a corresponding development environment of the programmable logic device to acquire original configuration codes; converting the original configuration codes into an SVF (serial vector format) file through a conversion tool; converting the SVF file into a PCF (portable compiled format) file; generating an ATP file by a C-language transcoding program; converting the ATP file into a Pattern file, and using an ATE (automatic test equipment) automatic test system for rapid configuration and test. The rapid configuration and test method for the programmable logic device in system programming has the advantages that the ISP state machine configuration codes can be generated automatically, and multi-time configuration and test operation can be conducted, so that test fault coverage rate is increased greatly, and the test problem of the programmable logic device is solved; the rapid configuration and test method is universal.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of configuration and method of testing of programmable logic device (PLD), be specifically related to a kind of rapid configuration and method of testing of programmable logic device (PLD) in-system programming.
Background technology
Programmable logic device (PLD) comprises PROM, PAL, GAL, PLA, CPLD, FPGA etc., and they mainly contain programmable with array or the composition such as array, gate array, by the logic function that programming realization is certain.
Programmable logic device (PLD) is carried out testing the resource that may will comprise its inside and carries out structure analysis, the process of (TS) is implemented through a test configurations (TC) and vector, be configured as the circuit with specific function, from application level, circuit is tested again, the function of completing circuit and parameter testing.
In-system programmable components (In-System Programmable is called for short ISP) technology is the programming technique of a kind of advanced person that first late 1980s Lattice company proposes.So-called " in-system programming " refers to the ability can modified to the logic function of device, circuit board or whole electronic system at any time or reconstruct.This reconstruct or amendment can each links in product design, manufacture process, even carry out after payment user.Support that the programmable logic device (PLD) of ISP technology is called in-system programmable logical device (ISP-PLD).
Traditional programming to programmable logic device (PLD) is all generally connect computer by downloading wire or programmable device to programme to device, concerning being that JED file " is downloaded (Down Load) ", in CPLD device, is in FPGA by bit stream data Bit file " configuration " concerning FPGA CPLD device.First go to test again to test macro with after downloading wire programming often to the test of CPLD device, only once configure---test process, this method test coverage is low, or with in downloading wire programming process, logic analyser is utilized to go acquisition configuration data, process through manually again and obtain ISP configuration code, waste time and energy so very much and be easy to make mistakes; Although to FPGA device detection can by from string or from and wait collocation method realization in system configuration and test, still need utilization state machine method to be configured and checking to the test of JTAG.
Summary of the invention
The technical issues that need to address of the present invention are just the defect overcoming prior art, a kind of rapid configuration and method of testing of programmable logic device (PLD) in-system programming are provided, the inventive method can generate ISP state machine configuration code automatically, ATE can be utilized to realize at system rapid configuration programmable logic device (PLD) such as PROM, CPLD, FPGA, can repeatedly configure and test operation, substantially increase test failure coverage rate, solve the problem of programmable logic device (PLD) test; And the inventive method has versatility, among the rapid configuration that can be widely used in the programmable logic device (PLD) such as PROM, PLD, CPLD, FPGA of the companies such as Xilinx, Altera, Lattice, Cypress and test.
For solving the problem, the present invention adopts technical scheme to be:
The rapid configuration of programmable logic device (PLD) in-system programming and method of testing, described rapid configuration and method of testing obtain ISP state machine configuration code by one-time programming four transcoding processes;
The step of described rapid configuration and method of testing is:
(1) under the corresponding corresponding development environment of programmable logic device (PLD), carry out test configurations program development, obtain original configuration code;
(2) original configuration code is converted to the SVF file of serial vector format by crossover tool;
(3) SVF formatted file is converted to PCF formatted file;
(4) utilize C language transcoding program to be extracted by the valid data in PCF formatted file and directly generate ATP formatted file;
(5) ATP form is changed into Pattern file needed for test macro, utilize ATE Auto-Test System to carry out rapid configuration and the test of programmable logic device (PLD) in-system programming.
Preferably, the programmable logic device (PLD) of different company adopts different development environments to carry out test configurations program development.
Preferably, the programmable logic device (PLD) of Xilinx company adopts ISE development environment to carry out the test configurations program of test configurations program development acquisition .bit .bin .mcs form; The programmable logic device (PLD) of altera corp adopts Quartus development environment to carry out the test configurations program of test configurations program development acquisition .pof .sof form; The programmable logic device (PLD) of Lattice company adopts ispLEVER development environment to carry out the test configurations program of test configurations program development acquisition .jed form; The programmable logic device (PLD) of Cypress company adopts Warp development environment to carry out the test configurations program of test configurations program development acquisition .jed form.
Preferably, adopt the automatic transcoding of test configurations program to generate ISP configuration code, ATE Auto-Test System is directly at system rapid configuration; The method not adopting artificial collection of material configuration code and utilize downloading wire and programmable device to configure.Traditional artificial collection of material configuration code and the method utilizing downloading wire and programmable device to configure, test coverage is low, wastes time and energy very much and is easy to make mistakes, and is unfavorable for the rapid configuration and the test operation that improve programmable logic device (PLD).
Preferably, programmable logic device (PLD) comprises the programmable logic device (PLD) such as PROM, PAL, GAL, PLA, CPLD, FPGA of the companies such as Xilinx, Altera, Lattice, Cypress.
Preferably, crossover tool in step (2) is: the iMPACT instrument of Xilinx company, " Creat JAM, SVF, ISC " instrument of altera corp, the ISR instrument of Cypress company, the ispVM instrument of Lattice company, for the crossover tool that the product choice for use of different company is corresponding.
Preferably, the crossover tool used in step (3) is Svf2pcf transcoding program.
Preferably, the crossover tool used in step (4) is Pcf2atp transcoding program.
Preferably, ATE Auto-Test System is J750EX or the Ultra-FLEX test macro of Teradyne Inc. of the U.S..Select in above-mentioned two test macros one as ATE automatic checkout system according to the performance of specific product and test request.
Preferably, test configurations program carries out test configurations program development according to the requirement of the databook of detected programmable logic device (PLD) product, method of testing, test specification, test outline.
Advantage of the present invention and beneficial effect are:
The rapid configuration of programmable logic device (PLD) in-system programming of the present invention and method of testing, automatically ISP state machine configuration code can be generated, ATE can be utilized to realize at system rapid configuration programmable logic device (PLD) such as PROM, CPLD, FPGA, can repeatedly configure and test operation, substantially increase test failure coverage rate, solve the problem of programmable logic device (PLD) test;
The rapid configuration of programmable logic device (PLD) in-system programming of the present invention and method of testing, there is very big versatility, among the rapid configuration that can be widely used in the programmable logic device (PLD) such as PROM, PLD, CPLD, FPGA of the companies such as Xilinx, Altera, Lattice, Cypress and test;
The rapid configuration of programmable logic device (PLD) in-system programming of the present invention and method of testing, test coverage is high and be not easy to make mistakes, and greatly can improve the rapid configuration of in-system programming and the efficiency of test and quality.
Accompanying drawing explanation
Fig. 1 is rapid configuration and the method for testing process flow diagram of programmable logic device (PLD) in-system programming of the present invention.
Fig. 2 is the three condition ISP state machine transition diagram that the present invention uses.
Fig. 3 is the IEEE1149.1 standard I SP state machine transition diagram that the present invention uses.
Fig. 4 the present invention creates SVF file operation interface.
The SVF formatted file schematic diagram that Fig. 5 the present invention generates.
Fig. 6 svf2pcf transcoding operation of the present invention interface.
The PCF formatted file schematic diagram that Fig. 7 the present invention generates.
The ATP formatted file schematic diagram that Fig. 8 the present invention generates.
Embodiment
The following example will further illustrate the present invention.
embodiment 1
The present invention adopts technical scheme to be rapid configuration and the method for testing of programmable logic device (PLD) in-system programming, and described rapid configuration and method of testing obtain ISP state machine configuration code by one-time programming four transcoding processes;
The step of rapid configuration and method of testing is:
(1) under the corresponding corresponding development environment of programmable logic device (PLD), carry out test configurations program development, obtain original configuration code;
(2) original configuration code is converted to the SVF file of serial vector format by crossover tool; Crossover tool is: the iMPACT instrument of Xilinx company, " Creat JAM, SVF, ISC " instrument of altera corp, the ISR instrument of Cypress company, the ispVM instrument of Lattice company.
(3) SVF formatted file is converted to PCF formatted file; Crossover tool is Svf2pcf transcoding program;
(4) utilize C language transcoding program to be extracted by the valid data in PCF formatted file and directly generate ATP formatted file; Crossover tool is Pcf2atp transcoding program;
(5) ATP form is changed into Pattern file needed for test macro, utilize ATE Auto-Test System to carry out rapid configuration and the test of programmable logic device (PLD) in-system programming.
In this method, the programmable logic device (PLD) of different company adopts different development environments to carry out test configurations program development.The programmable logic device (PLD) of Xilinx company adopts ISE development environment to carry out the test configurations program of test configurations program development acquisition .bit .bin .mcs form; The programmable logic device (PLD) of altera corp adopts Quartus development environment to carry out the test configurations program of test configurations program development acquisition .pof .sof form; The programmable logic device (PLD) of Lattice company adopts ispLEVER development environment to carry out the test configurations program of test configurations program development acquisition .jed form; The programmable logic device (PLD) of Cypress company adopts Warp development environment to carry out the test configurations program of test configurations program development acquisition .jed form.
This method adopts the automatic transcoding of test configurations program to generate ISP configuration code, and ATE Auto-Test System is directly at system rapid configuration; The method not adopting artificial collection of material configuration code and utilize downloading wire and programmable device to configure.Traditional artificial collection of material configuration code and the method utilizing downloading wire and programmable device to configure, test coverage is low, wastes time and energy very much and is easy to make mistakes, and is unfavorable for the rapid configuration and the test operation that improve programmable logic device (PLD).
Programmable logic device (PLD) comprises the programmable logic device (PLD) such as PROM, PAL, GAL, PLA, CPLD, FPGA of the companies such as Xilinx, Altera, Lattice, Cypress.
ATE Auto-Test System comprises: J750EX and/or the Ultra-FLEX test macro of Teradyne Inc. of the U.S..According in above-mentioned two automatic checkout systems of product performance selection of detected programmable logic device (PLD) as ATE Auto-Test System;
Test configurations program carries out test configurations program development according to the requirement of the databook of detected programmable logic device (PLD) product, method of testing, test specification, test outline.
The test configurations program used in the present embodiment is that those of ordinary skill in the art can write according to detection demand; belong to existing known mature technology; no longer describe related request and the method for test configurations program in the present embodiment, also do not belong to protection scope of the present invention.
Composition graphs 1 to Fig. 8 illustrates rapid configuration and the method for testing of the present embodiment,
The objective for implementation of this method is all support ISP(in-system programmable components) programmable logic device (PLD), comprise PROM, PAL, GAL, PLA, CPLD, FPGA etc.According to ISP state machine principle, by some transcoding instruments and utilize C language to write transcoding program through four transcoding processes, can be fast automatic be created on configuration code needed for system configuration, recycling ATE directly loads the circuit that cell configuration is become to have certain function by configuration code, and then carrying out comprehensive function and parameter testing, whole configuration and testing process are as shown in Figure 1.
ISP state machine has two kinds: the ISP state machine of three condition ISP state machine and IEEE1149.1 standard.The ISP state machine proposed by Lattice company the earliest only has three states: idle state (IDLE), displacement state (SHIFT) and execution state (EXECUTE), and the transfer of its state as shown in Figure 2.Put forward boundary scan technique by joint test active organization (JTAG) afterwards, IEEE has formulated testing standard to this, is called IEEE1194.1 standard, and the ISP state machine meeting this standard has 16 states, as shown in Figure 3.Two states machine has four signal ports: mode selection terminal MODE(TMS), data input pin SDI(TDI), data output end SDO(TDO), input end of clock SCLK(TCK), control these port statuss according to state machine and by the write device of configuration data serial, the in-system programming of ISP device can be realized.
Serial vector (SVF) form is a kind of order format describing state machine programming, can record whole ISP programming process information.The development environment of major part programmable logic device (PLD) is all supported to convert configuration data file to SVF form.Complete after configurator writes with different development environments, automatically can generate the configuration file of the forms such as bit, bin, mcs, jed, pof, first need to convert thereof into serial vector format (SVF) file.For the ISE development environment of Xilinx company, Configure Device(iMPACT is entered after generating configurator file) interface (as shown in Figure 4), then Boundary Scan is used, add target configuration device and configuration file, then choice menus hurdle---Output---SVF File---Create SVF File, start to record SVF file, any operation (Program now to target devices, Verify, Erase, Get Device ID etc.) can be recorded in SVF file, after recording completes, choice menus hurdle---Output---SVF File---Stop Writing to SVF File, SVF formatted file can be generated, as shown in Figure 5.
After generating SVF formatted file, then need to utilize transcoding software (its operation interface as shown in Figure 6) that SVF format conversion is become PCF formatted file, as shown in Figure 7.
Data in PCF formatted file in double quotation marks are the configuration datas needing to be configured in target devices, in addition, also has the category information of such as " RUNTEST IDLE 100000 TCK " or " wait 100000s ", be meant to need to wait for 100000 clock period in " Run-Test-Idle " state of state machine, these useful datas need to extract.C programmer can be write these valid data are extracted, and convert the binary vector file of ATP form to, as shown in Figure 8.
Finally, recycling test macro software kit changes into the test patterns formatted file corresponding to test macro, ATP format conversion is become Pattern file by the Pattern compiler instrument in the IG-XL of such as Teradyne company, ATE just can be utilized to load configuration code and carry out in system configuration and test target devices.
Thus, rapid configuration of the present invention and method of testing achieve at system rapid configuration, repeatedly can configure and test operation, substantially increase test failure coverage rate, solve the problem of programmable logic device (PLD) test; There is great versatility, among the rapid configuration that can be widely used in the programmable logic device (PLD) such as PROM, PLD, CPLD, FPGA of the companies such as Xilinx, Altera, Lattice, Cypress and test; Further, test coverage is high and be not easy to make mistakes, and greatly can improve the rapid configuration of in-system programming and the efficiency of test and quality.
Last it is noted that obviously, above-described embodiment is only for example of the present invention is clearly described, and the restriction not to embodiment.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all embodiments.And thus the apparent change of amplifying out or variation be still among protection scope of the present invention.
Claims (10)
1. the rapid configuration of programmable logic device (PLD) in-system programming and method of testing, is characterized in that, described rapid configuration and method of testing obtain ISP state machine configuration code by one-time programming four transcoding processes;
The step of described rapid configuration and method of testing is:
(1) under the corresponding corresponding development environment of programmable logic device (PLD), carry out test configurations program development, obtain original configuration code;
(2) original configuration code is converted to the SVF file of serial vector format by crossover tool;
(3) SVF formatted file is converted to PCF formatted file;
(4) utilize C language transcoding program to be extracted by the valid data in PCF formatted file and directly generate ATP formatted file;
(5) ATP form is changed into Pattern file needed for test macro, utilize ATE Auto-Test System to carry out rapid configuration and the test of programmable logic device (PLD) in-system programming.
2. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 1 and method of testing, it is characterized in that, the programmable logic device (PLD) of different company adopts different development environments to carry out test configurations program development.
3. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 2 and method of testing, it is characterized in that, the programmable logic device (PLD) of Xilinx company adopts ISE development environment to carry out the test configurations program of test configurations program development acquisition .bit .bin .mcs form; The programmable logic device (PLD) of altera corp adopts Quartus development environment to carry out the test configurations program of test configurations program development acquisition .pof .sof form; The programmable logic device (PLD) of Lattice company adopts ispLEVER development environment to carry out the test configurations program of test configurations program development acquisition .jed form; The programmable logic device (PLD) of Cypress company adopts Warp development environment to carry out the test configurations program of test configurations program development acquisition .jed form.
4. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 1 and method of testing, it is characterized in that, adopt the automatic transcoding of test configurations program to generate ISP configuration code, ATE Auto-Test System is directly at system rapid configuration; The method not adopting artificial collection of material configuration code and utilize downloading wire and programmable device to configure.
5. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 1 and method of testing, it is characterized in that, programmable logic device (PLD) comprises PROM, PAL, GAL, PLA, CPLD, FPGA programmable logic device (PLD) of Xilinx, Altera, Lattice, Cypress company.
6. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 1 and method of testing, it is characterized in that, crossover tool in step (2) is: the iMPACT instrument of Xilinx company, " Creat JAM, SVF, ISC " instrument of altera corp, the ISR instrument of Cypress company, the ispVM instrument of Lattice company.
7. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 1 and method of testing, it is characterized in that, the crossover tool used in step (3) is Svf2pcf transcoding program.
8. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 1 and method of testing, it is characterized in that, the crossover tool used in step (4) is Pcf2atp transcoding program.
9. the rapid configuration of the programmable logic device (PLD) in-system programming as described in as arbitrary in claim 1-8 and method of testing, it is characterized in that, ATE Auto-Test System is J750EX or the UltraFLEX test macro of Teradyne Inc. of the U.S..
10. the rapid configuration of programmable logic device (PLD) in-system programming as claimed in claim 9 and method of testing, it is characterized in that, test configurations program carries out test configurations program development according to the requirement of the databook of detected programmable logic device (PLD) product, method of testing, test specification, test outline.
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