CN104485281A - Indium phosphide heterojunction transistor emitter region material dry process and wet process combined etching manufacturing method - Google Patents
Indium phosphide heterojunction transistor emitter region material dry process and wet process combined etching manufacturing method Download PDFInfo
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- CN104485281A CN104485281A CN201410578314.XA CN201410578314A CN104485281A CN 104485281 A CN104485281 A CN 104485281A CN 201410578314 A CN201410578314 A CN 201410578314A CN 104485281 A CN104485281 A CN 104485281A
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Abstract
The invention provides an indium phosphide heterojunction transistor emitter region material dry process and wet process combined etching manufacturing method which comprises the following steps: preparing an emitter electrode metal bar; etching an emitter region material for a certain thickness by utilizing a dry etching device; corroding the emitter region material with the remaining thickness by utilizing an acidic etching solution; and preparing base electrode contact metal by utilizing a self-aligning method and forming electrical isolation between the base electrode and the emitter electrode, and thus indium phosphide heterojunction transistor emitter electrode dry process and wet process combined etching manufacturing is finished. The method has the advantages that through carrying out dry etching first on the emitter region material, vertical side wall etching morphology can be obtained, and the width of the emitter region material is maintained; and after the dry etching is carried out to a certain thickness, the wet etching is then carried out, so that damage to the surface of the base region material can be reduced, and side hollowed depth of the emitter region material is reduced.
Description
Technical field
What the present invention relates to is the manufacture method of a kind of heterojunction of indium phosphide transistor emission district material etch, belongs to semiconductor transistor technology field.
Background technology
Bipolar transistor with heterojunction of indium phosphide (InP HBT) has very excellent high frequency characteristics, and in ultrahigh speed Digital Analog Hybrid Circuits, submillimeter wave circuit and optoelectronic IC, tool has been widely used.InP HBT is divided into indium phosphide single heterojunction bipolar transistor (InP SHBT) and indium phosphide double hetero bipolar transistor npn npn (InP DHBT) according to the difference of collector region material.The collector region of InP SHBT is indium gallium arsenic (InGaAs), and the collector region of InP DHBT is indium phosphide (InP).The relative InP SHBT of InP DHBT, have higher puncture voltage and better heat dissipation characteristics, therefore range of application is more wide, is the focus of Study and appliance both at home and abroad at present.For InP HBT, high-frequency parameter mainly contains two, and one is current gain cutoff frequencies (f
t); Two is maximum frequency of oscillation (f
max).For making device high-frequency parameter be increased to γ doubly, emitter live width need foreshorten to original γ
-1/2doubly, for obtaining the better high frequency characteristics of HBT device, emitter live width must be reduced further.Narrower emitter live width proposes severe challenge to emitter rate of finished products, reliability.
The single dry etch process of normal employing or wet corrosion technique in emitter region table top preparation technology conventional at present.Adopt single dry etch process can obtain vertical emitter region material side wall, but due to the physical bombardment of etching gas, material surface damage in base is comparatively large, causes device performance degradation.The base material surface damage adopting single wet corrosion technique to reduce, but draw excessive to the side of emitter region material, cause emitter region material width narrow, even rupture, reduce device yield and reliability.Therefore, there is certain shortcoming in traditional heterojunction of indium phosphide transistor emission district material etching method.
Summary of the invention
What the present invention proposed is that a kind of heterojunction of indium phosphide transistor emission district material wet-dry change combines etching manufacture method, its object is intended to overcome the base material surface run in the material technology of single dry etching emitter region and damages large problem, and problems of too is drawn in the side run in the material technology of single wet etching emitter region, wet-dry change is adopted to combine etching, the damage of base material surface can be reduced and the degree of depth is drawn in material side, emitter region, improve indium phosphide heterojunction transistor device yield and reliability.
Technical solution of the present invention: heterojunction of indium phosphide transistor emission district material wet-dry change combines etching manufacture method, comprises the following steps:
1) on heterojunction of indium phosphide transistor epitaxial material, make emitter metal bar shaped, strip width scope is that 50 nanometers are to 5 microns;
2) utilize dry etching equipment to etch emitter region material, emitter region material total thickness be 10 nanometers to 1 micron, dry etching thickness should be less than emitter region material gross thickness;
3) utilize acid etching solution, the emitter region material of corrosion residual thickness, wet etching creates the side being unlikely to cause emitter to rupture and draws the degree of depth;
4) adopt Alignment Method to prepare base contact metal, form the electric isolution between base stage and emitter, complete heterojunction of indium phosphide transistor emission district material wet-dry change and combine etching making.
Advantage of the present invention: first carry out dry etching to emitter region material and can obtain vertical sidewall etch topography, keeps emitter region material width; Carry out wet etching after dry etching to certain thickness again and can reduce base material surface damage, reduce material side, emitter region and draw the degree of depth, thus improve indium phosphide heterojunction transistor emitter rate of finished products and reliability.
Accompanying drawing explanation
Fig. 1 makes the device profile map after emitter metal bar shaped.
Fig. 2 has been the device profile map after the material of dry etching emitter region.
Fig. 3 has been the device profile map after the material of wet etching emitter region.
Fig. 4 makes device profile map after base contact metal by Alignment Method.
Embodiment
Further describe skill of the present invention below in conjunction with accompanying drawing and state scheme;
Concrete grammar is as follows:
1) on heterojunction of indium phosphide transistor epitaxial material, make emitter metal bar shaped, strip width scope is that 50 nanometers are to 5 microns.As shown in Figure 1.
2) utilize dry etching equipment to etch emitter region material, emitter region material total thickness be 10 nanometers to 1 micron, etching side can keep vertical.A part of emitter region material due to dry etching, reduces the emitter region material thickness needing wet etching, thus reduces side that wet etching causes and draw the degree of depth, avoids because the excessive emitter fracture caused of the degree of depth is drawn in side.As shown in Figure 2.
3) utilize acid etching solution, the emitter region material of corrosion residual thickness, wet etching creates the side being unlikely to cause emitter to rupture and draws the degree of depth.As shown in Figure 3.
4) adopt Alignment Method to prepare base contact metal, contacting metal thickness is less than wet etching material thickness.Survey caused by wet etching is drawn the degree of depth and is defined gap between base contact resistance and emitter region material, thus ensure that the electric isolution between base stage and emitter, completes heterojunction of indium phosphide transistor emission district material wet-dry change and combines etching and make.As shown in Figure 4.
Described Alignment Method is: first make covering emitter by lithography, and the figure wider than emitter metal, graphics field is covered without photoresist, peripheral region has photoresist to cover, evaporation base contact metal, while finally removing photoresist, the base contact metal on photoresist is peeled off simultaneously, leave the base contact metal of emitter both sides and the base contact metal covered on emitter.
Claims (2)
1. heterojunction of indium phosphide transistor emission district material wet-dry change combines an etching manufacture method, it is characterized in that the method comprises the following steps:
1) on heterojunction of indium phosphide transistor epitaxial material, emitter metal bar shaped is made;
2) utilize dry etching equipment, etch certain thickness emitter region material, obtain vertical emitter region etched sidewall;
3) utilize acid etching solution, the emitter region material of corrosion residual thickness, wet etching creates the side being unlikely to cause emitter to rupture and draws the degree of depth;
4) adopt Alignment Method to prepare base contact metal, form the electric isolution between base stage and emitter, complete heterojunction of indium phosphide transistor emission district material wet-dry change and combine etching making.
2. a kind of heterojunction of indium phosphide transistor emission district according to claim 1 material wet-dry change combines the manufacture method of etching, it is characterized in that first carrying out dry etching to emitter region material, obtains vertical sidewall etch topography, keeps emitter region material width; Carry out wet etching after dry etching to certain thickness again and can reduce base material surface damage, reduce material side, emitter region and draw the degree of depth.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111883429A (en) * | 2020-08-06 | 2020-11-03 | 厦门市三安集成电路有限公司 | Platform manufacturing method of GaAs HBT device and GaAs HBT device |
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US5344786A (en) * | 1990-08-31 | 1994-09-06 | Texas Instruments Incorporated | Method of fabricating self-aligned heterojunction bipolar transistors |
US5411632A (en) * | 1992-11-06 | 1995-05-02 | Thomson-Csf | Method for the etching of a heterostructure of materials of the III-V group |
US5717228A (en) * | 1994-11-07 | 1998-02-10 | Nippon Telegraph And Telephone Corporation | Heterojunction bipolar transistor with crystal orientation |
US7598148B1 (en) * | 2004-10-15 | 2009-10-06 | Fields Charles H | Non-self-aligned heterojunction bipolar transistor and a method for preparing a non-self-aligned heterojunction bipolar transistor |
CN103021847A (en) * | 2012-11-29 | 2013-04-03 | 中国电子科技集团公司第五十五研究所 | Method for realizing gallium-arsenic-antimony double-heterojunction bipolar transistor base electrode metallization |
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2014
- 2014-10-27 CN CN201410578314.XA patent/CN104485281A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US5344786A (en) * | 1990-08-31 | 1994-09-06 | Texas Instruments Incorporated | Method of fabricating self-aligned heterojunction bipolar transistors |
US5411632A (en) * | 1992-11-06 | 1995-05-02 | Thomson-Csf | Method for the etching of a heterostructure of materials of the III-V group |
US5717228A (en) * | 1994-11-07 | 1998-02-10 | Nippon Telegraph And Telephone Corporation | Heterojunction bipolar transistor with crystal orientation |
US7598148B1 (en) * | 2004-10-15 | 2009-10-06 | Fields Charles H | Non-self-aligned heterojunction bipolar transistor and a method for preparing a non-self-aligned heterojunction bipolar transistor |
CN103021847A (en) * | 2012-11-29 | 2013-04-03 | 中国电子科技集团公司第五十五研究所 | Method for realizing gallium-arsenic-antimony double-heterojunction bipolar transistor base electrode metallization |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111883429A (en) * | 2020-08-06 | 2020-11-03 | 厦门市三安集成电路有限公司 | Platform manufacturing method of GaAs HBT device and GaAs HBT device |
CN111883429B (en) * | 2020-08-06 | 2023-05-23 | 厦门市三安集成电路有限公司 | Platform manufacturing method of GaAs HBT device and GaAs HBT device |
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