CN104424149A - Split type data flow controllable observable high-speed serial receiving device - Google Patents
Split type data flow controllable observable high-speed serial receiving device Download PDFInfo
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- CN104424149A CN104424149A CN201310377741.7A CN201310377741A CN104424149A CN 104424149 A CN104424149 A CN 104424149A CN 201310377741 A CN201310377741 A CN 201310377741A CN 104424149 A CN104424149 A CN 104424149A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
Abstract
The invention relates to a split type data flow controllable observable high-speed serial receiving device. The split type data flow controllable observable high-speed serial receiving device comprises a device body, wherein a differential signal input port is arranged on the device body. The split type data flow controllable observable high-speed serial receiving device is characterized in that an ASIC receiving assembly is arranged on the differential signal input port; a communication port of the ASIC receiving device is connected with an off-chip buffering assembly; accordingly an integral SerDes receiving circuit can be achieved by adopting ASCI and an on-chip structure does not comprise an on-chip buffering module, clock driving mainly depends on data recovery, and the clock domain is simplified and a sequential logic design is simplified due to the fact that the number of clocks is reduced by one. Additionally, the off-chip elastic buffering module is achieved through FPGA and accordingly the configurability and the observability of the off-chip elastic buffering module are greatly improved.
Description
Technical field
The present invention relates to a kind of serial received device, particularly relate to a kind of split type data stream and can control Observable formula high speed serialization receiving trap.
Background technology
At a high speed (data transfer rate is at more than GHz) serial communication as between backboard and backboard, chip and interchip communication etc. apply the support needing SerDes transceiver module.Under prior art conditions, the transceiver module of more than GHz can only realize with asic chip.Existing commercialization SerDes chip and all similar black box of reusable IP, be difficult to control the data stream of its inside and observe.When carrying out the design of high-speed I/O protocol stack, by optimizing TLP(Transaction Layer Packet) data packet length and clock compensation sequence transmission frequency, can improve the effective transmission speed of passage.This needs a kind of device to control in real time and observes the internal data flow of SerDes receiver module.Elastic buffer module is the data backbone of high-speed data receiver module.In order to realize controlling and Observable of receiver module internal data flow, needing the architecture and the peripheral module that redesign receiver module, making terminal user have approach to configure, control and observe the course of work of elastic buffer module.
Elastic buffer module is for guaranteeing the data integrity communicated between two clock zones.This buffer module is similar to a FIFO (First-In-First-Out), and in FIFO, data export with a certain clock frequency write is another different clock frequency.Because these two clocks (almost always like this) have slight difference on the frequency, then this FIFO likely final overflow or underflow.In order to avoid this situation, elastic buffer can insert or delete special symbol SKP, makes the difference of buffer module compensating clock within the time interval of specifying.This mechanism of overflowing that prevents of elastic buffer module is called clock compensation, ensure that SerDes receiving cable can continuous reception data.The specific implementation principle of elastic buffer module: this buffer module is half-full in normal state, all leaves abundant entrance in the front and back of medial inlet.Even thus ensure that maximum timing differential also can be compensated by the SKP symbol inserting and delete in ordered set.
The target of this implementation method is that maintenance elastic buffer module is half-full.Because recovered clock territory and local clock territory have trickle difference on the frequency, the filling extent of elastic buffer module will depend on the interval between this two clock frequency differences and SKP ordered set of reception.But, whenever receiver module device receives (or multiple) SKP ordered set, elastic buffer module will be made to return half-full state by inserting or delete SKP symbol from ordered set.When local clock is faster than recovered clock, many than stored in elastic buffer module of the symbol of output, then compensate by inserting extra SKP symbol in SKP ordered set.When local clock is slower than recovered clock, elastic buffer module starts close to spill-over.This situation appears at when transmission very large packet (may be maximum), and such SKP ordered set could send after the TLP such as only having send.At this moment single SKP ordered set is not enough to make buffer module get back to half-full state.But, due to SKP ordered set during sending large TLP packet as usual accumulation get off, elastic buffer module receives several SKP ordered set continuously by after large TLP end-of-packet.Receiving trap utilizes these ordered sets afterwards to make elastic buffer module recovery normal condition.
The common feature of the architecture of existing most of high speed serialization receiver module is the inside that elastic buffer module is positioned at receiver module chip.There is following limitation in such design: because elastic buffer module is in the sheet of high speed serialization receiver module, cause its configurability and observability poor; And in sheet the bit wide of elastic buffer module and the degree of depth limited, which has limited the size of the maximum TLP bag (TLP bag can not be blocked by out of Memory) that receiver module can receive; In this structure, sheet there are these three clock zones of data recovery clock, local crystal oscillator clock, system clock PCLK.Data recovery clock and local crystal oscillator clock difference on the frequency very little, be respectively used to the write and read clock of elastic buffer module.The reading and writing clock of elastic buffer module can not have excessive difference on the frequency.Data recovery clock, frequency relation between local clock and system clock are relevant, can not random adjustment System clock frequency.Multiple clock zones on sheet, cause the complexity that sequential logic designs.
Being the design closest to this patent thought in Fig. 1, is the United States Patent (USP) " ELASTIC BUFFER MODULE FOR PCI EXPRESS DEVICES " delivered in January, 2006.This patent will be applicable to the buffer module design of PCIe specification in SerDes chip, feature decides to insert or delete SKP character by read-write pointer difference and a threshold value being compared, and according to the adaptive selection threshold value of read-write situation, the compensation to deviation between two clock zones can be realized.This patent can not solve the limitation of pointed existing high speed serialization receiver module above.
Summary of the invention
Object of the present invention is exactly to solve the above-mentioned problems in the prior art, provides a kind of split type data stream can control Observable formula high speed serialization receiving trap.
Object of the present invention is achieved through the following technical solutions:
Split type data stream can control Observable formula high speed serialization receiving trap, include device body, described device body is provided with differential signal input mouth, wherein: described differential signal input mouth is provided with ASIC receiving unit, the PORT COM of described ASIC receiving trap is connected with the outer Buffer Unit of sheet, the outer Buffer Unit of described sheet is provided with input clock signal port and parallel output signal port.
Above-mentioned split type data stream can control Observable formula high speed serialization receiving trap, wherein: described ASIC receiving unit includes differential received module, the input end of described differential received module connects differential signal input mouth, the output terminal connection data of described differential received module recovers the input end of module, the output terminal of described data recovery module connects the input end of serioparallel exchange module, the output terminal of described serioparallel exchange module connects the input end of decoder module, the outer Buffer Unit of output terminal brace of described decoder module, clock recovery module is connected with between described differential received module and data recovery module.
Further, above-mentioned split type data stream can control Observable formula high speed serialization receiving trap, wherein: described decoder module is connected with receiver state detection module, described receiver state detection module is provided with signal input port.
Further, above-mentioned split type data stream can control Observable formula high speed serialization receiving trap, wherein: the supplemental communication port of described clock recovery module is connected with the supplemental communication port of the supplemental communication port of decoder module, the outer Buffer Unit of sheet.
Again further, above-mentioned split type data stream can control Observable formula high speed serialization receiving trap, wherein: the outer Buffer Unit of described sheet comprises elastic buffer module, the input end of described elastic buffer module connects the output terminal of decoder module, and the output terminal of described elastic buffer module is provided with data-interface.
The advantage of technical solution of the present invention is mainly reflected in: whole SerDes receiving circuit all can adopt ASIC to realize.Further, on sheet, structure is no longer containing elastic buffer module, and the main data recovery clock that relies on drives, and clock quantity reduces 1, thus has simplified clock zone and simplify sequential logic design.In addition, because the outer elastic buffer module of sheet is realized by FPGA, its configurability and observability improve greatly.
Meanwhile, SerDes receiver module architecture can be redefined, make user can configure the size of elastic buffer module, the course of work of Real-Time Monitoring elastic buffer module, thus can control and observe the data stream of SerDes receiver module.Elastic buffer module and clock compensation logic adopt FPGA to realize, and have good configurability.
Further, adopt the development board design supporting the exploitation of high speed protocol stack, developer can be helped to attempt different TLP packet length (TLP packet length is limited to the size of elastic buffer), parallel interface bit wide and speed.On the development board of reality, bit wide and the degree of depth that can configure elastic buffer module by FPGA, can observe the course of work of elastic buffer module by FPGA developing instrument.
Accompanying drawing explanation
Object of the present invention, advantage and disadvantage, by for illustration and explanation for the non-limitative illustration passing through preferred embodiment below.
Fig. 1 is the organigram of existing United States Patent (USP).
Fig. 2 is the overall schematic that split type data stream can control Observable formula high speed serialization receiving trap.
Fig. 3 is the operation organigram that split type data stream can control Observable formula high speed serialization receiving trap.
In figure, the implication of each Reference numeral is as follows:
| 1 | Device body | 2 | Differential signal input mouth |
| 3 | ASIC receiving unit | 4 | The outer Buffer Unit of sheet |
| 5 | Differential received module | 6 | Data recovery module |
| 7 | Serioparallel exchange module | 8 | Decoder module |
| 9 | Clock recovery module | 10 | Receiver state detection module |
| 11 | Elastic buffer module | 12 | Input clock signal port |
| 13 | Parallel output signal port |
Embodiment
Split type data stream as shown in Figure 2 can control Observable formula high speed serialization receiving trap, include device body 1, device body 1 is provided with differential signal input mouth 2, its special feature is: differential signal input mouth 2 of the present invention is provided with ASIC receiving unit 3, the PORT COM of this ASIC receiving trap is connected with the outer Buffer Unit 4 of sheet, the outer Buffer Unit 4 of described sheet is provided with input clock signal port and parallel output signal port.
With regard to the present invention one preferably embodiment, consider the effective process to serial communication, ASIC receiving unit 3 includes differential received module 5.Specifically, the input end of differential received module 5 connects differential signal input mouth 2, the output terminal connection data of this differential received module 5 recovers the input end of module 6.Meanwhile, the output terminal of data recovery module 6 connects the input end of serioparallel exchange module 7.Further, the output terminal of serioparallel exchange module 7 connects the input end of decoder module 8, the outer Buffer Unit 4 of output terminal brace of decoder module 8.Moreover, be connected with clock recovery module 9 between differential received module 5 and data recovery module 6.
Further, decoder module 8 is connected with receiver state detection module 10, receiver state detection module 10 is provided with signal input port.Meanwhile, the supplemental communication port of clock recovery module 9 is connected with the supplemental communication port of decoder module 8, the supplemental communication port of the outer Buffer Unit 4 of sheet.
Further, the outer Buffer Unit 4 of sheet comprises elastic buffer module 11, and the input end of elastic buffer module 11 connects the output terminal of decoder module 8.Meanwhile, the output terminal of elastic buffer module 11 is provided with data-interface.Thus, realize effective separate type to arrange.
In conjunction with actual service condition of the present invention, the differential signal from the IA High Speed Channel outside sheet is converted to single ended serial data stream through differential received module 5.Meanwhile, clock recovery module 9 is extracted data recovered clock from this serial data stream, and data recovery module 6 utilizes this clock to data stream, carries out resampling, thus obtains the serial data stream after recovering.
Then, this data stream is through serioparallel exchange, and after decoding, data become 8 original bit parallel data simultaneously.Further, the decoding different in order to correspondence needs, and realize best decoding specific aim, the decoder module 8 of employing can be 8b/10b or 64b/66b.
Then, this parallel signal outputs to the elastic buffer module 11 outside sheet, treated and after reconfiguring, and occurs according to required frequency and data layout.
Can be found out by above-mentioned character express, after adopting the present invention, whole SerDes receiving circuit all can adopt ASIC to realize.Further, on sheet, structure is no longer containing elastic buffer module, and the main data recovery clock that relies on drives, and clock quantity reduces 1, thus has simplified clock zone and simplify sequential logic design.In addition, because the outer elastic buffer module of sheet is realized by FPGA, its configurability and observability improve greatly.
Meanwhile, SerDes receiver module architecture can be redefined, make user can configure the size of elastic buffer module, the course of work of Real-Time Monitoring elastic buffer module, thus can control and observe the data stream of SerDes receiver module.Elastic buffer module and clock compensation logic adopt FPGA to realize, and have good configurability.
Further, adopt the development board design supporting the exploitation of high speed protocol stack, developer can be helped to attempt different TLP packet length (TLP packet length is limited to the size of elastic buffer), parallel interface bit wide and speed.On the development board of reality, bit wide and the degree of depth that can configure elastic buffer module by FPGA, can observe the course of work of elastic buffer module by FPGA developing instrument.
These embodiments are only the prominent examples of application technical solution of the present invention, allly take equivalent replacement or equivalent transformation and the technical scheme that formed, all drop within the scope of protection of present invention.
Claims (5)
1. split type data stream can control Observable formula high speed serialization receiving trap, include device body, described device body is provided with differential signal input mouth, it is characterized in that: described differential signal input mouth is provided with ASIC receiving unit, the PORT COM of described ASIC receiving trap is connected with the outer Buffer Unit of sheet, the outer Buffer Unit of sheet is provided with input clock signal port and parallel output signal port.
2. split type data stream according to claim 1 can control Observable formula high speed serialization receiving trap, it is characterized in that: described ASIC receiving unit includes differential received module, the input end of described differential received module connects differential signal input mouth, the output terminal connection data of described differential received module recovers the input end of module, the output terminal of described data recovery module connects the input end of serioparallel exchange module, the output terminal of described serioparallel exchange module connects the input end of decoder module, the outer Buffer Unit of output terminal brace of described decoder module, clock recovery module is connected with between described differential received module and data recovery module.
3. split type data stream according to claim 2 can control Observable formula high speed serialization receiving trap, it is characterized in that: described decoder module is connected with receiver state detection module, described receiver state detection module is provided with signal input port.
4. split type data stream according to claim 2 can control Observable formula high speed serialization receiving trap, it is characterized in that: the supplemental communication port of described clock recovery module is connected with the supplemental communication port of the supplemental communication port of decoder module, the outer Buffer Unit of sheet.
5. split type data stream according to claim 1 can control Observable formula high speed serialization receiving trap, it is characterized in that: the outer Buffer Unit of described sheet comprises elastic buffer module, the input end of described elastic buffer module connects the output terminal of decoder module, and the output terminal of described elastic buffer module is provided with data-interface.
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| CN1507026A (en) * | 2002-12-09 | 2004-06-23 | 刘建光 | Method and system for observing all signals inside programmable digital IC chip |
| US20060230215A1 (en) * | 2005-04-06 | 2006-10-12 | Woodral David E | Elastic buffer module for PCI express devices |
| CN101266568A (en) * | 2007-03-16 | 2008-09-17 | 上海燃料电池汽车动力系统有限公司 | MPC555 on-line artificial debugging minimum system |
| CN201742104U (en) * | 2010-09-01 | 2011-02-09 | 湖南大学 | Thyristor triggering plate used for high pressure stationary reactive compensation device |
| CN102708086A (en) * | 2012-05-10 | 2012-10-03 | 无锡华大国奇科技有限公司 | Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) |
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2013
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6112267A (en) * | 1998-05-28 | 2000-08-29 | Digital Equipment Corporation | Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels |
| CN1507026A (en) * | 2002-12-09 | 2004-06-23 | 刘建光 | Method and system for observing all signals inside programmable digital IC chip |
| US20060230215A1 (en) * | 2005-04-06 | 2006-10-12 | Woodral David E | Elastic buffer module for PCI express devices |
| CN101266568A (en) * | 2007-03-16 | 2008-09-17 | 上海燃料电池汽车动力系统有限公司 | MPC555 on-line artificial debugging minimum system |
| CN201742104U (en) * | 2010-09-01 | 2011-02-09 | 湖南大学 | Thyristor triggering plate used for high pressure stationary reactive compensation device |
| CN102708086A (en) * | 2012-05-10 | 2012-10-03 | 无锡华大国奇科技有限公司 | Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) |
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Application publication date: 20150318 |