CN104409335A - Preparation method of silicon carbide JFET gate structure with rectification effect - Google Patents
Preparation method of silicon carbide JFET gate structure with rectification effect Download PDFInfo
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- CN104409335A CN104409335A CN201410657412.2A CN201410657412A CN104409335A CN 104409335 A CN104409335 A CN 104409335A CN 201410657412 A CN201410657412 A CN 201410657412A CN 104409335 A CN104409335 A CN 104409335A
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- gate
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- conduction type
- rectification
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 230000009471 action Effects 0.000 claims description 9
- 239000002800 charge carrier Substances 0.000 abstract description 6
- 230000008901 benefit Effects 0.000 abstract description 2
- 230000006698 induction Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Abstract
The invention relates to a preparation method of a silicon carbide JFET gate structure with a rectification effect. The preparation method comprises the steps that (1) a first conduction type layer grows on a first conduction type substrate; (2) a PN junction is formed; (3) ohmic contact between a source electrode and a drain electrode is achieved through ohmic annealing; (4) rectification gate contact is formed through rectification gate electrode contact annealing. Compared with a conventional silicon carbide JFET gate structure, the silicon carbide JFET gate structure with the rectification effect has the advantages that the controllable gate voltage range is wide, and gate current is low. A gate contact region 7 is added on the basis of the conventional silicon carbide JFET gate structure, the rectification characteristic is introduced between a gate electrode 8 and the gate contact region 7 through adjustment of the doping concentration of the gate contact region and the annealing conditions so as to limit the gate current, the gate electrode voltage range is widened, and the channel connection capacity is improved through the induction effect of charge carriers injected into gates.
Description
Technical field
That the present invention relates to is a kind of preparation method with the carborundum JFET grid structure of rectified action, belongs to technical field of semiconductor device.
Background technology
SiC material energy gap is large, breakdown electric field is high, saturation drift velocity and thermal conductivity large, and these material superior functions become the ideal material making high power, high frequency, high temperature resistant, radioresistance device.SiC JFET has very large value in large merit application, and this all gives the credit to junction gate and has very high stability, and this stability is not limit by reliability of the gate oxide in MOS structure.
One of current restriction SiC JFET widespread adoption very major reason be the complexity of drive circuit and surprisingly open the system damage caused.Due to junction gate after grid voltage exceedes PN junction cut-in voltage gate current will fast layer long, therefore require that work grid voltage will lower than PN junction conducting voltage (being less than 3V).In order to ensure that device is often close device, be usually higher than 2V and open, therefore grid voltage control range is generally less than 1V in the on-state, and this just seriously improves the design difficulty of SiC JFET device drive circuit and the fail safe of system.
In usual ohmic contact grid structure, gate electrode voltage exceedes carborundum PN junction cut-in voltage (2.8V), and gate electrode Injection Current increases fast.Cause channel part 3 place to respond to the first charge carrier suitable with injection rate owing to injecting a large amount of the second charge carrier, raceway groove conducting resistance declines, and conductivity is enhanced.But improve too fast owing to injecting the second carrier concentration with grid voltage, device cannot be operated in this raceway groove 3 enhanced situation.In addition for raceway groove 3 normally-off carborundum JFET device, cut-in voltage is higher than 0V, and grid-control scope is less than 2.8V, and gate electrode 8 voltage power supply scope is too small, easily produces unexpected unlatching in system fluctuation situation.
Summary of the invention
That the present invention proposes is a kind of preparation method with the carborundum JFET grid structure of rectified action, its objective is the above-mentioned technical problem in order to solve existing for prior art, under the state that injection the second charge carrier makes device channel resistance significantly decline, still ensure proper device operation, under system fluctuation situation can be avoided, easily produce unexpected defect of opening.
Technical solution of the present invention: a kind of preparation method with the carborundum JFET grid structure of rectified action, comprises following processing step:
1) in the first conductivity type substrate, the first conductive type layer is grown;
2) inject by two groups gate contact zone and gate regions two parts of being formed respectively and having the second conduction type, gate regions forms PN junction respectively with the drift region and channel region with the first conduction type;
3) source electrode and channel region and the ohmic contact between drain electrode and the first conductivity type substrate is realized by ohm annealing;
4) between gate electrode and the gate contact zone of the second conduction type, honeycomb screen contact is formed by the annealing of rectification gate contact.
Advantage of the present invention: the design's structure adopts the potential barrier between the method adjustment gate electrode 8 of control gate contact zone 7 doping content and annealing conditions and gate contact zone 7, make it have rectification characteristic, nonlinear reduction grid current is with the growth rate of grid voltage, make device grid current when grid injects charge carrier remain within the scope of tolerable, channel region 3 reality conduction width reach maximum after continue through grid and inject the method for charge carrier and improve raceway groove conduction property further.In addition expand grid voltage working range (such as Fig. 6), avoid the accident unlatching that system fluctuation causes.Such as Figure 7 shows that the carborundum JFET mutual conductance test result adopting honeycomb screen structure, after grid voltage is higher than 2.8V, still can keeps higher mutual conductance.
Accompanying drawing explanation
Accompanying drawing 1 is the carborundum JFET grid structural representation with rectification.
Accompanying drawing 2 is that the present invention is for the schematic diagram in A silicon carbide device structure.
Accompanying drawing 3 is that the present invention is for the schematic diagram in B silicon carbide device structure.
Accompanying drawing 4 is that the present invention is for the schematic diagram in C silicon carbide device structure.
Accompanying drawing 5 is that the present invention is for the schematic diagram in D silicon carbide device structure.
Accompanying drawing 6 is that gate turn-on voltage brings up to the schematic diagram of 6V from 2V.
Accompanying drawing 7 is the carborundum JFET mutual conductance test result schematic diagrames adopting honeycomb screen structure.
In figure 1 is the first conductive type layer, 2 is first conductivity type substrate, 3 is channel regions, 4 is drain electrodes, 5 is source electrodes, 6 is gate regions, 7 is gate contact zones of the second conduction type, 8 is gate electrodes, 9 is A drift regions, 10 is A substrates, 11 is A channel regions, 12 is ohmic contact regions, A source, 13 is A drain electrodes, 14 is A source electrodes, 15 is A gate regions, 16 is A gate contact zones, 17 is A gate electrodes, 18 is B drift regions, 19 is B substrates, 20 is B channel regions, 21 is B source electrode ohmic contact regions, 22 is B drain electrodes, 23 is B source electrodes, 24 is B gate regions, 25 is B gate contact zones, 26 is B gate regions, 27 is B gate contact zones, 28 is B gate electrodes, 29 is C drift layers, 30 is C substrates, 31 is C channel regions, 32 is C source electrode ohmic contact regions, 33 is C drain electrodes, 34 is C gate regions, 35 is C gate contact zones, 36 is C gate electrodes, 37 is C source electrodes, 38 is D gate regions, 39 is D substrates, 40 is D channel regions, 41 is that D leaks contact nurse district, Europe, 42 is D drain electrodes, 43 is D gate regions, 44 is D gate contact zones, 45 is D gate electrodes, 46 is D source electrode ohmic contact regions, 47 is D source electrodes, 48 is D gate contact zones, 49 is D gate electrodes.
Embodiment
There is a preparation method for the carborundum JFET grid structure of rectified action, comprise following processing step:
1) in the first conductivity type substrate 2, the first conductive type layer 1 is grown;
2) inject by two groups gate contact zone 7 and gate regions 6 two parts of being formed respectively and having the second conduction type, gate regions 6 forms PN junction respectively with the drift region 1 and channel region 3 with the first conduction type;
3) source electrode 5 and channel region 3 and the ohmic contact between drain electrode 4 and the first conductivity type substrate 2 is realized by ohmic contact annealing;
4) between gate electrode 8 and the gate contact zone 7 of the second conduction type, honeycomb screen contact is formed by the annealing of rectification gate contact.
The cut-in voltage of described honeycomb screen can be controlled in 2V-20V.
Described first conduction type is N-shaped, and wherein the second conduction type is p-type.
Described surface, gate regions 7 has 1 × 1016 to 1 × 1018/cm
3the doping content of individual atom.
Described grid forms the gate contact zone 7 rectification gate contact annealing temperature of gate electrode 8 and the second conduction type 600
oc to 900
oc.
Technical solution of the present invention is further described below in conjunction with accompanying drawing.
As shown in Figure 1, the first conductivity type substrate 2 realizes continuously drift region 1 and channel region 3, the gate contact zone 7 that drift layer 1 passes through injection formation second conduction type and the gate regions 6 of the first conduction type; Gate regions 6 and drift region 1 and channel region 3 forms PN junction simultaneously, between gate electrode 8 and the gate contact zone 7 of the second conduction type by rectification gate contact anneal with gate regions 6 merge the rectifying contact grid realized as shown in Figure 1.
On current is flowed to source electrode 5 by drain electrode 4, channel region 3 part controlled in the gate contact zone 7 through gate regions, left and right 6 and the second conduction type control by grid voltage.
Conventional ohmic contact grid structure is replaced by the gate contact zone 7 of gate electrode 8, second conduction type and the gate regions 6 honeycomb screen structure formed of connecting.
As shown in Figure 2, electric current by A drain electrode 13 by A substrate 10 and A drift region 9 through A channel region 11 arrive ohmic contact regions, A source 12 and A source electrode 14 to be made up of respectively A gate regions 15, A gate contact zone 16 and A gate electrode 17 left and right two parts honeycomb screen structure to A channel region 11 in electric current control.
Structure as shown in Figure 3, electric current reaches B source electrode ohmic contact regions 21 and B source electrode 23 by B substrate 19 and B drift region 18 through B raceway groove 20 by B drain electrode 22.
Part I honeycomb screen structure is formed by B gate regions 24, B gate contact zone 25 and B gate electrode 23.
Part II honeycomb screen structure is formed by B gate regions 26, B gate contact zone 27 and B gate electrode 28.
The Current Control that B channel region 20 is passed through jointly is completed by the first and second partial rectification grid structures.
As shown in Figure 4, electric current reaches C source electrode ohmic contact regions 32 and C source electrode 37 by C substrate 30 and C drift layer 29 through C channel part 31 by C drain electrode 33.
Form left and right two parts honeycomb screen structure respectively by C gate regions 34, C gate contact zone 35 and C gate electrode 36 to control electric current in C channel region 31.
Structure as shown in Figure 5, electric current leaks ohmic contact regions 41 by D drain electrode 42 by D and reaches D source electrode ohmic contact regions 46 and D source electrode 47 through D channel region 40.
Part I honeycomb screen structure is formed by D gate regions 43, D gate contact zone 44 and D gate electrode 45.
Part II honeycomb screen structure is formed by C gate regions 38, E gate contact zone 48 and E gate electrode 49.
The control to electric current in D channel region 40 is jointly completed by the first and second partial rectification grid structures.
Claims (5)
1. there is a preparation method for the carborundum JFET grid structure of rectified action, it is characterized in that comprising following processing step:
1) in the first conductivity type substrate, the first conductive type layer is grown;
2) inject by two groups gate contact zone and gate regions two parts of being formed respectively and having the second conduction type, gate regions forms PN junction respectively with the drift region and channel region with the first conduction type;
3) source electrode and channel region and the ohmic contact between drain electrode and the first conductivity type substrate is realized by ohm annealing;
4) between gate electrode and the gate contact zone of the second conduction type, honeycomb screen contact is formed by the annealing of rectification gate contact.
2. a kind of preparation method with the carborundum JFET grid structure of rectified action as claimed in claim 1, is characterized in that the cut-in voltage of described honeycomb screen can be controlled in 2V-20V.
3. a kind of preparation method with the carborundum JFET grid structure of rectified action as claimed in claim 1, it is characterized in that described first conduction type is N-shaped, and wherein the second conduction type is p-type.
4. a kind of preparation method with the carborundum JFET grid structure of rectified action as claimed in claim 1, is characterized in that described surface, gate contact zone 7 has 1 × 1016 to 1 × 1018/cm
3the doping content of individual atom.
5. a kind of preparation method with the carborundum JFET grid structure of rectified action as claimed in claim 1, is characterized in that described grid forms the gate contact zone rectification gate contact annealing temperature of gate electrode and the second conduction type 600
oc to 900
oc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410657412.2A CN104409335B (en) | 2014-11-18 | 2014-11-18 | A kind of preparation method of the carborundum JFET grid structures with rectification |
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| CN201410657412.2A CN104409335B (en) | 2014-11-18 | 2014-11-18 | A kind of preparation method of the carborundum JFET grid structures with rectification |
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| CN104409335A true CN104409335A (en) | 2015-03-11 |
| CN104409335B CN104409335B (en) | 2017-11-21 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024864A (en) * | 2016-06-28 | 2016-10-12 | 长安大学 | P-trench silicon-carbide static induction thyristor and manufacturing method thereof |
| CN110739349A (en) * | 2019-10-22 | 2020-01-31 | 深圳第三代半导体研究院 | silicon carbide transverse JFET (junction field Effect transistor) device and preparation method thereof |
| CN113410135A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Method for manufacturing anti-radiation junction field effect transistor |
| CN114613861A (en) * | 2022-05-16 | 2022-06-10 | 深圳平创半导体有限公司 | Groove type SiC JFET device and preparation method thereof |
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| CN101124678A (en) * | 2004-12-01 | 2008-02-13 | 半南实验室公司 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making |
| US20080258184A1 (en) * | 2004-07-08 | 2008-10-23 | Igor Sankin | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making |
| CN101317271A (en) * | 2004-12-01 | 2008-12-03 | 半南实验室公司 | Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making |
| US20080308838A1 (en) * | 2007-06-13 | 2008-12-18 | Mcnutt Ty R | Power switching transistors |
| CN102664197A (en) * | 2012-06-05 | 2012-09-12 | 长安大学 | JFET (Junction Field Effect Transistor) and manufacturing method thereof, and micro inverter using JFET |
-
2014
- 2014-11-18 CN CN201410657412.2A patent/CN104409335B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080258184A1 (en) * | 2004-07-08 | 2008-10-23 | Igor Sankin | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making |
| CN101124678A (en) * | 2004-12-01 | 2008-02-13 | 半南实验室公司 | Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making |
| CN101317271A (en) * | 2004-12-01 | 2008-12-03 | 半南实验室公司 | Lateral trench field-effect transistors in wide bandgap semiconductor materials, methods of making |
| US20080308838A1 (en) * | 2007-06-13 | 2008-12-18 | Mcnutt Ty R | Power switching transistors |
| CN102664197A (en) * | 2012-06-05 | 2012-09-12 | 长安大学 | JFET (Junction Field Effect Transistor) and manufacturing method thereof, and micro inverter using JFET |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024864A (en) * | 2016-06-28 | 2016-10-12 | 长安大学 | P-trench silicon-carbide static induction thyristor and manufacturing method thereof |
| CN110739349A (en) * | 2019-10-22 | 2020-01-31 | 深圳第三代半导体研究院 | silicon carbide transverse JFET (junction field Effect transistor) device and preparation method thereof |
| CN113410135A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Method for manufacturing anti-radiation junction field effect transistor |
| CN113410135B (en) * | 2021-06-15 | 2023-06-30 | 西安微电子技术研究所 | Manufacturing method of anti-radiation junction field effect transistor |
| CN114613861A (en) * | 2022-05-16 | 2022-06-10 | 深圳平创半导体有限公司 | Groove type SiC JFET device and preparation method thereof |
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| CN104409335B (en) | 2017-11-21 |
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Application publication date: 20150311 Assignee: YANGZHOU GUOYANG ELECTRONIC CO., LTD. Assignor: No.55 Inst., China Electronic Science and Technology Group Corp. Contract record no.: 2018320000192 Denomination of invention: Preparation method of silicon carbide JFET gate structure with rectification effect Granted publication date: 20171121 License type: Common License Record date: 20181012 |
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