CN104392969A - Impact-resistant packaging structure of multi-chip integrated circuit - Google Patents

Impact-resistant packaging structure of multi-chip integrated circuit Download PDF

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Publication number
CN104392969A
CN104392969A CN201410535314.1A CN201410535314A CN104392969A CN 104392969 A CN104392969 A CN 104392969A CN 201410535314 A CN201410535314 A CN 201410535314A CN 104392969 A CN104392969 A CN 104392969A
Authority
CN
China
Prior art keywords
impact
integrated circuit
sealing
packaging structure
hard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410535314.1A
Other languages
Chinese (zh)
Inventor
夏俊生
邹建安
周峻霖
潘大卓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
No 214 Institute of China North Industries Group Corp
Original Assignee
No 214 Institute of China North Industries Group Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by No 214 Institute of China North Industries Group Corp filed Critical No 214 Institute of China North Industries Group Corp
Priority to CN201410535314.1A priority Critical patent/CN104392969A/en
Publication of CN104392969A publication Critical patent/CN104392969A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

The invention relates to an impact-resistant packaging structure of a multi-chip integrated circuit. The impact-resistant packaging structure is characterized in that bare chips (1) and lead (2) bonding zones are arranged at a substrate (3) in a centralized mode and are placed inside caps (8); soft packaging materials (10) are poured into the caps (8) for sealing; and hard packaging materials (11) are poured into other parts of the integrated circuit inside a housing (12) for sealing. The impact-resistant packaging structure has the following advantages: with pouring and sealing of the soft materials inside the caps, the chips and the lead bonding units can be protected from being damaged under the environment stress, especially the temperature changing stress and the impact-resistant protection effect of the hard pouring and sealing can be realized. On the basis of the cap protection structure, the extrusion effect on the soft materials by the hard materials and the temperature stress effect can be effectively prevented and thus the chips and lead bonding zones can be further protected, thereby improving the product assembling reliability.

Description

A kind of multichip IC shock resistance encapsulating structure
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of multichip IC shock resistance encapsulating structure.
Background technology
Inner embedding is the important means improving hybrid integrated circuit shock resistance level, for ensureing embedding effect, circuit integrity embedding all adopts hard material embedding mode usually, its objective is the high overload impact stress that absorption, distributed circuit internal base plate, element bear, to improve circuit integrity impact resistance.Because overall embedding all adopts hard material, this environmental stress (especially variations in temperature stress) that is potted in acts on lower easily damage wire bonding and chip surface, such as, bonding line fracture, bonding point interconnect failure etc. can be caused, in hybrid integrated circuit, bare chip is more, is easy to cause thus the performance parameter of circuit to lose efficacy.
Summary of the invention
Object of the present invention is exactly to solve existing integrated circuits integral hard material embedding structure, easily damages the shortcoming of wire bonding and chip surface, provide a kind of multichip IC shock resistance encapsulating structure under action of environmental stresses.
To achieve these goals, the present invention adopts following technical scheme
A kind of multichip IC shock resistance encapsulating structure, the substrate comprising housing and wherein connect, is characterized in that:
A, by bare chip and wire bonding district centralized arrangement on substrate;
B, employing pottery or metal nut cap are bonded in substrate surface, and make bare chip and wire bonding district insert block inside, block top has aperture;
The soft encapsulating material of embedding in c, block;
Integrated circuit other parts overall embedding hard encapsulating material in d, housing.
In technique scheme, described hard encapsulating material is prior art, typically epoxy resin.Described soft encapsulating material, typically sulphurated siliastic.
The invention has the advantages that:
(1) have employed compound embedding mode, on the one hand, local soft material embedding can protect IC and wire bonding injury-free under environmental stress (especially variations in temperature stress); On the other hand, the defense of resistance to impact effect of overall hard embedding can be played again.
(2) operator guards of blocking a shot can effectively prevent hard material on the extruding impact of soft material and temperature stress impact, chip and wire bonding is further protected, improves the assembling reliability of product.
Accompanying drawing explanation
Fig. 1 is multichip IC substrate surface of the present invention assembling vertical view;
Fig. 2 is IC interior embedding structural representation in Fig. 1.
Embodiment
(1) as shown in Figure 1, first by bare chip 1 and lead-in wire 2 bonding region centralized arrangement in the middle part of circuit substrate 3, in bare chip bonding region periphery reserved block adhesion zone 4.Lead-in wire 2 bonding completed between bare chip 1 and substrate 3 is assembled, substrate 3 and outer casing base 12 is assembled, electrical connection between substrate and package lead 5, and on substrate, other element 6 is assembled.Wherein, substrate 3 and package lead 5 adopt conventional cover mounting interconnection mode, and namely substrate 3 edge is provided with through hole, package lead 5 through through hole, and with electric conducting material 7(conductive epoxy or solder etc.) realize the interconnection of lead-in wire and via pad in bore periphery.
(2) make the block 8 of box body structure, block top has aperture 9, the rigid materials such as cap material useful ceramics or metal.With adhesives 13, block is bonded on the position, adhesion zone 4 of bare chip bonding region periphery, makes bare chip and wire bonding thereof be placed in block inner.
(3) with the aperture 9 of the mode such as continuous drip or injection by blocking a shot above, soft material 10 being injected in block (described soft encapsulating material, typically sulphurated siliastic), after solidification, namely completing embedding in block.And then carry out overall embedding by circuit other parts in hard material 11 pairs of shells 12.
(4) the product casing end face of this embedding structure can seal, and also can not seal.

Claims (1)

1. a multichip IC shock resistance encapsulating structure, the substrate (3) comprising housing (12) and wherein connect, is characterized in that:
A, by bare chip (1) and lead-in wire (2) bonding region centralized arrangement on substrate (3);
B, employing pottery or metal nut cap (8) are bonded in substrate surface, and make bare chip and wire bonding district insert block inside, block (8) top has aperture (9);
C, the soft encapsulating material of block (8) interior embedding (10);
Overall embedding hard encapsulating material (11) of the interior integrated circuit other parts of d, housing (12).
CN201410535314.1A 2014-10-13 2014-10-13 Impact-resistant packaging structure of multi-chip integrated circuit Pending CN104392969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410535314.1A CN104392969A (en) 2014-10-13 2014-10-13 Impact-resistant packaging structure of multi-chip integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410535314.1A CN104392969A (en) 2014-10-13 2014-10-13 Impact-resistant packaging structure of multi-chip integrated circuit

Publications (1)

Publication Number Publication Date
CN104392969A true CN104392969A (en) 2015-03-04

Family

ID=52610845

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410535314.1A Pending CN104392969A (en) 2014-10-13 2014-10-13 Impact-resistant packaging structure of multi-chip integrated circuit

Country Status (1)

Country Link
CN (1) CN104392969A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331499A (en) * 2017-06-30 2017-11-07 深圳市崧盛电子股份有限公司 The encapsulating method and embedding circuit structure of circuit structure
CN110600432A (en) * 2019-05-27 2019-12-20 华为技术有限公司 Packaging structure and mobile terminal
CN111622747A (en) * 2020-05-14 2020-09-04 中国科学院地质与地球物理研究所 Receiving transducer array full digitalization device of acoustic logging while drilling instrument
CN114554718A (en) * 2022-03-21 2022-05-27 四川九洲空管科技有限责任公司 Filling and sealing process for arranging mounting plate in shell with only exposed contact pin

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567708A (en) * 1991-09-09 1993-03-19 Seiko Epson Corp Packaging method for semiconductor integrated circuit
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5585600A (en) * 1993-09-02 1996-12-17 International Business Machines Corporation Encapsulated semiconductor chip module and method of forming the same
US5793118A (en) * 1994-05-26 1998-08-11 Nec Corporation Semiconductor device capable of accomplishing a high moisture proof
CN1342035A (en) * 2000-09-04 2002-03-27 三洋电机株式会社 Circuit device and its manufacturing method
CN1352804A (en) * 1999-05-18 2002-06-05 阿梅拉西亚国际技术公司 High-density electronic package and method for making same
CN1455960A (en) * 2001-01-24 2003-11-12 日亚化学工业株式会社 Light emitting diode, optical semiconductor element and epoxy resin composition suitable for optical semiconductor element and production methods therefor
CN1581482A (en) * 2003-07-31 2005-02-16 三洋电机株式会社 Circuit moudel
CN101552264A (en) * 2008-02-27 2009-10-07 英飞凌科技股份有限公司 Power module
CN102405523A (en) * 2009-04-21 2012-04-04 罗伯特·博世有限公司 Encapsulated circuit device for substrates with absorption layer and method for producing the same
CN103066192A (en) * 2013-01-10 2013-04-24 李刚 Semiconductor illuminating light source and method of manufacturing the same and semiconductor illuminating chip
CN103219446A (en) * 2012-01-20 2013-07-24 日亚化学工业株式会社 Molded package and light emitting device
CN203351591U (en) * 2013-07-23 2013-12-18 长兴芯亿微电子科技有限公司 Flexible substrate packaging structure
CN203398110U (en) * 2013-07-03 2014-01-15 叶逸仁 LED light source combination of fixed-type and fixed-specification packaging

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567708A (en) * 1991-09-09 1993-03-19 Seiko Epson Corp Packaging method for semiconductor integrated circuit
US5386342A (en) * 1992-01-30 1995-01-31 Lsi Logic Corporation Rigid backplane formed from a moisture resistant insulative material used to protect a semiconductor device
US5585600A (en) * 1993-09-02 1996-12-17 International Business Machines Corporation Encapsulated semiconductor chip module and method of forming the same
US5793118A (en) * 1994-05-26 1998-08-11 Nec Corporation Semiconductor device capable of accomplishing a high moisture proof
CN1352804A (en) * 1999-05-18 2002-06-05 阿梅拉西亚国际技术公司 High-density electronic package and method for making same
CN1342035A (en) * 2000-09-04 2002-03-27 三洋电机株式会社 Circuit device and its manufacturing method
CN1455960A (en) * 2001-01-24 2003-11-12 日亚化学工业株式会社 Light emitting diode, optical semiconductor element and epoxy resin composition suitable for optical semiconductor element and production methods therefor
CN1581482A (en) * 2003-07-31 2005-02-16 三洋电机株式会社 Circuit moudel
CN101552264A (en) * 2008-02-27 2009-10-07 英飞凌科技股份有限公司 Power module
CN102405523A (en) * 2009-04-21 2012-04-04 罗伯特·博世有限公司 Encapsulated circuit device for substrates with absorption layer and method for producing the same
CN103219446A (en) * 2012-01-20 2013-07-24 日亚化学工业株式会社 Molded package and light emitting device
CN103066192A (en) * 2013-01-10 2013-04-24 李刚 Semiconductor illuminating light source and method of manufacturing the same and semiconductor illuminating chip
CN203398110U (en) * 2013-07-03 2014-01-15 叶逸仁 LED light source combination of fixed-type and fixed-specification packaging
CN203351591U (en) * 2013-07-23 2013-12-18 长兴芯亿微电子科技有限公司 Flexible substrate packaging structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331499A (en) * 2017-06-30 2017-11-07 深圳市崧盛电子股份有限公司 The encapsulating method and embedding circuit structure of circuit structure
CN110600432A (en) * 2019-05-27 2019-12-20 华为技术有限公司 Packaging structure and mobile terminal
CN111622747A (en) * 2020-05-14 2020-09-04 中国科学院地质与地球物理研究所 Receiving transducer array full digitalization device of acoustic logging while drilling instrument
CN114554718A (en) * 2022-03-21 2022-05-27 四川九洲空管科技有限责任公司 Filling and sealing process for arranging mounting plate in shell with only exposed contact pin
CN114554718B (en) * 2022-03-21 2023-10-24 四川九洲空管科技有限责任公司 Filling and sealing process for mounting plate in shell with only contact pins exposed

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Application publication date: 20150304

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