CN104377160B - Metal interconnector structure and process thereof - Google Patents
Metal interconnector structure and process thereof Download PDFInfo
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- CN104377160B CN104377160B CN201310353503.2A CN201310353503A CN104377160B CN 104377160 B CN104377160 B CN 104377160B CN 201310353503 A CN201310353503 A CN 201310353503A CN 104377160 B CN104377160 B CN 104377160B
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Abstract
The invention discloses a metal interconnector process. The process includes the steps that a first dielectric layer is formed on a substrate, and a conductor plug is formed in the first dielectric layer; a second dielectric layer is formed on the first dielectric layer, and a dielectric layer window opening is formed in the second dielectric layer; a lining layer is formed on the surface of the second dielectric layer and on the side walls and the bottom of the dielectric layer window opening; the dielectric layer window opening is filled with a filling layer; a third dielectric layer is formed on the lining layer; a self-alignment dual metal embedment structure is formed, penetrates through the third dielectric layer, the filling layer in the dielectric layer window opening and the lining layer and is electrically connected with the conductor plug. The invention further discloses a metal interconnector. Process steps can be reduced, process margin is improved, the coupling problem between a bit line and a grid conductor can be solved, the limit of photoetching critical dimension is overcome, nesting margin is improved, and product cost is lowered.
Description
Technical field
The present invention relates to a kind of metal interconnecting structure and its technique.
Background technology
Metal interconnecting can be used to connect different elements, and very important role is played the part of in semiconductor processing.With
Electronic product is constantly minimized, and required component size is more and more little.However, being limited to the critical of existing exposure bench
The limit of size, the interlayer hole opening of little critical dimension is difficult to make.The size for being additionally, since interlayer hole opening is little, is inserted
Oxide layer easily forms hole in oxide layer, and the interlayer hole for causing to be subsequently formed occurs the problem of lateral conducting.The opposing party
Face, although carry out cvd silicon oxide using high density plasma deposition method and contribute to silica smoothly fill in interlayer hole opening
In, but carry out cvd silicon oxide using high density plasma deposition method, the corner that interlayer hole opening is easily caused again is cut,
Thus the critical dimension of derivative interlayer hole opening is uncontrollable, even results in and connect in the follow-up metal formed in interlayer hole opening
The problem that line (e.g. bit line) is short-circuited with adjacent metal interconnecting (e.g. bit line).
The content of the invention
It is an object of the invention to provide a kind of metal interconnecting structure and its technique, can save processing step, increase work
Skill nargin, improves the coupled problem between grid conductor, overcomes the limit of lithographic critical dimension, lifts the nargin of alignment, reduces
The cost of product.
The embodiment of the present invention proposes a kind of metal interconnecting technique, including provides substrate, has formed the first dielectric on substrate
Layer, and formed conductive plugs in the first dielectric layer.The second dielectric layer is formed on the first dielectric layer, and in the second dielectric layer
Form interlayer hole opening.Lining is formed in the side wall of the surface of the second dielectric layer and interlayer hole opening with bottom.In interlayer hole
Packed layer is inserted in opening.The 3rd dielectric layer is formed on lining.Autoregistration double-metal inlaid structure is formed, autoregistration is dual
Metal damascene structure is electrically connected through packed layer and lining in the 3rd dielectric layer and interlayer hole opening with conductive plugs.
According to described in the embodiment of the present invention, wherein being formed in the second dielectric layer before the first interlayer hole opening, also include
Stop-layer is formed on the second dielectric layer.
According to described in the embodiment of the present invention, also including the wire formed through the 3rd dielectric layer, lining and stop-layer.
According to described in the embodiment of the present invention, wherein forming the method bag of autoregistration double-metal inlaid structure and wire
Include：Hard mask layer is formed on the 3rd dielectric layer, there is hard mask layer one of multiple patterns of openings, patterns of openings to be situated between positioned at first
Layer window overthe openings；With hard mask layer as mask, technique is etched, to form the first irrigation canals and ditches and autoregistration double metal edge
Embedding opening, wherein the first irrigation canals and ditches pass through the 3rd dielectric layer, lining and stop-layer, autoregistration dual-metal inserting opening is through the
Packed layer and lining in three dielectric layers and the first interlayer hole opening, exposes conductive plugs；And in the first irrigation canals and ditches shape
Into wire, and autoregistration double-metal inlaid structure is formed in autoregistration dual-metal inserting opening.
According to described in the embodiment of the present invention, wherein lining is identical with the material of stop-layer.
According to described in the embodiment of the present invention, the wherein material of lining and stop-layer includes silicon nitride, the second dielectric layer with
And the material of packed layer includes silica.
According to described in the embodiment of the present invention, wherein the forming method of lining includes atomic layer deposition method.
According to the embodiment of the present invention, wherein forming the method bag of the first irrigation canals and ditches and autoregistration dual-metal inserting opening
Include：With hard mask layer as mask, lining is etching stopping layer, the 3rd dielectric layer is removed with the etching of the first etching condition, with the
The first irrigation canals and ditches and the second irrigation canals and ditches are formed in three dielectric layers, the second irrigation canals and ditches expose packed layer；With hard mask layer as mask, lining is
Etching stopping layer, with the etching of the second etching condition packed layer is removed, to form the second interlayer hole opening connected with the second irrigation canals and ditches；
And with hard mask layer as mask, the lining and stop-layer and the second interlayer below irrigation canals and ditches is removed with the etching of the 3rd etching condition
Lining below window opening, the second irrigation canals and ditches and the second interlayer hole opening composition autoregistration dual-metal inserting opening.
The embodiment of the present invention also proposes a kind of metal interconnecting structure, including substrate, the first dielectric layer, conductive plugs,
Two dielectric layers, the 3rd dielectric layer, autoregistration double-metal inlaid structure and lining.First dielectric layer is located on substrate.Conductor
Connector is located in the first dielectric layer.Second dielectric layer is located on the first dielectric layer.3rd dielectric layer is located on the second dielectric layer.From
Alignment double-metal inlaid structure is electrically connected through the 3rd dielectric layer and the second dielectric layer with conductive plugs.Lining is located at certainly
Between alignment double-metal inlaid structure and the second dielectric layer and between the 3rd dielectric layer and the second dielectric layer.
According to the embodiment of the present invention, also include the stop-layer being located between the second dielectric layer and lining.
According to the embodiment of the present invention, also include the packed layer being located between lining and autoregistration double-metal inlaid structure.
According to the embodiment of the present invention, wherein lining is identical with the material of stop-layer.
According to the embodiment of the present invention, the wherein material of lining and stop-layer includes silicon nitride, the second dielectric layer and fills out
Filling the material of layer includes silica.
The metal interconnecting structure and its technique of the embodiment of the present invention, can save processing step, increase process margin, change
Coupled problem between kind grid conductor, overcomes the limit of lithographic critical dimension, lifts the nargin of alignment, reduce product into
This.
It is that the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Description of the drawings
Figure 1A to 1I is the manufacturing process of a kind of embedded memory element according to depicted in first embodiment of the invention
Generalized section.
Wherein, description of reference numerals is as follows：
10：Substrate 30：Encapsulant layer
11：Conduction region 30a：Packed layer
12、16、34：Dielectric layer 32：Hole
14：Conductive plugs 36：Hard mask layer
18：Stop-layer 40,41：Irrigation canals and ditches
20：Bottom anti-reflecting layer 42：Autoregistration dual-metal inserting opening
22：Mask layer 44：Wire
24、38：Opening irrigation canals and ditches pattern 45：Conductor layer
26、43：Interlayer hole opening 46：Autoregistration double-metal inlaid structure
28：Lining
Specific embodiment
Figure 1A to 1I is the section of the manufacturing process of the embedded memory element according to depicted in first embodiment of the invention
Schematic diagram.
Refer to Figure 1A, there is provided substrate 10.Substrate 10 can be semiconductor or semiconducting compound, e.g. silicon or
Germanium silicide.Substrate 10 can also be silicon on insulating barrier (SOI).There is conduction region 11 in substrate 10.Conduction region 11 e.g. adulterates
Area or conductive layer.
Dielectric layer 12 is formed over the substrate 10.The material of dielectric layer 12 is, for example, silica, and the method for formation is e.g. changed
Learn vapour deposition process.The thickness of dielectric layer 12 is, for example, 4000 angstroms to 5000 angstroms.Conductive plugs 14 are formed in dielectric layer 12.Lead
The material of body connector 14 can be metal, e.g. tungsten.Conductive plugs 14 are, for example, bit line contacting window.
Then, dielectric layer 16 is formed on the dielectric layer 12.The material of dielectric layer 16 is, for example, silica, the method example of formation
Chemical vapour deposition technique in this way.The thickness of dielectric layer 16 is, for example, 1000 angstroms to 2000 angstroms.Afterwards, formed on dielectric layer 16 and stopped
Only layer 18.The material of stop-layer 18 is different from the material of dielectric layer 16.The material of stop-layer 18 is, for example, silicon nitride, the side of formation
Method is, for example, as reacting gas, to be deposited using chemical vapour deposition technique with silicomethane, and thickness is, for example, 100 angstroms to 600 angstroms.
Afterwards, mask layer 22 is formed on stop-layer 18.There is patterns of openings 24 corresponding to conductive plugs 14 in mask layer 22.Mask
The material of layer 22 is, for example, photoresist.Bottom antireflection (BARC) can be initially formed on stop-layer 18 before mask layer 22 is formed
Layer 20.The material of bottom anti-reflecting layer 20 be, for example, organic polymer or carbon silicon oxynitride, the method for formation is, for example, liquid spin coating
Method, thickness is, for example, 200 angstroms to 400 angstroms.
Figure 1B is refer to, with mask layer 22 (Figure 1A) as mask, removal stop layer 18 and dielectric layer 16 is etched, to form Jie
Layer window opening 26, exposes conductive plugs 14.Mask layer 22 and bottom anti-reflecting layer 20 are removed afterwards.Etching removal stop layer 18
Can be anisotropic etch process with the method for dielectric layer 16, e.g. reactive ion etching method.Then, for example with oxonium ion etc.
Gas ions remove mask layer 22 and bottom anti-reflecting layer 20.
Afterwards, lining 28 is formed on dielectric layer 16, side wall of the stop-layer 18 with interlayer hole opening 26 and bottom is covered.Lining
The material of layer 28 is different from dielectric layer 16.The material of lining 28 can be identical with stop-layer 18.The material of lining 28 is, for example, nitrogen
SiClx, the method for formation is, for example, atomic layer deposition method, and thickness is, for example, 50 angstroms to 150 angstroms.Lining 28 can be used to reduce interlayer
The size of window opening 26, and the side of interlayer hole opening 26 is protected during autoregistration dual-metal inserting opening is subsequently formed
Wall.
Fig. 1 C are refer to, then, encapsulant layer 30 is formed on lining 28 and in interlayer hole opening 26.Packing material
The material of layer 30 is different from lining 28.The material of encapsulant layer 30 is, for example, silica, and the method for formation is, for example, chemical gas
Phase sedimentation.The size of interlayer hole opening 26 reduces because of lining 28, and encapsulant layer 30 may be caused to fill up interlayer
Window opening 26, and form hole 32.However, because the side wall of each interlayer hole opening 26 is surrounded by the lining 28 of different materials,
Therefore, the hole 32 in each interlayer hole opening 26 is not connected each other, and as lining in follow-up etching process
28 with the material of dielectric layer 16 on difference and avoid the problem of lateral communication.
Thereafter, Fig. 1 D are refer to, the encapsulant layer 30 of the top of lining 28 is removed, stayed in interlayer hole opening 26 and fill out
Fill a layer 30a.The method for removing the encapsulant layer 30 on lining 28 is, for example, with lining 28 as polish stop layer, using change
Learn mechanical milling method to remove it.After the encapsulant layer 30 for removing the top of lining 28, it is also possible to selective by stop-layer
The lining 28 of 18 tops is removed.
Afterwards, dielectric layer 34 is formed on lining 28 and packed layer 30a.The material of dielectric layer 34 is, for example, silica or low
Dielectric constant material is, for example, carborundum, and the method for formation is, for example, chemical vapour deposition technique.The thickness of dielectric layer 34 is, for example,
500 angstroms to 2500 angstroms.
Thereafter, hard mask layer 36 is formed on dielectric layer 34.Hard mask layer 36 has multiple opening irrigation canals and ditches patterns 38, wherein
There is an opening irrigation canals and ditches pattern 38 to be located at the top of interlayer hole opening 26, and it is corresponding with interlayer hole opening 26.The material of hard mask layer 36
E.g. polysilicon, carbon or silicon oxynitride.The forming method of polysilicon is, for example, chemical vapour deposition technique.Opening irrigation canals and ditches pattern 38
Forming method can be by photoetching and etch process.
Then, Fig. 1 G are refer to, with hard mask layer 36 as mask, technique is etched, forms irrigation canals and ditches 40 and from right
Quasi- dual-metal inserting opening 42.Irrigation canals and ditches 40 pass through dielectric layer 34, lining 28 and stop-layer 18.Autoregistration dual-metal inserting
Opening 42 exposes conductive plugs 14 through the packed layer 30a in dielectric layer 34 and interlayer hole opening 26 and lining 28.Adopted
Etch process can be anisotropic etching process, e.g. reactive ion etching process.
Fig. 1 E are refer to, in one embodiment, above-mentioned formation irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42 can
With elder generation with hard mask layer 36 as mask, using lining 28 as etching stopping layer, select for the lining 28 of dielectric layer 34/ or right
The the first etching condition etching for having high etching selectivity in the stop-layer 18 of dielectric layer 34/ removes dielectric layer 34, to form irrigation canals and ditches
40 and irrigation canals and ditches 41.When being etched with the first etching condition, because the first etching condition is for the lining 28 of dielectric layer 34/ or right
There is high etching selectivity in the stop-layer 18 of dielectric layer 34/, therefore, during etching, lining 28 and stop-layer 18 can be with
As etching stopping layer, the surface of dielectric layer 16 is protected.
Then, Fig. 1 F are refer to, with hard mask layer 36 as mask, lining 28 is stop-layer, changes etching condition, and it is right to select
In packed layer 30a/ linings 28 or for the second etching condition that packed layer 30a/ stop-layers 18 have high etching selectivity loses
Packed layer 30a is removed quarters, to form interlayer hole opening 43.Due to having hole 32 among packed layer 30a, therefore open in interlayer hole
The material volume of packed layer 30a is less among mouth 43, can be completely removed more quickly, therefore, hard mask layer 36 can be mitigated
Consumption, it is not necessary to too thick hard mask layer 36 is avoiding being consumed totally during etching.Additionally, with the second erosion
During quarter condition etching, because packed layer 30a/ linings 28 or packed layer 30a/ stop-layers 18 have high etching selectivity, therefore
Lining 28 as protective layer, can protect side wall and the surface of dielectric layer 16, and with autoregistration filling out for interlayer hole opening 26 is removed
A layer 30a is filled, the side wall without damaging dielectric layer 16.And when being etched with the second etching condition, the lining of the lower section of irrigation canals and ditches 40
28 or stop-layer 18 can as stop-layer, protect dielectric layer 16 surface.
Afterwards, Fig. 1 G are refer to, is selected for the dielectric layer 16 of lining 28/ or the dielectric layer 16 of stop-layer 18/ have high etching
The 3rd etching condition etching for selecting ratio is removed below the lining 28 and stop-layer 18, and interlayer hole opening 43 of the lower section of irrigation canals and ditches 40
Lining 28.When being etched with the 3rd etching condition, the 3rd etching condition is for the dielectric layer 16 of lining 28/ or for stop-layer 18/
Dielectric layer 16 has high etching selectivity, therefore removes irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42 etching is continued
When the lining 28 at place is with stop-layer 18, also will not over etching dielectric layer 16 below.43 groups of irrigation canals and ditches 41 and interlayer hole opening
Into autoregistration dual-metal inserting opening 42.Due to self aligned autoregistration dual-metal inserting opening 42 can be formed, therefore,
There is good alignment between autoregistration dual-metal inserting opening 42 and the interlayer hole opening 26 and conductive plugs 14 of lower section
Nargin.
Afterwards, Fig. 1 H are refer to, hard mask layer 36 is removed.Afterwards, conductor layer 45 is formed on dielectric layer 34, to fill up ditch
Canal 40 and autoregistration dual-metal inserting opening 42.The material of conductor layer 45 is, for example, tungsten or copper.In one embodiment, conductor
Layer 45 is tungsten metal level, and before tungsten metal level is formed, first in irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42
Form adhesion layer (not illustrating).The material of adhesion layer is, for example, titanium nitride.In another embodiment, conductor layer 45 is copper metal
Layer, and before copper metal layer is formed, first form barrier layer in irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42.Resistance
The material of barrier layer is, for example, tantalum nitride.
Fig. 1 I are refer to, conductor layer 45 unnecessary on dielectric layer 34 is removed, to form wire 44 in irrigation canals and ditches 40, and in certainly
Autoregistration double-metal inlaid structure 46 is formed in alignment dual-metal inserting opening 42, to electrically connect with conductive plugs 14.Move
Except the method for conductor layer 45 unnecessary on dielectric layer 34 is, for example, chemical mechanical milling method.In one embodiment, autoregistration is dual
Metal damascene structure 46 is as bit line.Because lining 28 can protect the side wall of interlayer hole opening 26 so that each interlayer hole opening
Hole 32 in 26 is not connected each other, therefore, after autoregistration double-metal inlaid structure 46 is formed, autoregistration double metal
Mosaic texture 46 also will not have each other the problem of short circuit because of hole 32.
Refer to Fig. 1 I, the metal interconnecting structure of the embodiment of the present invention, including substrate 10, dielectric layer 12, conductive plugs
14th, dielectric layer 16, dielectric layer 34, autoregistration double-metal inlaid structure 46 and lining 28.Dielectric layer 12 is located on substrate 10.
Conductive plugs 14 are located in dielectric layer 12.Dielectric layer 16 is located on dielectric layer 12.Dielectric layer 34 is located on dielectric layer 16.Autoregistration
Double-metal inlaid structure 46 is electrically connected through dielectric layer 34 and dielectric layer 16 with conductive plugs 14.Lining 28 is located at from right
Between quasi- double-metal inlaid structure 46 and dielectric layer 16 and between dielectric layer 34 and dielectric layer 16.Furthermore, in dielectric layer 16
Also include stop-layer 18 between lining 28.Additionally, in one embodiment, in lining 28 and autoregistration double-metal inlaid structure
Also include packed layer 30a between 46.In addition, metal interconnecting structure also include wire 44, its pass through dielectric layer 34, lining 28 with
And stop-layer 18.
In the present embodiment, dielectric layer 16 is formed directly on dielectric layer 12, is not had between dielectric layer 16 and dielectric layer 12
Other high-k material layers, e.g. silicon nitride, the step of not only can save deposition, can also improve bit line and grid
The problem coupled between conductor.
Furthermore, lining 28 is formed in the side wall of the surface of dielectric layer 16 and interlayer hole opening 26, interlayer hole can be protected
The side wall and corner of opening 26, forms self aligned autoregistration dual-metal inserting opening 42, can overcome lithographic critical dimension
The limit and high-density plasma (HDP) oxide layer caused by corner damage problem.
Further, since the side wall of interlayer hole opening 26 is covered by lining 28, therefore, even if the filling in interlayer hole opening 26
Layer 30a has hole 32, does not also result in the problem that the autoregistration double-metal inlaid structure 46 being subsequently formed laterally is turned on.And
And, the packed layer 30a in interlayer hole opening 26 has hole 32 to contribute to packed layer 30a on the contrary can be more rapidly removed, therefore
Consumption of the hard mask layer on etch process can be reduced.
Furthermore, due to self aligned autoregistration dual-metal inserting opening 42 can be formed, therefore, autoregistration double metal
Inlay and have between opening 42 and interlayer hole opening 26 below and conductive plugs 14 good alignment nargin.Additionally, this
Invention example replaces single mosaic technology, the cost of product to save 2～3% with dual-damascene technics.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any people in the art
Member, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore protection scope of the present invention is when regarding
What appended claim was defined is defined.
Claims (13)
1. a kind of metal interconnecting technique, it is characterised in that include：
Substrate is provided, has been formed on the substrate in the first dielectric layer, and first dielectric layer and has been formed conductive plugs；
The second dielectric layer is formed on first dielectric layer；
The first interlayer hole opening is formed in second dielectric layer；
Lining is formed in the side wall of the surface of second dielectric layer and the first interlayer hole opening with bottom；
Packed layer is inserted in the first interlayer hole opening；
The 3rd dielectric layer is formed on the lining；And
Formed autoregistration double-metal inlaid structure, the autoregistration double-metal inlaid structure through the 3rd dielectric layer with
And the packed layer in the first interlayer hole opening and the lining, electrically connect with the conductive plugs.
2. metal interconnecting technique as claimed in claim 1, wherein form the first interlayer hole in second dielectric layer opening
Before mouthful, also it is included on second dielectric layer and forms stop-layer.
3. metal interconnecting technique as claimed in claim 2, also including formed through the 3rd dielectric layer, the lining with
And the wire of the stop-layer.
4. metal interconnecting technique as claimed in claim 3, wherein formed the autoregistration double-metal inlaid structure and
The method of the wire includes：
Hard mask layer is formed on the 3rd dielectric layer, the hard mask layer has multiple patterns of openings, the patterns of openings
One of be located at the first interlayer hole overthe openings；
With the hard mask layer as mask, technique is etched, is opened with forming the first irrigation canals and ditches and autoregistration dual-metal inserting
Mouthful, wherein first irrigation canals and ditches pass through the 3rd dielectric layer, the lining and the stop-layer, the dual gold of the autoregistration
Category inlays opening through the packed layer and the lining in the 3rd dielectric layer and the first interlayer hole opening, naked
Expose the conductive plugs；And
Form the wire in first irrigation canals and ditches, and form described from right in the autoregistration dual-metal inserting opening
Quasi- double-metal inlaid structure.
5. metal interconnecting technique as claimed in claim 2, wherein the lining is identical with the material of the stop-layer.
6. metal interconnecting technique as claimed in claim 5, wherein the material of the lining and the stop-layer includes nitrogen
The material of SiClx, second dielectric layer and the packed layer includes silica.
7. metal interconnecting technique as claimed in claim 6, wherein the forming method of the lining includes atomic layer deposition method.
8. metal interconnecting technique as claimed in claim 4, wherein forming first irrigation canals and ditches and the autoregistration is dual
The method of damascene opening includes：
With the hard mask layer as mask, the lining is etching stopping layer, and with the etching of the first etching condition the described 3rd is removed
Dielectric layer, to form first irrigation canals and ditches and the second irrigation canals and ditches in the 3rd dielectric layer, second irrigation canals and ditches expose described
Packed layer；
With the hard mask layer as mask, the lining is etching stopping layer, and with the etching of the second etching condition the filling is removed
Layer, to form the second interlayer hole opening connected with second irrigation canals and ditches；And
With the hard mask layer as mask, stopped with described with the lining that the etching of the 3rd etching condition is removed below the irrigation canals and ditches
The only lining below layer and the second interlayer hole opening, second irrigation canals and ditches are constituted with the second interlayer hole opening
The autoregistration dual-metal inserting opening.
9. a kind of metal interconnecting structure, it is characterised in that include：
Substrate；
First dielectric layer, on the substrate；
Conductive plugs, in being embedded in first dielectric layer；
Second dielectric layer, on first dielectric layer；
3rd dielectric layer, on second dielectric layer；
Autoregistration double-metal inlaid structure, through the 3rd dielectric layer and second dielectric layer, inserts with the conductor
Plug electrical connection；And
Lining, between the autoregistration double-metal inlaid structure and second dielectric layer and the 3rd dielectric layer
Between second dielectric layer.
10. metal interconnecting structure as claimed in claim 9, also includes being located between second dielectric layer and the lining
Stop-layer.
11. metal interconnecting structures as claimed in claim 10, also include being located at the lining and the dual gold of the autoregistration
Packed layer between category mosaic texture.
12. metal interconnecting structures as claimed in claim 11, wherein the lining is identical with the material of the stop-layer.
13. metal interconnecting structures as claimed in claim 11, wherein the material of the lining and the stop-layer includes
The material of silicon nitride, second dielectric layer and the packed layer includes silica.
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| CN201310353503.2A CN104377160B (en) | 2013-08-14 | 2013-08-14 | Metal interconnector structure and process thereof |
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| CN104377160B true CN104377160B (en) | 2017-05-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10854505B2 (en) * | 2016-03-24 | 2020-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Removing polymer through treatment |
| CN109300875B (en) * | 2017-07-24 | 2020-11-10 | 旺宏电子股份有限公司 | Interconnect structure and method of fabricating the same |
| KR102451417B1 (en) * | 2018-04-26 | 2022-10-06 | 삼성전자주식회사 | Semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6171963B1 (en) * | 1998-11-30 | 2001-01-09 | Worldwide Semiconductor Manufacturing Corporation | Method for forming a planar intermetal dielectric using a barrier layer |
| CN1815711A (en) * | 2005-01-31 | 2006-08-09 | 台湾积体电路制造股份有限公司 | Interconnect structure and method of forming the same |
| CN1835206A (en) * | 2005-02-05 | 2006-09-20 | 三星电子株式会社 | Method of forming double-setting line arrange for semiconductor device using protective access cover layer |
| CN101425500A (en) * | 2007-11-01 | 2009-05-06 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW546771B (en) * | 2002-05-13 | 2003-08-11 | Nanya Technology Corp | Manufacturing method of dual damascene structure |
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- 2013-08-14 CN CN201310353503.2A patent/CN104377160B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6171963B1 (en) * | 1998-11-30 | 2001-01-09 | Worldwide Semiconductor Manufacturing Corporation | Method for forming a planar intermetal dielectric using a barrier layer |
| CN1815711A (en) * | 2005-01-31 | 2006-08-09 | 台湾积体电路制造股份有限公司 | Interconnect structure and method of forming the same |
| CN1835206A (en) * | 2005-02-05 | 2006-09-20 | 三星电子株式会社 | Method of forming double-setting line arrange for semiconductor device using protective access cover layer |
| CN101425500A (en) * | 2007-11-01 | 2009-05-06 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
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