CN104377160A - Metal interconnector structure and process thereof - Google Patents
Metal interconnector structure and process thereof Download PDFInfo
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- CN104377160A CN104377160A CN201310353503.2A CN201310353503A CN104377160A CN 104377160 A CN104377160 A CN 104377160A CN 201310353503 A CN201310353503 A CN 201310353503A CN 104377160 A CN104377160 A CN 104377160A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Abstract
The invention discloses a metal interconnector process. The process includes the steps that a first dielectric layer is formed on a substrate, and a conductor plug is formed in the first dielectric layer; a second dielectric layer is formed on the first dielectric layer, and a dielectric layer window opening is formed in the second dielectric layer; a lining layer is formed on the surface of the second dielectric layer and on the side walls and the bottom of the dielectric layer window opening; the dielectric layer window opening is filled with a filling layer; a third dielectric layer is formed on the lining layer; a self-alignment dual metal embedment structure is formed, penetrates through the third dielectric layer, the filling layer in the dielectric layer window opening and the lining layer and is electrically connected with the conductor plug. The invention further discloses a metal interconnector. Process steps can be reduced, process margin is improved, the coupling problem between a bit line and a grid conductor can be solved, the limit of photoetching critical dimension is overcome, nesting margin is improved, and product cost is lowered.
Description
Technical field
The present invention relates to a kind of metal interconnecting structure and technique thereof.
Background technology
Metal interconnecting can be used for connecting different elements, plays the part of very important role in semiconductor processing.Along with electronic product is constantly miniaturized, required component size is more and more little.But be limited to the limit of the critical dimension of existing exposure bench, the interlayer hole opening of little critical dimension not easily makes.And because the size of interlayer hole opening is little, oxide layer of inserting easily forms hole in oxide layer, and causes the problem of the interlayer hole generation side direction conducting of follow-up formation.On the other hand, although use high density plasma deposition method to carry out cvd silicon oxide to contribute to silica and can fill in smoothly in interlayer hole opening, but use high density plasma deposition method to carry out cvd silicon oxide, the corner of interlayer hole opening is easily caused again to be cut, thus the critical dimension of derivative interlayer hole opening is uncontrollable, even causes the problem that the follow-up metal interconnecting (being such as bit line) formed in interlayer hole opening and adjacent metal interconnecting (being such as bit line) are short-circuited.
Summary of the invention
The object of this invention is to provide a kind of metal interconnecting structure and technique thereof, can processing step be saved, increase process margin, improve the coupled problem between grid conductor, overcome the limit of lithographic critical dimension, promote the nargin of alignment, reduce the cost of product.
The embodiment of the present invention proposes a kind of metal interconnecting technique, comprises and provides substrate, and substrate has formed the first dielectric layer, and forms conductive plugs in the first dielectric layer.First dielectric layer is formed the second dielectric layer, and form interlayer hole opening in the second dielectric layer.Lining is formed at the sidewall of the surface of the second dielectric layer and interlayer hole opening and bottom.Packed layer is inserted in interlayer hole opening.Lining forms the 3rd dielectric layer.Form autoregistration double-metal inlaid structure, autoregistration double-metal inlaid structure, through the packed layer in the 3rd dielectric layer and interlayer hole opening and lining, is electrically connected with conductive plugs.
Described in the embodiment of the present invention, before wherein forming the first interlayer hole opening in the second dielectric layer, be also included on the second dielectric layer and form stop-layer.
Described in the embodiment of the present invention, also comprise the wire formed through the 3rd dielectric layer, lining and stop-layer.
Described in the embodiment of the present invention, the method wherein forming autoregistration double-metal inlaid structure and wire comprises: on the 3rd dielectric layer, form hard mask layer, hard mask layer has multiple patterns of openings, and one of patterns of openings is positioned at the first interlayer hole overthe openings; Take hard mask layer as mask, carry out etch process, to form the first irrigation canals and ditches and autoregistration dual-metal inserting opening, wherein the first irrigation canals and ditches are through the 3rd dielectric layer, lining and stop-layer, autoregistration dual-metal inserting opening, through the packed layer in the 3rd dielectric layer and the first interlayer hole opening and lining, exposes conductive plugs; And form wire in the first irrigation canals and ditches, and form autoregistration double-metal inlaid structure in autoregistration dual-metal inserting opening.
Described in the embodiment of the present invention, wherein lining is identical with the material of stop-layer.
Described in the embodiment of the present invention, wherein the material of lining and stop-layer comprises silicon nitride, and the material of the second dielectric layer and packed layer comprises silica.
Described in the embodiment of the present invention, wherein the formation method of lining comprises atomic layer deposition method.
According to the embodiment of the present invention, the method wherein forming the first irrigation canals and ditches and autoregistration dual-metal inserting opening comprises: take hard mask layer as mask, lining is etching stopping layer, the 3rd dielectric layer is removed with the first etching condition etching, to form the first irrigation canals and ditches and the second irrigation canals and ditches in the 3rd dielectric layer, the second irrigation canals and ditches expose packed layer; Take hard mask layer as mask, lining is etching stopping layer, removes packed layer, to form the second interlayer hole opening be communicated with the second irrigation canals and ditches with the second etching condition etching; And be mask with hard mask layer, etch the lining below the lining and stop-layer and the second interlayer hole opening removed below irrigation canals and ditches with the 3rd etching condition, the second irrigation canals and ditches and the second interlayer hole opening form autoregistration dual-metal inserting opening.
The embodiment of the present invention also proposes a kind of metal interconnecting structure, comprises substrate, the first dielectric layer, conductive plugs, the second dielectric layer, the 3rd dielectric layer, autoregistration double-metal inlaid structure and lining.First dielectric layer is positioned on substrate.Conductive plugs is arranged in the first dielectric layer.Second dielectric layer is positioned on the first dielectric layer.3rd dielectric layer is positioned on the second dielectric layer.Autoregistration double-metal inlaid structure, through the 3rd dielectric layer and the second dielectric layer, is electrically connected with conductive plugs.Lining is between autoregistration double-metal inlaid structure and the second dielectric layer and between the 3rd dielectric layer and the second dielectric layer.
According to the embodiment of the present invention, also comprise the stop-layer between the second dielectric layer and lining.
According to the embodiment of the present invention, also comprise the packed layer between lining and autoregistration double-metal inlaid structure.
According to the embodiment of the present invention, wherein lining is identical with the material of stop-layer.
According to the embodiment of the present invention, wherein the material of lining and stop-layer comprises silicon nitride, and the material of the second dielectric layer and packed layer comprises silica.
The metal interconnecting structure of the embodiment of the present invention and technique thereof, can save processing step, increases process margin, improve the coupled problem between grid conductor, overcome the limit of lithographic critical dimension, promotes the nargin of alignment, reduces the cost of product.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to 1I is the generalized section of the manufacturing process of a kind of embedded memory element illustrated according to a first embodiment of the present invention.
Wherein, description of reference numerals is as follows:
10: substrate 30: encapsulant layer
11: conduction region 30a: packed layer
12,16,34: dielectric layer 32: hole
14: conductive plugs 36: hard mask layer
18: stop-layer 40,41: irrigation canals and ditches
20: end anti-reflecting layer 42: autoregistration dual-metal inserting opening
22: mask layer 44: wire
24,38: opening irrigation canals and ditches pattern 45: conductor layer
26,43: interlayer hole opening 46: autoregistration double-metal inlaid structure
28: lining
Embodiment
Figure 1A to 1I is the generalized section of the manufacturing process of embedded memory element illustrated according to a first embodiment of the present invention.
Please refer to Figure 1A, substrate 10 is provided.Substrate 10 can be semiconductor or semiconducting compound, such as, be silicon or germanium silicide.Substrate 10 also can be silicon on insulating barrier (SOI).There is in substrate 10 conduction region 11.Conduction region 11 is such as doped region or conductive layer.
Form dielectric layer 12 over the substrate 10.The material of dielectric layer 12 is such as silica, and the method for formation is such as chemical vapour deposition technique.The thickness of dielectric layer 12 is such as 4000 dust to 5000 dusts.Conductive plugs 14 is formed in dielectric layer 12.The material of conductive plugs 14 can be metal, such as, be tungsten.Conductive plugs 14 is such as bit line contacting window.
Then, dielectric layer 16 is formed on the dielectric layer 12.The material of dielectric layer 16 is such as silica, and the method for formation is such as chemical vapour deposition technique.The thickness of dielectric layer 16 is such as 1000 dust to 2000 dusts.Afterwards, dielectric layer 16 forms stop-layer 18.The material of stop-layer 18 is different from the material of dielectric layer 16.The material of stop-layer 18 is such as silicon nitride, and the method for formation is such as with silicomethane as reacting gas, utilizes chemical vapour deposition technique to deposit, and thickness is such as 100 dust to 600 dusts.Afterwards, stop-layer 18 forms mask layer 22.Corresponding to conductive plugs 14, there is patterns of openings 24 in mask layer 22.The material of mask layer 22 is such as photoresist.End antireflection (BARC) layer 20 can be first formed on stop-layer 18 before formation mask layer 22.The material of end anti-reflecting layer 20 be such as organic polymer or carbon silicon oxynitride, the method for formation is such as liquid spin-coating method, and thickness is such as 200 dust to 400 dusts.
Please refer to Figure 1B, with mask layer 22 (Figure 1A) for mask, etching removal stop layer 18 and dielectric layer 16, to form interlayer hole opening 26, expose conductive plugs 14.Remove mask layer 22 and end anti-reflecting layer 20 afterwards.Etching removal stop layer 18 can be anisotropic etch process with the method for dielectric layer 16, such as, be reactive ion etching method.Then, such as mask layer 22 and end anti-reflecting layer 20 is removed with oxonium ion plasma.
Afterwards, dielectric layer 16 forms lining 28, cover sidewall and the bottom of stop-layer 18 and interlayer hole opening 26.The material of lining 28 is different from dielectric layer 16.The material of lining 28 can be identical with stop-layer 18.The material of lining 28 is such as silicon nitride, and the method for formation is such as atomic layer deposition method, and thickness is such as 50 dust to 150 dusts.Lining 28 can be used to the size reducing interlayer hole opening 26, and protects the sidewall of interlayer hole opening 26 in the process of follow-up formation autoregistration dual-metal inserting opening.
Please refer to Fig. 1 C, then, on lining 28 and in interlayer hole opening 26, form encapsulant layer 30.The material of encapsulant layer 30 is different from lining 28.The material of encapsulant layer 30 is such as silica, and the method for formation is such as chemical vapour deposition technique.The size of interlayer hole opening 26 reduces because of lining 28, encapsulant layer 30 may be caused cannot to fill up interlayer hole opening 26, and form hole 32.But, because the sidewall of each interlayer hole opening 26 is surrounded by the lining 28 of different materials, therefore, the hole 32 in each interlayer hole opening 26 is not communicated with each other, and also can avoid the problem of lateral communication because of the difference on lining 28 and dielectric layer 16 material in follow-up etching process.
Thereafter, please refer to Fig. 1 D, the encapsulant layer 30 above lining 28 is removed, in interlayer hole opening 26, leaves packed layer 30a.The method removing the encapsulant layer 30 be positioned on lining 28 be such as with lining 28 for polish stop layer, utilize chemical mechanical milling method to remove it.After the encapsulant layer 30 removed above lining 28, also can the lining 28 above stop-layer 18 be removed selectivity.
Afterwards, on lining 28 with packed layer 30a, dielectric layer 34 is formed.The material of dielectric layer 34 is such as silica or advanced low-k materials is such as carborundum, and the method for formation is such as chemical vapour deposition technique.The thickness of dielectric layer 34 is such as 500 dust to 2500 dusts.
Thereafter, dielectric layer 34 forms hard mask layer 36.Hard mask layer 36 has multiple opening irrigation canals and ditches pattern 38, wherein has an opening irrigation canals and ditches pattern 38 to be positioned at above interlayer hole opening 26, and corresponding with interlayer hole opening 26.The material of hard mask layer 36 is such as polysilicon, carbon or silicon oxynitride.The formation method of polysilicon is such as chemical vapour deposition technique.The formation method of opening irrigation canals and ditches pattern 38 can by photoetching and etch process.
Then, please refer to Fig. 1 G, with hard mask layer 36 for mask, carry out etch process, to form irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42.Irrigation canals and ditches 40 are through dielectric layer 34, lining 28 and stop-layer 18.Autoregistration dual-metal inserting opening 42, through the packed layer 30a in dielectric layer 34 and interlayer hole opening 26 and lining 28, exposes conductive plugs 14.The etch process adopted can be anisotropic etching process, such as, be reactive ion etching process.
Please refer to Fig. 1 E, in one embodiment, above-mentioned formation irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42 can first with hard mask layer 36 for mask, utilize lining 28 as etching stopping layer, select for dielectric layer 34/ lining 28 or for dielectric layer 34/ stop-layer 18 have high etching selectivity first etching condition etching remove dielectric layer 34, to form irrigation canals and ditches 40 and irrigation canals and ditches 41.When with the first etching condition etching; because the first etching condition has high etching selectivity for dielectric layer 34/ lining 28 or for dielectric layer 34/ stop-layer 18, therefore, in the process of etching; lining 28 can as etching stopping layer with stop-layer 18, the surface of protection dielectric layer 16.
Then, please refer to Fig. 1 F, with hard mask layer 36 for mask, lining 28 is stop-layer, change etching condition, select for packed layer 30a/ lining 28 or for packed layer 30a/ stop-layer 18 have high etching selectivity second etching condition etching remove packed layer 30a, to form interlayer hole opening 43.Owing to there is hole 32 among packed layer 30a, therefore among interlayer hole opening 43, the material volume of packed layer 30a is less, can be completely removed more quickly, therefore, the consumption of hard mask layer 36 can be alleviated, do not need too thick hard mask layer 36 to avoid being consumed totally in the process of etching.In addition; when with the second etching condition etching; due to packed layer 30a/ lining 28 or packed layer 30a/ stop-layer 18 has high etching selectivity; therefore lining 28 can as protective layer; the sidewall of protection dielectric layer 16 and surface; remove the packed layer 30a of interlayer hole opening 26 with autoregistration, and the sidewall of dielectric layer 16 can not be damaged.And when with the second etching condition etching, the lining 28 below irrigation canals and ditches 40 or stop-layer 18 can as stop-layers, the surface of protection dielectric layer 16.
Afterwards, please refer to Fig. 1 G, select the 3rd etching condition etching lining 28/ dielectric layer 16 or stop-layer 18/ dielectric layer 16 to high etching selectivity to remove lining below irrigation canals and ditches 40 28 and stop-layer 18, and the lining 28 below interlayer hole opening 43.During with the 3rd etching condition etching, 3rd etching condition has high etching selectivity for lining 28/ dielectric layer 16 or for stop-layer 18/ dielectric layer 16, therefore when continuing lining 28 that etching removes irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42 place with stop-layer 18, also can not the dielectric layer 16 of over etching below it.Irrigation canals and ditches 41 and interlayer hole opening 43 form autoregistration dual-metal inserting opening 42.Due to self aligned autoregistration dual-metal inserting opening 42 can be formed, therefore, between the interlayer hole opening 26 of autoregistration dual-metal inserting opening 42 and below and conductive plugs 14, there is good alignment nargin.
Afterwards, please refer to Fig. 1 H, remove hard mask layer 36.Afterwards, dielectric layer 34 forms conductor layer 45, to fill up irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42.The material of conductor layer 45 is such as tungsten or copper.In one embodiment, conductor layer 45 is tungsten metal level, and before formation tungsten metal level, first in irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42, forms adhesion layer (not illustrating).The material of adhesion layer is such as titanium nitride.In another embodiment, conductor layer 45 is copper metal layer, and before formation copper metal layer, first in irrigation canals and ditches 40 and autoregistration dual-metal inserting opening 42, forms barrier layer.The material of barrier layer is such as tantalum nitride.
Please refer to Fig. 1 I, remove conductor layer 45 unnecessary on dielectric layer 34, to form wire 44 in irrigation canals and ditches 40, and form autoregistration double-metal inlaid structure 46 in autoregistration dual-metal inserting opening 42, to be electrically connected with conductive plugs 14.The method removing conductor layer 45 unnecessary on dielectric layer 34 is such as chemical mechanical milling method.In one embodiment, autoregistration double-metal inlaid structure 46 is as bit line.Because lining 28 can protect the sidewall of interlayer hole opening 26 to make the hole 32 in each interlayer hole opening 26 not be communicated with each other; therefore; after formation autoregistration double-metal inlaid structure 46, autoregistration double-metal inlaid structure 46 also can not have the problem of short circuit each other because of hole 32.
Please refer to Fig. 1 I, the metal interconnecting structure of the embodiment of the present invention, comprise substrate 10, dielectric layer 12, conductive plugs 14, dielectric layer 16, dielectric layer 34, autoregistration double-metal inlaid structure 46 and lining 28.Dielectric layer 12 is positioned on substrate 10.Conductive plugs 14 is arranged in dielectric layer 12.Dielectric layer 16 is positioned on dielectric layer 12.Dielectric layer 34 is positioned on dielectric layer 16.Autoregistration double-metal inlaid structure 46, through dielectric layer 34 and dielectric layer 16, is electrically connected with conductive plugs 14.Lining 28 is between autoregistration double-metal inlaid structure 46 and dielectric layer 16 and between dielectric layer 34 and dielectric layer 16.Moreover, between dielectric layer 16 and lining 28, also comprise stop-layer 18.In addition, in one embodiment, between lining 28 and autoregistration double-metal inlaid structure 46, packed layer 30a is also comprised.In addition, metal interconnecting structure also comprises wire 44, and it is through dielectric layer 34, lining 28 and stop-layer 18.
In the present embodiment, dielectric layer 16 is formed directly on dielectric layer 12, does not have other high-k material layer between dielectric layer 16 and dielectric layer 12, such as, be silicon nitride, not only can save the step of deposition, the problem be coupled between bit line with grid conductor can also be improved.
Moreover; lining 28 is formed at the sidewall of the surface of dielectric layer 16 and interlayer hole opening 26; sidewall and the corner of interlayer hole opening 26 can be protected; form self aligned autoregistration dual-metal inserting opening 42, the problem that corner that the limit of lithographic critical dimension and high-density plasma (HDP) oxide layer cause damages can be overcome.
In addition, because the sidewall of interlayer hole opening 26 is covered by lining 28, therefore, even if the packed layer 30a in interlayer hole opening 26 has hole 32, the problem of the autoregistration double-metal inlaid structure 46 side direction conducting of follow-up formation can not also be caused.And the packed layer 30a in interlayer hole opening 26 has hole 32 to contribute to packed layer 30a on the contrary can be removed more fast, therefore can to reduce the consumption of hard mask layer on etch process.
Moreover, due to self aligned autoregistration dual-metal inserting opening 42 can be formed, therefore, autoregistration dual-metal inserting opening 42 and the interlayer hole opening 26 below it and between conductive plugs 14, there is good alignment nargin.In addition, example of the present invention replaces single mosaic technology with dual-damascene technics, and the cost of product can save 2 ~ 3%.
Although the present invention with embodiment openly as above; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion of defining depending on appended claim.
Claims (13)
1. a metal interconnecting technique, is characterized in that comprising:
Substrate is provided, described substrate has formed the first dielectric layer, and form conductive plugs in described first dielectric layer;
Described first dielectric layer forms the second dielectric layer;
The first interlayer hole opening is formed in described second dielectric layer;
Lining is formed at the sidewall of the surface of described second dielectric layer and described first interlayer hole opening and bottom;
Packed layer is inserted in described first interlayer hole opening;
The 3rd dielectric layer is formed on described lining; And
Form autoregistration double-metal inlaid structure, described autoregistration double-metal inlaid structure, through the described packed layer in described 3rd dielectric layer and described first interlayer hole opening and described lining, is electrically connected with described conductive plugs.
2. metal interconnecting technique as claimed in claim 1, before wherein forming the first interlayer hole opening in described second dielectric layer, is also included on described second dielectric layer and forms stop-layer.
3. metal interconnecting technique as claimed in claim 2, also comprises the wire formed through described 3rd dielectric layer, described lining and described stop-layer.
4. metal interconnecting technique as claimed in claim 3, the method wherein forming described autoregistration double-metal inlaid structure and described wire comprises:
Described 3rd dielectric layer forms hard mask layer, and described hard mask layer has multiple patterns of openings, and one of described patterns of openings is positioned at described first interlayer hole overthe openings;
With described hard mask layer for mask, carry out etch process, to form the first irrigation canals and ditches and autoregistration dual-metal inserting opening, wherein said first irrigation canals and ditches are through described 3rd dielectric layer, described lining and described stop-layer, described autoregistration dual-metal inserting opening, through the described packed layer in described 3rd dielectric layer and described first interlayer hole opening and described lining, exposes described conductive plugs; And
In described first irrigation canals and ditches, form described wire, and form described autoregistration double-metal inlaid structure in described autoregistration dual-metal inserting opening.
5. metal interconnecting technique as claimed in claim 2, wherein said lining is identical with the material of described stop-layer.
6. metal interconnecting technique as claimed in claim 5, the material of wherein said lining and described stop-layer comprises silicon nitride, and the material of described second dielectric layer and described packed layer comprises silica.
7. metal interconnecting technique as claimed in claim 6, the formation method of wherein said lining comprises atomic layer deposition method.
8. metal interconnecting technique as claimed in claim 4, the method wherein forming described first irrigation canals and ditches and described autoregistration dual-metal inserting opening comprises:
With described hard mask layer for mask, described lining is etching stopping layer, and remove described 3rd dielectric layer with the first etching condition etching, to form described first irrigation canals and ditches and the second irrigation canals and ditches in described 3rd dielectric layer, described second irrigation canals and ditches expose described packed layer;
With described hard mask layer for mask, described lining is etching stopping layer, removes described packed layer, to form the second interlayer hole opening be communicated with described second irrigation canals and ditches with the second etching condition etching; And
With described hard mask layer for mask, etch the described lining below the described lining and described stop-layer and described second interlayer hole opening removed below described irrigation canals and ditches with the 3rd etching condition, described second irrigation canals and ditches and described second interlayer hole opening form described autoregistration dual-metal inserting opening.
9. a metal interconnecting structure, is characterized in that comprising:
Substrate;
First dielectric layer, is positioned on described substrate
Conductive plugs, is embedded in described first dielectric layer;
Second dielectric layer, is positioned on described first dielectric layer;
3rd dielectric layer, is positioned on described second dielectric layer;
Autoregistration double-metal inlaid structure, through described 3rd dielectric layer and described second dielectric layer, is electrically connected with described conductive plugs; And
Lining, between described autoregistration double-metal inlaid structure and described second dielectric layer and between described 3rd dielectric layer and described second dielectric layer.
10. metal interconnecting structure as claimed in claim 9, also comprises the stop-layer between described second dielectric layer and described lining.
11. metal interconnecting structures as claimed in claim 10, also comprise the packed layer between described lining and described autoregistration double-metal inlaid structure.
12. metal interconnecting structures as claimed in claim 11, wherein said lining is identical with the material of described stop-layer.
13. metal interconnecting structures as claimed in claim 10, the material of wherein said lining and described stop-layer comprises silicon nitride, and the material of described second dielectric layer and described packed layer comprises silica.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107230660A (en) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor device |
| CN109300875A (en) * | 2017-07-24 | 2019-02-01 | 旺宏电子股份有限公司 | Internal connection-wire structure and its manufacturing method |
| CN110416210A (en) * | 2018-04-26 | 2019-11-05 | 三星电子株式会社 | Semiconductor device |
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| US20030211727A1 (en) * | 2002-05-13 | 2003-11-13 | Nanya Technology Corporation | Dual damascene process |
| CN1815711A (en) * | 2005-01-31 | 2006-08-09 | 台湾积体电路制造股份有限公司 | Interconnect structure and method of forming the same |
| CN1835206A (en) * | 2005-02-05 | 2006-09-20 | 三星电子株式会社 | Method of forming double-setting line arrange for semiconductor device using protective access cover layer |
| CN101425500A (en) * | 2007-11-01 | 2009-05-06 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107230660A (en) * | 2016-03-24 | 2017-10-03 | 台湾积体电路制造股份有限公司 | The manufacture method of semiconductor device |
| CN109300875A (en) * | 2017-07-24 | 2019-02-01 | 旺宏电子股份有限公司 | Internal connection-wire structure and its manufacturing method |
| CN109300875B (en) * | 2017-07-24 | 2020-11-10 | 旺宏电子股份有限公司 | Interconnect structure and method of fabricating the same |
| CN110416210A (en) * | 2018-04-26 | 2019-11-05 | 三星电子株式会社 | Semiconductor device |
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