CN104282750B - The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid - Google Patents
The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid Download PDFInfo
- Publication number
- CN104282750B CN104282750B CN201310590299.6A CN201310590299A CN104282750B CN 104282750 B CN104282750 B CN 104282750B CN 201310590299 A CN201310590299 A CN 201310590299A CN 104282750 B CN104282750 B CN 104282750B
- Authority
- CN
- China
- Prior art keywords
- nearly
- gate electrode
- control gate
- monocrystalline silicon
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 33
- 241001347978 Major minor Species 0.000 title claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 63
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000012212 insulator Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000004411 aluminium Substances 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 18
- 230000010354 integration Effects 0.000 abstract description 9
- 230000005641 tunneling Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 6
- 230000008569 process Effects 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
The present invention relates to a kind of discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid of the high integration high mobility low current leakage with outstanding switching characteristic, utilize nearly source master control gate electrode, the collective effect of nearly the two gate electrodes controlled independently of one another of leakage auxiliary control gate electrode, there is knot and without junction field effect transistor on the premise of avoiding doping process from causing device mobility to decline than common doping type, on the one hand nearly leakage auxiliary control gate electrode is kept to be in high potential, while occurring obvious tunneling effect in the channel region side for avoiding nearly drain electrode side and produce leakage current, promote U-shaped channel region to close on drain electrode side and be in low resistive state, on the other hand the thickness of source electrode side Schottky barrier is changed by adjusting the current potential of nearly source master control gate electrode, and then change the resistance of source electrode side to realize the switching of device.The U-shaped raceway groove used effectively increases the switching characteristic of high integration transistor on the premise of chip area is not increased.
Description
Technical field
The invention belongs to super large-scale integration manufacture field, and in particular to one kind is applied to the integrated electricity of superelevation integrated level
The discrete control U-shaped raceway groove non-impurity-doped field-effect transistor structure of major-minor grid of road manufacture.
Background technology
The elementary cell MOSFETs transistors of integrated circuit with size continuous reduction, it is necessary to several nanometers away from
Formed from the interior concentration difference for realizing multiple orders of magnitude extremely steep source electrode and drain electrode PN junction, such concentration gradient for doping and
Technology for Heating Processing has high requirement.A kind of method for solving this problem is by being made in SOI wafer without junction field effect
Transistor.Without junction field effect transistor using many son conductings, source region, drain region and the channel region for making device by ion implanting are formed
Same type, the Impurity Distribution of same concentrations, because silicon thin film is very thin, by taking N-type device as an example, when gate electrode is in low potential
When, most electronics of channel region are depleted in the presence of grid electric field, so that the raceway groove of device is in high-impedance state.With
Gradually rising for gate electrode potential, many sons of channel region exhaust gradually to be released therewith, and electron accumulation is formed in interface, from
And the raceway groove of device is in low resistive state.Therefore, it is this without realizing the dense of multiple orders of magnitude in several nanometers of distance
Spend difference to form extremely steep source electrode and drain electrode PN junction, but can equally realize the switching function of conventional MOS FETs transistors.So
And, this inferior position without junction field effect transistor is：
1. being reduction source and drain resistance, no junction field effect transistor needs very high doping concentration, but too high doping concentration
Being decreased obviously for device channel region mobility can be caused, meanwhile, impurity random scatter can cause the reliability of device by serious
Influence.Therefore the intrinsic contradictory relation existed between the source and drain resistance of device and the channel mobility of device.
2. it is similar with tradition MOSFETs transistors, when gate electrode is in reverse biased, the drain electrode voltage of positively biased
The high potential difference formed between reverse-biased gate electrode voltage causes the silicon thin film areas adjacent for closing on two electrodes to be formed by force
Electric field, this can cause bending substantially for the local energy band of silicon thin film, enable the tunneling effect enhancing of interband, and then cause leakage current
Generation.
In addition, having based on planar structure is tied and nodeless mesh body pipe is faced with the challenge of horizontal channel length physics limit,
For more than ten or the long raceway groove of several nanometers, gate electrode can substantially weaken to the controling power of channel switches, so as to cause device
The enhancing of short-channel effect so that device is difficult to good switching function.
The content of the invention
Goal of the invention
To improve the mobility without junction field effect transistor based on silicon technology, reduction is common to have knot and brilliant without junction field effect
The leakage current of body pipe and the switching function for improving nanoscale short channel length field-effect transistor, the present invention provide a kind of main
The concrete structure of the auxiliary discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid.
Technical scheme
The present invention is achieved through the following technical solutions：
A kind of discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid, includes the silicon substrate of SOI wafer, SOI is brilliant
It is the insulating barrier of SOI wafer above round silicon substrate；It is characterized in that：It is monocrystalline silicon groove above the insulating barrier of SOI wafer, it is single
Have in the groove of crystal silicon groove and make to playing mutually insulated between monocrystalline silicon groove, nearly source master control gate electrode and nearly leakage auxiliary control gate electrode
It is respectively source electrode and drain electrode above gate insulator, monocrystalline silicon groove two ends, adjacent monocrystalline silicon groove and source are electric
Isolated between pole and drain electrode by insulating medium layer.
Nearly source master control gate electrode and the nearly electrode for leaking the two electrodes of auxiliary control gate electrode to control independently of one another, and pass through grid
Pole insulating barrier and insulating medium layer realize it is insulated from each other, wherein nearly source master control gate electrode be located at monocrystalline silicon groove in close on source electrode
Side, for monocrystalline silicon groove be located at source electrode below vertically and horizontally raceway groove part electric field, potential and carrier
Control action is distributed, nearly leakage auxiliary control gate electrode is located at the side that drain electrode is closed in monocrystalline silicon groove, for monocrystalline silicon groove
Be located at drain electrode below vertically and horizontally raceway groove part electric field, potential and Carrier Profile rise control action, nearly source master
Control gate electrode and nearly the two electrodes of leakage auxiliary control gate electrode are each other in the relation being parallel to each other.
The selected SOI wafer for being used to form monocrystalline silicon groove is that non-impurity-doped or impurity concentration are less than 1016cm-3SOI
Wafer.
Source electrode and drain electrode are respectively with the two ends upper surface of monocrystalline silicon groove and forming Schottky barrier.
Gate insulator be by the inside to monocrystalline silicon groove by depositing technics generate have high-k
Insulating materials dielectric layer, the described insulating materials dielectric layer with high-k is hafnium oxide, silicon nitride or three
Al 2 O.
Advantage and effect
The invention has the advantages that and beneficial effect：
1. high mobility：
The material used due to the raceway groove part of monocrystalline silicon groove part proposed by the invention, i.e. device is non-impurity-doped
Or impurity concentration is less than 1016cm-3Monocrystalline silicon, this cause device in contrast to common doping type have knot or without junction field effect crystal
Pipe has higher mobility.
2. low current leakage：
Due to the present invention grid electricity that the two are controlled independently of one another using nearly source master control gate electrode and nearly leakage auxiliary control gate electrode
Pole, when device works, nearly leak auxiliary control gate electrode remain at high potential, so can significantly drain electrode and monocrystalline silicon it is recessed
The thickness of the Schottky barrier formed between groove, makes a large amount of electronics cross potential barrier by tunneling effect, is closed in monocrystalline silicon groove
The side of drain electrode and the interface of gate insulator form electron accumulation, so monocrystalline silicon groove is closed on the one of drain electrode
Side is in low resistive state when device works.Nearly source master control gate electrode as device actual switch coordination electrode, when near
When master control gate electrode in source is in low potential, the schottky barrier width formed between monocrystalline silicon groove and source electrode is very thick, because
This does not have a large amount of electronics from source electrode one end and Xiao for being formed between monocrystalline silicon groove and source electrode is crossed by tunneling effect
Special base potential barrier, this make it that the side that monocrystalline silicon groove closes on source electrode is high-impedance state, electric leakage is closed on due to monocrystalline silicon groove
It is series relationship between the side of pole and the side for closing on source electrode, therefore device is overall still with high resistance.
Meanwhile, it is maintained between the nearly leakage auxiliary control gate electrode of high potential and drain electrode and does not form obvious electrical potential difference, this makes
Monocrystalline silicon groove will not form obvious band curvature in the areas adjacent, therefore have knot or without junction field in contrast to common doping type
Effect transistor, the discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid proposed by the invention will not occur substantially
Interband tunneling effect, therefore efficiently avoid the generation of leakage current.
To sum up, by the collective effect of nearly source master control gate electrode and nearly leakage auxiliary control gate electrode, there are knot and nothing in contrast to common
Junction field effect transistor, the discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid proposed by the invention has low
The advantage of leakage current.
3. high integration and outstanding switching characteristic：
The present invention is using monocrystalline silicon groove as device channel portion, and its length of effective channel is the vertical furrow of groove both sides
The height of road part and horizontal channel length sum, and vertical channel portion is located at the lower section of source electrode and drain electrode, therefore it is right
Than in common plane structure, there is longer channel length on the premise of few chip occupying area, therefore be suitable for high collection
Into degree manufacture, while also slow down the deterioration of devices switch characteristic caused by short-channel effect under planar structure.
Brief description of the drawings
Fig. 1 is two that the discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid of the invention is formed on soi substrates
Tie up structural representation；
Fig. 2 to Fig. 7 for the discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid of the invention construction unit and its
The process chart of one instantiation of the preparation method of array,
Fig. 2 is step one schematic diagram,
Fig. 3 is step 2 schematic diagram,
Fig. 4 is step 3 schematic diagram,
Fig. 5 is step 4 schematic diagram,
Fig. 6 is step 5 schematic diagram,
Fig. 7 is step 6 schematic diagram.
Reference is said：
1st, source electrode；2nd, drain electrode；3rd, nearly source master control gate electrode；4th, nearly leakage auxiliary control gate electrode；5th, gate insulator；6th, absolutely
Edge dielectric layer；7th, monocrystalline silicon groove；8th, the insulating barrier of SOI wafer；9th, the silicon substrate of SOI wafer.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：
The present invention provides a kind of major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, by using non-impurity-doped
Or low-doped monocrystalline silicon groove 7 is used as the raceway groove part of device so that device has knot or nodeless mesh in contrast to common doping type
Body pipe has higher mobility.When device works, forward bias between drain electrode 2 and source electrode 1, by using nearly source master
Control gate electrode 3 and nearly the two gate electrodes controlled independently of one another of leakage auxiliary control gate electrode 4 carry out the switch of control device.When device work
When making, nearly leak auxiliary control gate electrode 4 and remain at high potential, so can shape significantly between drain electrode 2 and monocrystalline silicon groove 7
Into Schottky barrier thickness, a large amount of electronics is crossed potential barrier by tunneling effect, drain electrode 2 closed in monocrystalline silicon groove 7
The interface of side and gate insulator 5 form electron accumulation, monocrystalline silicon groove 7 is closed on the side of drain electrode 2
Low resistive state is in when device works, there is the drain region tied or without junction field effect transistor equivalent to common doping type；And nearly source
The actual control grid electrode that master control gate electrode 3 is then switched on and off for device, when nearly source master control gate electrode 3 is in low potential,
The Schottky barrier thickness formed between monocrystalline silicon groove 7 and source electrode 1 is very thick, therefore does not have a large amount of electronics and pass through tunnelling
Effect crosses the Schottky barrier formed between monocrystalline silicon groove 7 and source electrode 1 and forms electric current, this thicker Schottky
Potential barrier can play good blocking effect to device, even if monocrystalline silicon groove 7 is in low-resistance shape all the time in one end of drain electrode 2
State, because the side that monocrystalline silicon groove 7 closes on the side of drain electrode 2 with closing on source electrode 1 is series relationship therebetween, therefore
Device is integrally still in the off state of high resistant；With being gradually increasing for the nearly current potential of source master control gate electrode 3, monocrystalline silicon groove 7
The thickness of the Schottky barrier formed with source electrode 1 is constantly thinned, and tunneling effect also constantly strengthens, when nearly source master control gate electrode
3 when being in high potential, thickness and the monocrystalline silicon groove 7 and leakage of the Schottky barrier that monocrystalline silicon groove 7 and source electrode 1 are formed
Quite, both sides have a large amount of electronics by tunneling effect by Schottky barrier to the thickness for the Schottky barrier that electrode 2 is formed,
Therefore U-shaped carrier channels are formed in the interface of monocrystalline silicon groove 7 and gate insulator 5, if now drain electrode 2 and source electrode
There is electrical potential difference between 1, then have obvious electric current and flow through device.
Meanwhile, there are knot and nodeless mesh body pipe in contrast to common doping type, be always held at the nearly leakage auxiliary control grid electricity of high potential
Obvious electrical potential difference is not formed between pole 4 and drain electrode 2, this makes monocrystalline silicon groove 7 not formed in the vicinity for closing on drain electrode 2
Obvious band curvature, therefore the discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid proposed by the invention will not
The obvious interband tunneling effect of generation, thus efficiently solve common doping type have knot and nodeless mesh body pipe, when gate electrode is anti-
Partially, the problem of a large amount of leakage currents can be produced during drain voltage positively biased.
In addition, the present invention uses monocrystalline silicon groove 7 as device channel portion, its length of effective channel is groove both sides
The height of vertical channel portion and horizontal channel length sum, and the vertical channel portion of both sides is located at source electrode 1 and drain electrode 2
Lower section, therefore in contrast to common plane structure, on the premise of few chip occupying area, the device has longer raceway groove
Length, therefore it is suitable for high integration manufacture, while it is special also to slow down devices switch caused by short-channel effect under planar structure
The deterioration of property.
The present invention realized with high integration by above-mentioned embodiment, well switch special efficacy, high mobility and low
The discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid of leakage current.
To reach device function of the present invention, this major-minor discrete control U-shaped raceway groove of grid proposed by the invention without
Doped field effect transistor, its core texture is characterized as：
1. being the basic function and reduction leakage current for realizing device, the discrete control U-shaped raceway groove of described major-minor grid is without mixing
Miscellaneous field-effect transistor, its core texture is characterized as：Nearly source master control gate electrode 3 and nearly the two electrodes of leakage auxiliary control gate electrode 4 are
The electrode controlled independently of one another, and realized by gate insulator 5 and insulating medium layer 6 it is insulated from each other, wherein nearly source master control grid
Electrode 3 is located at the side that source electrode 1 is closed in monocrystalline silicon groove 7, is located at hanging down for the lower section of source electrode 1 for monocrystalline silicon groove 7
Electric field, potential and the Carrier Profile of straight and horizontal channel part play control action, and it is recessed that nearly leakage auxiliary control gate electrode 4 is located at monocrystalline silicon
The side of drain electrode 2 is closed in groove 7, for the vertically and horizontally raceway groove part that is located at the lower section of drain electrode 2 of monocrystalline silicon groove 7
Electric field, potential and Carrier Profile play control action, nearly source master control gate electrode 3 and nearly the two electrodes of leakage auxiliary control gate electrode 4 that
This is in the relation being parallel to each other.
2. it is the basic function for realizing device, the discrete control U-shaped raceway groove non-impurity-doped field effect transistor of described major-minor grid
Pipe, its core texture is characterized as：Source electrode 1 and drain electrode 2 are respectively with the two ends upper surface of monocrystalline silicon groove 7 and forming Xiao
Special base potential barrier.
3. to make device that there is high mobility, the discrete control U-shaped raceway groove non-impurity-doped field effect transistor of described major-minor grid
Pipe, its core texture is characterized as：It is selected to be used to form monocrystalline silicon groove（7）SOI wafer be non-impurity-doped or impurity concentration
Less than 1016cm-3SOI wafer.
4. it is described to improve the control ability of nearly source master control gate electrode 3 and nearly leakage auxiliary control gate electrode 4 to device channel
The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid, its core texture is characterized as：Gate insulator 5 is by list
The insulating materials dielectric layer with high-k that the inside of crystal silicon groove 7 is generated by depositing technics, described has height
The insulating materials dielectric layer of dielectric constant is hafnium oxide, silicon nitride or alundum (Al2O3).
5. make device under high integration have outstanding switching characteristic, described major-minor grid it is discrete control U-shaped raceway groove without
Doped field effect transistor, its core texture is characterized as：Using raceway groove part of the monocrystalline silicon groove 7 as device, monocrystalline is utilized
The vertical channel portion of the both sides of silicon groove 7, and two vertical-channels are located at the lower section of source electrode 1 and drain electrode 2 respectively, in contrast to
Common plane structure, on the premise of extra chip area is not take up, adds the length of effective channel of device, therefore help
Overcome the influence of short-channel effect in device, make device that there is outstanding switching characteristic under high integration.
The unit and array of this high integration high mobility source and drain grid auxiliary control type nodeless mesh body pipe proposed by the invention
Specific manufacturing technology steps it is as follows：
Step 1: providing a non-impurity-doped or doping concentration less than 1016cm-3SOI wafer, the lower section of SOI wafer is
It is the monocrystalline silicon thin film for forming monocrystalline silicon groove 7 above the silicon substrate 9 of SOI wafer, SOI wafer, it is brilliant for SOI therebetween
Round insulating barrier 8, forms a series of such as Fig. 2 institutes by techniques such as photoetching, etchings on the insulating barrier 8 of the SOI wafer provided
The monocrystalline silicon isolated island array for being used to form monocrystalline silicon groove 7 of the rectangular-shape shown；
Step 2: as shown in figure 3, above monocrystalline silicon isolated island array by depositing dielectric after, throw flat surface formed
Insulating medium layer 6, is used as isolating between device cell；
Step 3: as shown in figure 4, by etching technics, by each unit of monocrystalline silicon isolated island array by etching work
Skill formation monocrystalline silicon groove 7；
Step 4: being situated between as shown in figure 5, depositing the insulation with high-k in crystal column surface on the basis of the above-described procedure
Matter is used to form gate insulator 5, and throw is used to form nearly source master control gate electrode 3 and nearly leakage auxiliary control by etching again after flat surface
The groove of gate electrode 4；
Step 5: as shown in fig. 6, depositing metal or polysilicon, the flat table of throwing in crystal column surface on the basis of above-mentioned steps
Nearly source master control gate electrode 3 and nearly leakage auxiliary control gate electrode 4 are formed behind face respectively；
Step 6: as shown in fig. 7, depositing dielectric in crystal column surface on the basis of the above-described procedure, throwing flat surface enters one
Step generation insulating medium layer 6, and the insulating medium layer 6 of the two ends upper surface of monocrystalline silicon groove 7 is etched away with life by etching technics
Cheng Yuan, leakage through hole, and the two ends upper surface of injection metal and monocrystalline silicon groove 7 forms schottky junctions in source, leakage through hole respectively
Touch, source electrode 1 and drain electrode 2 are generated with this.
Claims (3)
1. a kind of discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid, includes the silicon substrate of SOI wafer（9）, SOI
The silicon substrate of wafer（9）Top is the insulating barrier of SOI wafer（8）；It is characterized in that：The insulating barrier of SOI wafer（8）Top is single
Crystal silicon groove（7）, monocrystalline silicon groove（7）Groove in have to monocrystalline silicon groove（7）, nearly source master control gate electrode（3）Closely leak auxiliary
Control gate electrode（4）Between play the gate insulator of mutually insulated（5）, monocrystalline silicon groove（7）It is respectively source electricity above two ends
Pole（1）And drain electrode（2）, adjacent monocrystalline silicon groove（7）And source electrode（1）And drain electrode（2）Between pass through insulating medium layer
（6）Isolation；Nearly source master control gate electrode（3）With nearly leakage auxiliary control gate electrode（4）The two electrodes are the electrode controlled independently of one another, and
Pass through gate insulator（5）And insulating medium layer（6）Realize it is insulated from each other, wherein nearly source master control gate electrode（3）Positioned at monocrystalline silicon
Groove（7）Inside close on source electrode（1）Side, nearly leakage auxiliary control gate electrode（4）Positioned at monocrystalline silicon groove（7）Inside close on drain electrode
（2）Side, nearly source master control gate electrode（3）With nearly leakage auxiliary control gate electrode（4）The two electrodes are each other in the relation being parallel to each other；
Source electrode（1）And drain electrode（2）Respectively with monocrystalline silicon groove（7）Two ends upper surface and form Schottky barrier.
2. the discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid according to claim 1, it is characterised in that：
It is selected to be used to form monocrystalline silicon groove（7）SOI wafer be less than 10 for non-impurity-doped or impurity concentration16cm-3SOI wafer.
3. the discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of major-minor grid according to claim 1, it is characterised in that：
Gate insulator（5）It is by monocrystalline silicon groove（7）Inside by depositing technics generate have high-k it is exhausted
Edge material medium layer, the described insulating materials dielectric layer with high-k is hafnium oxide, silicon nitride or three oxygen
Change two aluminium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310590299.6A CN104282750B (en) | 2013-11-20 | 2013-11-20 | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310590299.6A CN104282750B (en) | 2013-11-20 | 2013-11-20 | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104282750A CN104282750A (en) | 2015-01-14 |
| CN104282750B true CN104282750B (en) | 2017-07-21 |
Family
ID=52257459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310590299.6A Expired - Fee Related CN104282750B (en) | 2013-11-20 | 2013-11-20 | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104282750B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180068211A (en) * | 2016-12-13 | 2018-06-21 | 현대자동차주식회사 | Semiconductor device and method manufacturing the same |
| CN107785436B (en) * | 2017-10-31 | 2019-10-15 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped channel bidirectional transistor and its manufacturing method |
| CN107785437B (en) * | 2017-10-31 | 2020-05-29 | 沈阳工业大学 | Bracket-shaped grid-control source-drain resistance-variable bidirectional switch transistor and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6972260B2 (en) * | 2004-05-07 | 2005-12-06 | Powerchip Semiconductor Corp. | Method of fabricating flash memory cell |
| CN101154660A (en) * | 2006-09-30 | 2008-04-02 | 海力士半导体有限公司 | Semiconductor device for preventing reciprocal influence between neighboring gates and method for manufacturing the same |
| CN103199017A (en) * | 2003-12-30 | 2013-07-10 | 飞兆半导体公司 | A method for forming buried conductive layers, a method for controlling the thickness of a material, and a method for forming a transistor |
| CN103268889A (en) * | 2013-05-23 | 2013-08-28 | 清华大学 | Junction-free transverse tunneling field effect transistor |
-
2013
- 2013-11-20 CN CN201310590299.6A patent/CN104282750B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199017A (en) * | 2003-12-30 | 2013-07-10 | 飞兆半导体公司 | A method for forming buried conductive layers, a method for controlling the thickness of a material, and a method for forming a transistor |
| US6972260B2 (en) * | 2004-05-07 | 2005-12-06 | Powerchip Semiconductor Corp. | Method of fabricating flash memory cell |
| CN101154660A (en) * | 2006-09-30 | 2008-04-02 | 海力士半导体有限公司 | Semiconductor device for preventing reciprocal influence between neighboring gates and method for manufacturing the same |
| CN103268889A (en) * | 2013-05-23 | 2013-08-28 | 清华大学 | Junction-free transverse tunneling field effect transistor |
Non-Patent Citations (1)
| Title |
|---|
| Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness;Horng-Chih Lin.et.al;《IEEE Transactions on Electron Devices》;20130331;第60卷(第3期);第1142-1148页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104282750A (en) | 2015-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102403356B (en) | Semiconductor device | |
| CN107808899B (en) | Lateral power device with mixed conduction mode and preparation method thereof | |
| CN102214684B (en) | Semiconductor structure with suspended sources and drains as well as formation method thereof | |
| CN104409487B (en) | The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method | |
| CN104282750B (en) | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid | |
| CN102130176B (en) | SOI (silicon-on-insulator) super-junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with buffer layer | |
| CN103531592B (en) | Three gate control type nodeless mesh body pipes of high mobility low source and drain resistance | |
| CN104282751B (en) | High integration high mobility source and drain grid auxiliary control type nodeless mesh body pipe | |
| CN103545375B (en) | The discrete control type non-impurity-doped field-effect transistor of the nearly nearly drain-gate of source grid | |
| CN104157690B (en) | Strain NLDMOS device with groove structure and manufacturing method thereof | |
| CN103762229B (en) | There is the lateral power of gate stack | |
| CN107785414A (en) | Lateral power with hybrid conductive pattern and preparation method thereof | |
| CN104282754B (en) | High integration L-shaped grid-control Schottky barrier tunneling transistor | |
| CN104393033B (en) | Gate insulation tunnelling groove base bipolar transistor with breakdown protection function | |
| CN107785436A (en) | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method | |
| CN203941904U (en) | Based on SOI pressure-resistance structure and the power device of folding drift region | |
| CN104282752B (en) | Drain electrode auxiliary control L-shaped gate type junction-free transistor | |
| CN109256423B (en) | Oxidation tank alternate isolation type insulated gate bipolar transistor and preparation method thereof | |
| CN104282753B (en) | Highly integrated shape source and drain grid auxiliary control U-shaped raceway groove high mobility nodeless mesh body pipe of subsisting | |
| CN207425863U (en) | Semiconductor field effect transistor with three-stage oxygen buried layer | |
| CN103531636B (en) | Source grid leak controls single doping type tunneling transistor altogether | |
| CN110854192A (en) | Tunneling field effect transistor and preparation method thereof | |
| CN105932062B (en) | It is a kind of with the SOI LDMOS device for burying oxygen field plate | |
| CN104485353B (en) | Insulated gate tunneling bipolar transistor with U-shaped tunneling insulating layer and manufacturing process | |
| CN115101476B (en) | Manufacturing method of symmetrical silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of improving current capacity |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170721 Termination date: 20171120 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |