CN104282750A - Main and auxiliary gate discrete control U-shaped channel undoped field effect transistor - Google Patents
Main and auxiliary gate discrete control U-shaped channel undoped field effect transistor Download PDFInfo
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- CN104282750A CN104282750A CN201310590299.6A CN201310590299A CN104282750A CN 104282750 A CN104282750 A CN 104282750A CN 201310590299 A CN201310590299 A CN 201310590299A CN 104282750 A CN104282750 A CN 104282750A
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- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 230000000694 effects Effects 0.000 claims abstract description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 66
- 241001347978 Major minor Species 0.000 claims description 22
- 239000012212 insulator Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 230000005641 tunneling Effects 0.000 abstract description 10
- 230000010354 integration Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 6
- 230000009471 action Effects 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 2
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- 230000005684 electric field Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
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- 229910052751 metal Inorganic materials 0.000 description 2
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- 238000005452 bending Methods 0.000 description 1
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- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
The invention relates to a main and auxiliary gate discrete control U-shaped channel undoped field effect transistor which is good in switching characteristic, high in integration level, high in migration rate and low in leakage current. Compared with a common knotted or knotless doped field effect transistor, under the combined action of a near-source master control gate electrode and a near-drain auxiliary control gate electrode which carry out control independently, on the premise of avoiding the phenomenon that the doping process leads to decrease of the migration rate of a device, the near-drain auxiliary control gate electrode is kept at a high potential, the phenomenon that leakage current is generated when an obvious tunneling effect happens on the side, near the drain electrode, of a channel region is avoided, and the side, near the drain electrode, of the U-shaped channel region is in the low resistance state; in addition, the thickness of a schottky barrier on one side of the source electrode is changed by adjusting the potential of the near-source master control gate electrode, and then the resistance value of one side of the source electrode is changed to achieve switch-off and switch-on of the device. On the premise of not increasing the chip area, the adopted U-shaped channel effectively improves the switching characteristic of the transistor high in integration level.
Description
Technical field
The invention belongs to very lagre scale integrated circuit (VLSIC) and manufacture field, be specifically related to a kind of major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor structure being applicable to superelevation integrated level IC manufacturing.
Background technology
The elementary cell MOSFETs transistor of integrated circuit is along with the continuous reduction of size, need the concentration difference realizing multiple order of magnitude in the distance of several nanometer to form extremely steep source electrode and drain electrode PN junction, such concentration gradient has high requirement for doping and Technology for Heating Processing.A kind of method of head it off be by make in SOI wafer without junction field effect transistor.How sub-conducting is adopted without junction field effect transistor, the source region of device, drain region and channel region is made to form the Impurity Distribution of identical type, same concentrations by ion implantation, because silicon thin film is very thin, for N-type device, when gate electrode is in electronegative potential, most electronics of channel region are depleted under the effect of grid electric field, thus make the raceway groove of device be in high-impedance state.Along with the rising gradually of gate electrode potential, many sons of channel region exhaust to be removed thereupon gradually, and forms electron accumulation in interface, thus makes the raceway groove of device be in low resistive state.Therefore, this concentration difference without the need to realizing multiple order of magnitude in the distance of several nanometer forms extremely steep source electrode and drain electrode PN junction, but can realize the switching function of conventional MOS FETs transistor equally.But this inferior position without junction field effect transistor is:
1., for reducing source and drain resistance, need very high doping content without junction field effect transistor, but too high doping content can cause the obvious decline of device channel region mobility, meanwhile, impurity random scatter can cause the reliability of device to be had a strong impact on.Therefore the intrinsic contradictory relation existed between the source and drain resistance of device and the channel mobility of device.
2. similar with traditional MOSFETs transistor, when gate electrode is in reverse biased, the high potential difference formed between the drain electrode voltage of positively biased and reverse-biased gate electrode voltage makes the silicon thin film areas adjacent closing on two electrodes form highfield, it is significantly bending that this can cause silicon thin film local to be with, the tunneling effect of enable interband strengthens, and then causes the generation of leakage current.
In addition, have knot and nodeless mesh body pipe based on planar structure are faced with the challenge of horizontal channel length physics limit, for the raceway groove that tens or several nanometer grow, gate electrode can obviously weaken the control of channel switches, thus cause the enhancing of device short channel effect, make device be difficult to realize good switching function.
Summary of the invention
Goal of the invention
For improving the mobility without junction field effect transistor based on silicon technology, reduce common have knot and without junction field effect transistor leakage current and improve the switching function of nanoscale short channel length field-effect transistor, the invention provides the concrete structure of a kind of major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor.
Technical scheme
The present invention is achieved through the following technical solutions:
A kind of major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, comprising the silicon substrate of SOI wafer, is the insulating barrier of SOI wafer above the silicon substrate of SOI wafer; It is characterized in that: be monocrystalline silicon groove above the insulating barrier of SOI wafer, have monocrystalline silicon groove, the gate insulator playing mutually insulated effect between nearly source master control gate electrode and nearly leakage auxiliary control gate electrode in the groove of monocrystalline silicon groove, monocrystalline silicon groove is respectively source electrode and drain electrode above two ends, adjacent monocrystalline silicon groove and being isolated by insulating medium layer between source electrode and drain electrode.
Nearly source master control gate electrode and nearly these two electrodes of auxiliary control gate electrode that leak are the electrode controlled independent of one another, and realize insulated from each other by gate insulator and insulating medium layer, wherein nearly source master control gate electrode is positioned at the side that monocrystalline silicon groove closes on source electrode, for the electric field being positioned at the vertical and horizontal channel part below source electrode of monocrystalline silicon groove, electromotive force and Carrier Profile play control action, nearly leakage auxiliary control gate electrode is positioned at the side that monocrystalline silicon groove closes on drain electrode, for the electric field being positioned at the vertical and horizontal channel part below drain electrode of monocrystalline silicon groove, electromotive force and Carrier Profile play control action, nearly source master control gate electrode and nearly these two electrodes of auxiliary control gate electrode that leak are each other in the relation be parallel to each other.
The selected SOI wafer for the formation of monocrystalline silicon groove is that non-impurity-doped or impurity concentration are lower than 10
16cm
-3sOI wafer.
Source electrode and drain electrode contact with the two ends upper surface of monocrystalline silicon groove and form Schottky barrier respectively.
Gate insulator is the insulating material dielectric layer with high-k by being generated by depositing technics the inside of monocrystalline silicon groove, and the described insulating material dielectric layer with high-k is hafnium oxide, silicon nitride or alundum (Al2O3).
Advantage and effect
Tool of the present invention has the following advantages and beneficial effect:
1. high mobility:
Due to monocrystalline silicon groove part proposed by the invention, the material that namely channel part of device adopts is that non-impurity-doped or impurity concentration are lower than 10
16cm
-3monocrystalline silicon, this make device in contrast to common doping type have knot or without junction field effect transistor, there is higher mobility.
2. low current leakage:
Because the present invention adopts nearly source master control gate electrode and the nearly gate electrode leaking auxiliary control gate electrode these two and control independently of one another, when devices function, leak auxiliary control gate electrode nearly and remain at high potential, the thickness of the Schottky barrier that can significantly be formed between drain electrode and monocrystalline silicon groove like this, a large amount of electronics is made to cross potential barrier by tunneling effect, form electron accumulation in the interface of side and gate insulator that monocrystalline silicon groove closes on drain electrode, the side so just making monocrystalline silicon groove close on drain electrode is in low resistive state when devices function.The gate electrode of source master control is nearly as the switch control rule electrode of the reality of device, when nearly source master control gate electrode is in electronegative potential, the schottky barrier width formed between monocrystalline silicon groove and source electrode is very thick, therefore do not have a large amount of electronics from source electrode one end and crossed the Schottky barrier formed between monocrystalline silicon groove and source electrode by tunneling effect, this side making monocrystalline silicon groove close on source electrode is high-impedance state, because closing between the side of drain electrode and the side closing on source electrode of monocrystalline silicon groove is series relationship, therefore overall device still has high resistance.
Simultaneously, remain between the nearly leakage auxiliary control gate electrode of high potential and drain electrode and do not form obvious electrical potential difference, this makes monocrystalline silicon groove can not form obvious band curvature at this areas adjacent, therefore in contrast to common doping type have knot or without junction field effect transistor, can not be there is obvious interband tunneling effect in major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor proposed by the invention, therefore efficiently avoid the generation of leakage current.
To sum up, by nearly source master control gate electrode and nearly acting in conjunction of leaking auxiliary control gate electrode, in contrast to common have knot and without junction field effect transistor, major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor proposed by the invention has the advantage of low current leakage.
3. high integration and outstanding switching characteristic:
The present invention adopts monocrystalline silicon groove as device channel portion, its length of effective channel is height and the horizontal channel length sum of the vertical channel portion of groove both sides, and vertical channel portion is positioned at the below of source electrode and drain electrode, therefore common plane structure is in contrast to, under the prerequisite of few chip occupying area, there is longer channel length, therefore be suitable for high integration manufacture, also slow down simultaneously short-channel effect under planar structure cause the deterioration of devices switch characteristic.
Accompanying drawing explanation
Fig. 1 is the two-dimensional structure schematic diagram that the major-minor grid of the present invention discrete control U-shaped raceway groove non-impurity-doped field-effect transistor is formed on soi substrates;
Fig. 2 to Fig. 7 is the process chart of an instantiation of the construction unit of the major-minor grid of the present invention discrete control U-shaped raceway groove non-impurity-doped field-effect transistor and the preparation method of array thereof,
Fig. 2 is step one schematic diagram,
Fig. 3 is step 2 schematic diagram,
Fig. 4 is step 3 schematic diagram,
Fig. 5 is step 4 schematic diagram,
Fig. 6 is step 5 schematic diagram,
Fig. 7 is step 6 schematic diagram.
Reference numeral is said:
1, source electrode; 2, drain electrode; 3, nearly source master control gate electrode; 4, nearly leakage auxiliary control gate electrode; 5, gate insulator; 6, insulating medium layer; 7, monocrystalline silicon groove; 8, the insulating barrier of SOI wafer; 9, the silicon substrate of SOI wafer.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described further:
The invention provides a kind of major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, by adopting non-impurity-doped or low-doped monocrystalline silicon groove 7 as the channel part of device, making device in contrast to common doping type has knot or nodeless mesh body pipe to have higher mobility.When devices function, forward bias between drain electrode 2 and source electrode 1, by the switch adopting nearly source master control gate electrode 3 and the nearly gate electrode leaking auxiliary control gate electrode 4 these two controls independent of one another to carry out control device.When devices function, leak auxiliary control gate electrode 4 nearly and remain at high potential, the thickness of the Schottky barrier that can significantly be formed between drain electrode 2 and monocrystalline silicon groove 7 like this, a large amount of electronics is made to cross potential barrier by tunneling effect, electron accumulation is formed in the interface of side and gate insulator 5 that monocrystalline silicon groove 7 closes on drain electrode 2, so just, the side making monocrystalline silicon groove 7 close on drain electrode 2 is in low resistive state when devices function, and being equivalent to common doping type has knot or the drain region without junction field effect transistor, nearly source master control gate electrode 3 is then for device is opened and the working control gate electrode of shutoff, when nearly source master control gate electrode 3 is in electronegative potential, the Schottky barrier thickness formed between monocrystalline silicon groove 7 and source electrode 1 is very thick, therefore do not have a large amount of electronics cross by tunneling effect the Schottky barrier that formed between monocrystalline silicon groove 7 and source electrode 1 and form electric current, this thicker Schottky barrier can play good blocking effect to device, even if monocrystalline silicon groove 7 is in low resistive state all the time in one end of drain electrode 2, the side closing on drain electrode 2 due to monocrystalline silicon groove 7 is therebetween series relationship with the side closing on source electrode 1, therefore overall device is still in the off state of high resistant, along with the rising gradually of nearly source master control gate electrode 3 current potential, the thickness of the Schottky barrier that monocrystalline silicon groove 7 and source electrode 1 are formed is constantly thinning, tunneling effect also constantly strengthens, when nearly source master control gate electrode 3 is in high potential, the thickness of the Schottky barrier that the thickness of the Schottky barrier that monocrystalline silicon groove 7 and source electrode 1 are formed and monocrystalline silicon groove 7 are formed with drain electrode 2 is suitable, both sides all have a large amount of electronics to pass through Schottky barrier by tunneling effect, therefore U-shaped carrier channels is formed at monocrystalline silicon groove 7 and the interface of gate insulator 5, if now there is electrical potential difference between drain electrode 2 and source electrode 1, then have obvious electric current and flow through device.
Simultaneously, in contrast to common doping type and have knot and nodeless mesh body pipe, remain between the nearly leakage auxiliary control gate electrode 4 of high potential and drain electrode 2 always and do not form obvious electrical potential difference, this makes monocrystalline silicon groove 7 can not form obvious band curvature closing near drain electrode 2, obvious interband tunneling effect can not be there is in major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor therefore proposed by the invention, therefore efficiently solve common doping type and have knot and nodeless mesh body pipe, when gate electrode is reverse-biased, the problem of a large amount of leakage current during drain voltage positively biased, can be produced.
In addition, the present invention adopts monocrystalline silicon groove 7 as device channel portion, its length of effective channel is height and the horizontal channel length sum of the vertical channel portion of groove both sides, and the vertical channel portion of both sides is positioned at the below of source electrode 1 and drain electrode 2, therefore common plane structure is in contrast to, under the prerequisite of few chip occupying area, this device has longer channel length, therefore be suitable for high integration manufacture, also slow down simultaneously short-channel effect under planar structure cause the deterioration of devices switch characteristic.
The present invention realizes the major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor with high integration, good switch special efficacy, high mobility and low current leakage by above-mentioned embodiment.
For reaching device function of the present invention, this major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor proposed by the invention, its core texture is characterized as:
1. for realizing the basic function of device and reducing leakage current, described major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, its core texture is characterized as: nearly source master control gate electrode 3 and nearly these two electrodes of auxiliary control gate electrode 4 that leak are the electrode controlled independent of one another, and realize insulated from each other by gate insulator 5 and insulating medium layer 6, wherein nearly source master control gate electrode 3 is positioned at the side that monocrystalline silicon groove 7 closes on source electrode 1, for the electric field being positioned at the vertical and horizontal channel part below source electrode 1 of monocrystalline silicon groove 7, electromotive force and Carrier Profile play control action, nearly leakage auxiliary control gate electrode 4 is positioned at the side that monocrystalline silicon groove 7 closes on drain electrode 2, for the electric field being positioned at the vertical and horizontal channel part below drain electrode 2 of monocrystalline silicon groove 7, electromotive force and Carrier Profile play control action, nearly source master control gate electrode 3 and nearly these two electrodes of auxiliary control gate electrode 4 that leak are each other in the relation be parallel to each other.
2., for realizing the basic function of device, described major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, its core texture is characterized as: source electrode 1 and drain electrode 2 contact with the two ends upper surface of monocrystalline silicon groove 7 and form Schottky barrier respectively.
3., for making device have high mobility, described major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, its core texture is characterized as: the selected SOI wafer for the formation of monocrystalline silicon groove (7) is that non-impurity-doped or impurity concentration are lower than 10
16cm
-3sOI wafer.
4. for improving nearly source master control gate electrode 3 and nearly control ability of leaking auxiliary control gate electrode 4 pairs of device channel, described major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, its core texture is characterized as: the insulating material dielectric layer with high-k of gate insulator 5 by being generated by depositing technics the inside of monocrystalline silicon groove 7, the described insulating material dielectric layer with high-k is hafnium oxide, silicon nitride or alundum (Al2O3).
5. make device have outstanding switching characteristic under high integration, described major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, its core texture is characterized as: adopt monocrystalline silicon groove 7 as the channel part of device, utilize the vertical channel portion of monocrystalline silicon groove 7 both sides, and two vertical-channels lay respectively at the below of source electrode 1 and drain electrode 2, in contrast to common plane structure, under the prerequisite of the chip area outside not occupying volume, add the length of effective channel of device, therefore the impact that device overcomes short-channel effect is contributed to, device is made to have outstanding switching characteristic under high integration.
The unit of this high integration high mobility source and drain grid auxiliary control type nodeless mesh body pipe proposed by the invention and the concrete manufacturing technology steps of array as follows:
Step one, provide a non-impurity-doped or doping content lower than 10
16cm
-3sOI wafer, the below of SOI wafer is the silicon substrate 9 of SOI wafer, it is the monocrystalline silicon thin film for the formation of monocrystalline silicon groove 7 above SOI wafer, therebetween be the insulating barrier 8 of SOI wafer, on the insulating barrier 8 of provided SOI wafer, form a series of rectangular-shaped monocrystalline silicon isolated island array for the formation of monocrystalline silicon groove 7 as shown in Figure 2 by the technique such as photoetching, etching;
Step 2, as shown in Figure 3, by after deposit dielectric above monocrystalline silicon isolated island array, throws plane surface and forms insulating medium layer 6, use as isolation between device cell;
Step 3, as shown in Figure 4, by etching technics, forms monocrystalline silicon groove 7 by each unit of monocrystalline silicon isolated island array by etching technics;
Step 4, as shown in Figure 5, there is the dielectric of high-k on the basis of the above-described procedure for the formation of gate insulator 5 in crystal column surface deposit, again by etching for the formation of nearly source master control gate electrode 3 and the nearly groove leaking auxiliary control gate electrode 4 after throwing plane surface;
Step 5, as shown in Figure 6, at crystal column surface depositing metal or polysilicon on the basis of above-mentioned steps, forms nearly source master control gate electrode 3 respectively and closely leaks auxiliary control gate electrode 4 after throwing plane surface;
Step 6, as shown in Figure 7, on the basis of the above-described procedure at crystal column surface deposit dielectric, throw plane surface and generate insulating medium layer 6 further, and the insulating medium layer 6 being etched away monocrystalline silicon groove 7 two ends upper surface by etching technics with generation source, leak through hole, and the two ends upper surface injecting metal and monocrystalline silicon groove 7 respectively in source, leakage through hole forms Schottky contacts, generates source electrode 1 and drain electrode 2 with this.
Claims (5)
1. a major-minor grid discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, comprises the silicon substrate (9) of SOI wafer, and silicon substrate (9) top of SOI wafer is the insulating barrier (8) of SOI wafer; It is characterized in that: insulating barrier (8) top of SOI wafer is monocrystalline silicon groove (7), have monocrystalline silicon groove (7), the gate insulator (5) playing mutually insulated effect between nearly source master control gate electrode (3) and nearly leakage auxiliary control gate electrode (4) in the groove of monocrystalline silicon groove (7), be respectively source electrode (1) and drain electrode (2) above monocrystalline silicon groove (7) two ends, adjacent monocrystalline silicon groove (7) and between source electrode (1) and drain electrode (2) by insulating medium layer (6) isolation.
2. major-minor grid according to claim 1 discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, it is characterized in that: nearly source master control gate electrode (3) and nearly auxiliary control gate electrode (4) these two electrodes that leak are the electrode controlled independent of one another, and realize insulated from each other by gate insulator (5) and insulating medium layer (6), wherein nearly source master control gate electrode (3) is positioned at the side that monocrystalline silicon groove (7) closes on source electrode (1), nearly leakage auxiliary control gate electrode (4) is positioned at the side that monocrystalline silicon groove (7) closes on drain electrode (2), nearly source master control gate electrode (3) and nearly auxiliary control gate electrode (4) these two electrodes that leak are each other in the relation be parallel to each other.
3. major-minor grid according to claim 1 discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, is characterized in that: the selected SOI wafer for the formation of monocrystalline silicon groove (7) is that non-impurity-doped or impurity concentration are lower than 10
16cm
-3sOI wafer.
4. major-minor grid according to claim 1 discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, is characterized in that: source electrode (1) contacts and forms Schottky barrier with the two ends upper surface of monocrystalline silicon groove (7) with drain electrode (2) respectively.
5. major-minor grid according to claim 1 discrete control U-shaped raceway groove non-impurity-doped field-effect transistor, it is characterized in that: gate insulator (5) is the insulating material dielectric layer with high-k by being generated by depositing technics the inside of monocrystalline silicon groove (7), and the described insulating material dielectric layer with high-k is hafnium oxide, silicon nitride or alundum (Al2O3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310590299.6A CN104282750B (en) | 2013-11-20 | 2013-11-20 | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310590299.6A CN104282750B (en) | 2013-11-20 | 2013-11-20 | The major-minor discrete control U-shaped raceway groove non-impurity-doped field-effect transistor of grid |
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| Publication Number | Publication Date |
|---|---|
| CN104282750A true CN104282750A (en) | 2015-01-14 |
| CN104282750B CN104282750B (en) | 2017-07-21 |
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| CN107785437A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | A kind of bracket shape grid-control source and drain resistive formula two-way switch transistor and its manufacture method |
| CN107785436A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method |
| CN108615766A (en) * | 2016-12-13 | 2018-10-02 | 现代自动车株式会社 | Semiconductor devices and its manufacturing method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108615766A (en) * | 2016-12-13 | 2018-10-02 | 现代自动车株式会社 | Semiconductor devices and its manufacturing method |
| CN107785437A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | A kind of bracket shape grid-control source and drain resistive formula two-way switch transistor and its manufacture method |
| CN107785436A (en) * | 2017-10-31 | 2018-03-09 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped raceway groove bidirectional transistor and its manufacture method |
| CN107785436B (en) * | 2017-10-31 | 2019-10-15 | 沈阳工业大学 | Source and drain resistive formula rectangular grid control U-shaped channel bidirectional transistor and its manufacturing method |
| CN107785437B (en) * | 2017-10-31 | 2020-05-29 | 沈阳工业大学 | Bracket-shaped grid-control source-drain resistance-variable bidirectional switch transistor and manufacturing method thereof |
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| CN104282750B (en) | 2017-07-21 |
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