CN104241375B - Straddling type heterojunction resonance tunneling field-effect transistor and preparing method thereof - Google Patents
Straddling type heterojunction resonance tunneling field-effect transistor and preparing method thereof Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7606—Transistor-like structures, e.g. hot electron transistor [HET]; metal base transistor [MBT]
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66931—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT]
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Abstract
The invention discloses a straddling type heterojunction resonance tunneling field-effect transistor and a preparing method thereof. The tunneling field-effect transistor comprise a tunneling source region, a channel region, a drain region and a control gate above a channel, the energy band structure of the heterogeneous tunnel junction of the tunneling source region and the channel region is a Straddling-Gap. If the field-effect transistor is an N type device, the field-effect transistor is located at the interface of the heterogeneous tunnel junction of the tunneling source region and the channel region, the tunneling source region conduction band bottom is located above the channel region conduction band bottom, and the tunneling source region valence band top is located below the channel region valence band top; if the field-effect transistor is a P type device, the tunneling source region conduction band bottom is located below the channel region conduction band bottom, and the tunneling source region valence band top is located above the channel region valence band top. According to the tunneling field-effect transistor and the preparing method of the tunneling field-effect transistor, the ON state current of the tunneling field-effect transistor can be obviously improved, and a steep sub-threshold slope is kept. The preparing technology is simple and effect, and the production cost is greatly reduced.
Description
Technical field
The invention belongs to field-effect transistor logical device field in cmos vlsi (ULSI), specifically relates to
And a kind of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor and preparation method thereof.
Background technology
Since being born from integrated circuit, microelectronics integrated technology constantly develops according to " Moore's Law " always, semiconductor device
Part size constantly reduces.As semiconductor devices enters deep sub-micron range, existing MOSFET element is due to by self-propagating
The conduction mechanism of drift is limited, and sub-threshold slope is limited by thermoelectrical potential kT/q and cannot be same with the diminution of device size
Step reduces.This results in MOSFET element leakage current and reduces the requirement for being unable to reach device dimensions shrink, the energy of whole chip
Consumption constantly rises, and chip power-consumption density is increased dramatically, and seriously hinders the integrated development of chip system.In order to adapt to integrated circuit
Development trend, the R and D work of novel super-low power consuming devices just seems particular importance.Tunneling field-effect transistor
(TFET, Tunneling Field-Effect Transistor), using the new conduction mechanism of band-to-band-tunneling (BTBT), is a kind of non-
Often there is the Novel low power consumption device for being suitable to system integration application development of development potentiality.TFET controls source and ditch by gate electrode
The tunnelling width of tunnel junctions at road interface so that source valence-band electrons are tunneling to channel conduction band (or raceway groove valence-band electrons tunnelling
To source conduction band) form tunnelling current.This new conduction mechanism breaks through heat in conventional MOS FET sub-threshold slope theoretical limit
The restriction of potential kT/q, it is possible to achieve less than the super steep sub-threshold slope of 60mV/dec, reduces device static leakage current further
Reduce device quiescent dissipation.
But, due to semiconductor band-to-band-tunneling efficiency it is low, the ON state current of TFET compared with existing MOSFET than relatively low,
The requirement in system integration application can not be met.Therefore, while more steep sub-threshold slope is kept, TFET ON states are improved
Electric current, is a very important problem for needing in TFET device applications to solve.
The content of the invention
For solving the problems, such as above-mentioned prior art, the present invention provides a kind of straddle riding type hetero-junctions resonance tunnel-through field-effect
Transistor and preparation method thereof, it is brilliant that the straddle riding type hetero-junctions resonance tunnel-through field-effect transistor can significantly improve tunneling field-effect
The ON state current of body pipe, while keep more steep sub-threshold slope.
Technical scheme is as follows：
A kind of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor, as shown in figure 1, including tunnelling source region, channel region, leakage
Area and the control gate above channel region, wherein, form heterogeneous tunnel junctions at interface of the tunnelling source region with channel region,
The band structure of the heterogeneous tunnel junctions is straddle riding type hetero-junctions (Straddling-Gap).
Above-mentioned straddle riding type hetero-junctions resonance tunnel-through field-effect transistor can be N-type device or P-type device.For N-type device
For part, at its heterogeneous tunnel junctions interface in tunnelling source region with channel region, tunnelling source region conduction band bottom is located at channel region conduction band
The top at bottom, tunnelling source region top of valence band are located at the lower section of channel region top of valence band, a) shown in such as Fig. 1-1, i.e. tunnelling area material
Electron affinity be less than channel region material electron affinity, and tunnelling area material energy gap be more than channel region material forbidden band
Width；And for P-type device, tunnelling source region conduction band bottom at its heterogeneous tunnel junctions interface in tunnelling source region with channel region
Positioned at the lower section at channel region conduction band bottom, tunnelling source region top of valence band is located above channel region top of valence band, b) shown in such as Fig. 1-1, i.e.,
The electron affinity of tunnelling area material is more than channel region material electron affinity, and tunnelling area material energy gap is less than ditch
Road area material energy gap.
Further, for N-type straddle riding type hetero-junctions resonance tunnel-through FET device, tunnelling source region is P
Type heavy doping, its doping content are about 1E18cm-3-1E20cm-3, drain region is N-type heavy doping, and its doping content is about 1E18cm-3-1E19cm-3, channel region is lightly doped for p-type, and its doping content is about 1E13cm-3-1E15cm-3；And it is different for p-type straddle riding type
For matter knot resonance tunnel-through FET device, tunnelling source region is N-type heavy doping, and its doping content is about 1E18cm-3-
1E20cm-3, drain region is p-type heavy doping, and its doping content is about 1E18cm-3-1E19cm-3, channel region is lightly doped for N-type, and which is mixed
Miscellaneous concentration is about 1E13cm-3-1E15cm-3。
Above-mentioned straddle riding type hetero-junctions resonance tunnel-through field-effect transistor can apply to Si or Ge, or other can be formed across
Ride binary or the ternary compound half of II-VI, III-V or IV-IV race of type (Straddling-Gap) heterostructure band structure
Conductor material.Also, for N-type device, it is desirable to which the electron affinity of tunnelling area material is less than channel region material electronics
Affinity, and tunnelling area material energy gap is more than channel region material energy gap；And for P-type device, it is desirable to tunnel
The electron affinity of area material is worn more than channel region material electron affinity, and tunnelling area material energy gap is less than raceway groove
Area's material energy gap.
Present invention simultaneously provides the preparation method of above-mentioned straddle riding type hetero-junctions resonance tunnel-through field-effect transistor, including following
Step：
1) one layer of oxide and one layer of nitride are deposited on a semiconductor substrate in order；
2) carry out shallow trench isolation (Shallow Trench Isolation, STI), then deposit isolated material filling out after photoetching
Chemical-mechanical planarization (Chemical Mechanical Polishing, CMP) is carried out after filling deep hole；
3) gate dielectric material and grid material is deposited, carries out photoetching and etching, form gate figure；
4) photoetching exposes tunnelling source region and selective etching goes out tunnelling source region；
5) growth selection tunnelling source region compound semiconductor, forms straddle riding type (Straddling-Gap) with channel region heterogeneous
Tunnel junctions, while carry out doping in situ to tunnelling source region；
6) photoetching exposes drain region, with photoresist and grid as mask, carries out ion implanting and forms drain region；
7) quick high-temp annealing activator impurity；
8) the consistent later process of same CMOS is finally entered, including passivation layer, opening contact hole and metallization etc. is deposited, i.e.,
Straddle riding type hetero-junctions resonance tunnel-through field-effect transistor can be obtained.
For the preparation method of above-mentioned straddle riding type hetero-junctions resonance tunnel-through field-effect transistor, step 1) in semiconductor lining
For being lightly doped or unadulterated Semiconductor substrate, the embodiment of the present invention is in step 1 at bottom) in adopt lightly doped Semiconductor substrate,
Its doping content is about 1E13cm-3-1E15cm-3.Wherein, the material of Semiconductor substrate can be II-VI, III-V or IV-IV
One kind in the germanium (GOI) on silicon (SOI) or insulator in the binary of race or ternary semiconductor, insulator.
Preferably, step 3) in gate dielectric material be SiO2、Si3N4Or high-K gate dielectric material.Preferably, step 3) in
The method of deposit gate dielectric material is conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition.
Preferably, step 3) in grid material be DOPOS doped polycrystalline silicon, metallic cobalt, metallic nickel, the silicide of metallic cobalt or gold
The silicide of category nickel.
In the preparation method of above-mentioned straddle riding type hetero-junctions resonance tunnel-through field-effect transistor, the specific embodiment of the present invention exists
Step 5) pass through molecular beam epitaxy growth selection tunnelling source region compound semiconductor；The material of tunnelling source region compound semiconductor
Selected from Si, Ge etc., other can be with the material of the Semiconductor substrate in channel region material (i.e. step 1)) form straddle riding type
(Straddling-Gap) semi-conducting material of heterostructure band structure, or other II-VI, III-V and IV-IV race binary or
Ternary semiconductor material.Step 5) doping in situ is carried out to tunnelling source region, its doping content is about 1E18cm-3-
1E20cm-3.Step 6) ion implanting formation drain region is carried out, wherein, the concentration for injecting ion is about 1E18cm-3-1E19cm-3。
The straddle riding type hetero-junctions resonance tunnel-through field-effect transistor that the present invention is provided can be N-type device or P-type device.On
State in preparation method, for N-type device, the electron affinity of tunnelling area material is affine less than channel region material electronics
Gesture, and tunnelling area material energy gap is more than channel region material energy gap；And for P-type device, tunnelling source region material
The electron affinity of material is more than channel region material electron affinity, and tunnelling area material energy gap is prohibited less than channel region material
Bandwidth.
The method have the benefit that：
Compared with existing TFET, the straddle riding type hetero-junctions tunneling field-effect transistor that the present invention is provided not only is significantly increased
Device ON state current, maintains steep sub-threshold slope.With N-type straddle riding type hetero-junctions tunneling field-effect transistor device
As a example by part, tunnelling source region is different materials with channel region, forms the heterogeneous tunnel junctions of straddle riding type, and heterojunction boundary at interface
The conduction band bottom of place's tunnelling source region is located at the top at the conduction band bottom of channel region, and the top of valence band of tunnelling source region is located at the top of valence band of channel region
Lower section.Gate electrode adds positive voltage, and raceway groove can be with drop-down, and channel region forms a triangular quantum well at tunnel junctions, when source region valency
When overlapping at band, channel region valence band and channel region conduction band three, there is resonance tunnel-through at tunnel junctions, device is opened, can be with
Obtain more steep subthreshold swing.As grid voltage increases, tunnelling width between source region valence band, channel region valence band and channel region conduction band
Reduce, when both sides tunneling efficiency is close, resonance tunnel-through efficiency is increased dramatically, tunnelling probability levels off to 1, larger so as to obtain
The ON state current of tunneling transistor.
The straddle riding type hetero-junctions tunneling field-effect transistor preparation process is simple that the present invention is provided, can effectively in CMOS collection
The integrated TFET devices in circuit, can also prepare the low power consumption integrated circuit being made up of TFET, greatly using standard technology
Production cost is reduced, technological process is simplified.
Description of the drawings
Fig. 1 is the structural representation of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor of the present invention；
Fig. 1-1 is N/P type straddle riding type hetero-junctions resonant tunneling thin film tunnel junctions straddle riding type band structure schematic diagrames；
Wherein：A) band structure for the straddle riding type of N-type straddle riding type hetero-junctions resonant tunneling thin film tunnel junctions is illustrated；b)
Band structure for p-type straddle riding type hetero-junctions resonant tunneling thin film tunnel junctions straddle riding type is illustrated；
Fig. 1-2 is N-type straddle riding type hetero-junctions resonance tunnel-through field-effect transistor fundamental diagram；
Wherein：A) be device OFF state when tunnel junctions at band structure；B) be device ON state when tunnel junctions at can band knot
Structure；
Fig. 2 removes the device profile map after nitride after forming STI isolation on a semiconductor substrate；
Fig. 3 is photoetching and etches the device profile map after forming grid；
Fig. 4 exposes the source region of TFET devices for photoetching and etches device profile map after source region；
After Fig. 5 is the heterogeneous source region of extension growth selection, and the device profile map after doping in situ is carried out to tunnelling source region；
Fig. 6 photoetching exposes the drain region of TFET devices and ion implanting forms the device profile map behind drain region；
In Fig. 1～Fig. 6,
1- Semiconductor substrates (channel region)；2-STI isolates；
3- gate dielectric layers；4- control gates；
5- photoresists；The heterogeneous tunnelling source regions of 6-；
7- drain regions；The passivation layer of 8- later process；
The metal of 9- later process.
Specific embodiment
Below in conjunction with accompanying drawing, by specific embodiment, the present invention is described further.
In the present embodiment, the structure of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor is as shown in figure 1, including tunnelling source
Area 6, channel region 1, drain region 7 and the control gate above channel region 4, is characterized in that, described tunnelling source region 6 and channel region
The band structure of 1 heterogeneous tunnel junctions is straddle riding type hetero-junctions (Straddling-Gap), as shown in Fig. 1-1.
Straddle riding type hetero-junctions resonance tunnel-through field-effect transistor can be N-type device or P-type device.For N-type device comes
Say, at heterogeneous tunnel junctions interface, tunnelling source region conduction band bottom is located at the top at channel region conduction band bottom, tunnelling source region top of valence band is located at
Below channel region top of valence band, i.e., the electron affinity of tunnelling area material is less than channel region material electron affinity, and tunnelling source
Area's material energy gap is more than channel region material energy gap；And for P-type device, it is desirable at heterogeneous tunnel junctions interface
Tunnelling source region conduction band bottom is located at the lower section at channel region conduction band bottom, and tunnelling source region top of valence band is located above channel region top of valence band, i.e. tunnel
The electron affinity of area material is worn more than channel region material electron affinity, and tunnelling area material energy gap is less than raceway groove
Area's material energy gap.
Described tunneling field-effect transistor, is characterized in that, for N-type device, tunnelling source region is p-type heavy doping,
Its doping content is about 1E18cm-3-1E20cm-3, drain region is N-type heavy doping, and its doping content is about 1E18cm-3-1E19cm-3,
Channel region is lightly doped for p-type, and its doping content is about 1E13cm-3-1E15cm-3；And for P-type device, tunnelling source region is
N-type heavy doping, its doping content are about 1E18cm-3-1E20cm-3, drain region is p-type heavy doping, and its doping content is about 1E18cm-3-1E19cm-3, channel region is lightly doped for N-type, and its doping content is about 1E13cm-3-1E15cm-3。
Described tunneling field-effect transistor can apply to GaAs/Ge semi-conducting materials, it is also possible to which being applied to other can
To form the II-VI of straddle riding type (Straddling-Gap) heterostructure band structure, the binary or ternary of III-V and IV-IV races
Compound semiconductor materials.Also, for N-type device, it is desirable to which the electron affinity of tunnelling area material is less than channel region
Material electronicses affinity, and tunnelling area material energy gap is more than channel region material energy gap；And for P-type device comes
Say, it is desirable to which the electron affinity of tunnelling area material is more than channel region material electron affinity, and tunnelling area material forbidden band width
Degree is less than channel region material energy gap.
Fig. 1-2 is N-type straddle riding type hetero-junctions resonance tunnel-through field-effect transistor fundamental diagram, wherein：A) close for device
Band structure during state at tunnel junctions；B) be device ON state when tunnel junctions at band structure.Gate electrode adds positive voltage, raceway groove energy
With drop-down, channel region forms a triangular quantum well at tunnel junctions, when source region valence band, channel region valence band and channel region conduction band three
When place overlaps, there is resonance tunnel-through at tunnel junctions, device is opened, it is possible to obtain more steep subthreshold swing.With
Grid voltage increases, and between source region valence band, channel region valence band and channel region conduction band, tunnelling width reduces, when both sides tunneling efficiency is close,
Resonance tunnel-through efficiency is increased dramatically, and tunnelling probability levels off to 1, so as to obtain the ON state current of larger tunneling transistor.
Below by taking N-type device as an example, the preparation method of above-mentioned straddle riding type hetero-junctions resonance tunnel-through field-effect transistor is illustrated,
The preparation of p-type straddle riding type hetero-junctions resonance tunnel-through FET device is similar to therewith.It is by taking N-type device as an example, above-mentioned to straddle
The implementation steps of the preparation method of type hetero-junctions resonance tunnel-through field-effect transistor as shown in Fig. 2～Fig. 6, including：
1st, in substrate doping for (about 1E13cm is lightly doped-3-1E15cm-3), crystal orientation is<001>Ge substrates 1 on
Initial deposition layer of silicon dioxide, thickness about 10nm, and deposit one layer of silicon nitride (Si3N4), thickness about 100nm, afterwards using shallow
Groove isolation technique makes active area STI isolation 2, then carries out CMP, as shown in Figure 2.
2nd, the silica on surface is removed in drift, then deposits one layer of gate dielectric layer 3, and gate dielectric layer is Al2O3, thickness be 1～
5nm；Grid material 4 is deposited using LPCVD, grid material is doped polysilicon layer, and thickness is 50～200nm.Make gate figure by lithography, carve
Erosion grid material 4 until gate dielectric layer 3, as shown in Figure 3.
3rd, photoetching exposes source region, goes out hetero-junctions tunnelling source region using high selectivity dry etching, junction depth about 50nm, such as
Shown in figure -4.
4th, heterogeneous source region 6 is formed using molecular beam epitaxy growth selection GaAs semiconductors, while original position is carried out to source region
Doping (concentration about 1E20cm-3), as shown in figure -5.
5th, photoetching exposes drain region, and with photoresist 5 and grid 4 as mask, (As, dosage is to carry out 7 ion implanting of drain region
1E14/cm-2, energy is 20keV, and injection ion concentration is about 1E18/cm-3), as shown in Figure 6.Carry out a quick high-temp to move back
Fire, and enter line activating to implanted dopant (temperature is 1050 DEG C, and the time is 10s)
6th, conventional later process is finally entered, including deposit passivation layer 8, opening contact hole and metallization 9 etc., shown in Fig. 1
For the straddle riding type hetero-junctions resonance tunnel-through field-effect transistor structure schematic diagram of the obtained N-type.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with ability
The technical staff in domain, under without departing from technical solution of the present invention ambit, using in the methods and techniques of the disclosure above
Appearance makes many possible variations and modification, or the Equivalent embodiments for being revised as equivalent variations to technical solution of the present invention.Therefore,
Every content without departing from technical solution of the present invention, according to the technical spirit of the present invention to made for any of the above embodiments any simple
Modification, equivalent variations and modification, still fall within the range of technical solution of the present invention protection.
Claims (7)
1. a kind of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor, including tunnelling source region, channel region and is located at raceway groove at drain region
The control gate of top, is characterized in that, at interface of the tunnelling source region with channel region form heterogeneous tunnel junctions, described heterogeneous
The band structure of tunnel junctions is straddle riding type hetero-junctions, and the straddle riding type hetero-junctions resonance tunnel-through field-effect transistor is N-type device,
At interface of the tunnelling source region with the heterogeneous tunnel junctions of channel region, the conduction band bottom of tunnelling source region is located at the conduction band of channel region
The top at bottom, the top of valence band of tunnelling source region are located at the lower section of the top of valence band of channel region.
2. straddle riding type hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 1, is characterized in that, the tunnelling source region is
P-type heavy doping, doping content are 1E18cm-3～1E20cm-3；The drain region is N-type heavy doping, and doping content is 1E18cm-3~
1E19cm-3；The channel region is lightly doped for p-type, and doping content is 1E13cm-3～1E15cm-3。
3. the preparation method of the straddle riding type hetero-junctions resonance tunnel-through field-effect transistor described in claim 1, comprises the following steps：
1) one layer of oxide and one layer of nitride are deposited on a semiconductor substrate in order；
2) shallow trench isolation is carried out after photoetching, then carry out chemical-mechanical planarization after depositing isolated material filling deep hole；
3) gate dielectric material and grid material is deposited, carries out photoetching and etching, form gate figure；
4) photoetching exposes tunnelling source region and selective etching goes out tunnelling source region；
5) growth selection tunnelling source region compound semiconductor, forms the heterogeneous tunnel junctions of straddle riding type with channel region, while to tunnelling source
Area carries out doping in situ；
6) photoetching exposes drain region, with photoresist and grid as mask, carries out ion implanting and forms drain region；
7) quick high-temp annealing activator impurity；
8) by later process, including deposit passivation layer, opening contact hole and metallization, straddle riding type hetero-junctions resonance tunnel-through is obtained
Field-effect transistor.
4. the preparation method of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 3, is characterized in that, step
1) Semiconductor substrate is to be lightly doped or unadulterated Semiconductor substrate；The material of Semiconductor substrate be II-VI, III-V or
One kind in the germanium GOI on silicon SOI or insulator in the binary of IV-IV races or ternary semiconductor, insulator.
5. the preparation method of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 3, is characterized in that, step
3) gate dielectric material is SiO2、Si3N4Or high-K gate dielectric material；Step 3) it is described deposit gate dielectric material method for heat
Oxidation, nitriding thermal oxidation, chemical vapor deposition or physical vapor deposition；Step 3) grid material be DOPOS doped polycrystalline silicon, metal
The silicide of cobalt, metallic nickel, the silicide of metallic cobalt or metallic nickel.
6. the preparation method of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 3, is characterized in that, step
5) it is by molecular beam epitaxy growth selection tunnelling source region compound semiconductor.
7. the preparation method of straddle riding type hetero-junctions resonance tunnel-through field-effect transistor as claimed in claim 3, is characterized in that, step
5) doping content of the doping in situ is 1E18cm-3～1E20cm-3；Step 6) ion implanting concentration be 1E18cm-3
～1E19cm-3。
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| US4835581A (en) * | 1986-07-25 | 1989-05-30 | Hitachi, Ltd. | Electron gas hole gas tunneling transistor device |
| US5021841A (en) * | 1988-10-14 | 1991-06-04 | University Of Illinois | Semiconductor device with controlled negative differential resistance characteristic |
| US5734181A (en) * | 1995-09-14 | 1998-03-31 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
| US6897098B2 (en) * | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
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| US7282739B2 (en) * | 2002-04-26 | 2007-10-16 | Nissan Motor Co., Ltd. | Silicon carbide semiconductor device |
| US8441000B2 (en) * | 2006-02-01 | 2013-05-14 | International Business Machines Corporation | Heterojunction tunneling field effect transistors, and methods for fabricating the same |
| US9209288B2 (en) * | 2012-12-21 | 2015-12-08 | Intel Corporation | Reduced scale resonant tunneling field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4835581A (en) * | 1986-07-25 | 1989-05-30 | Hitachi, Ltd. | Electron gas hole gas tunneling transistor device |
| US5021841A (en) * | 1988-10-14 | 1991-06-04 | University Of Illinois | Semiconductor device with controlled negative differential resistance characteristic |
| US5734181A (en) * | 1995-09-14 | 1998-03-31 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method therefor |
| US6897098B2 (en) * | 2003-07-28 | 2005-05-24 | Intel Corporation | Method of fabricating an ultra-narrow channel semiconductor device |
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