CN104218893B

CN104218893B - A kind of low varactor control circuit of amplitude-frequency modulation effectiveness and its implementation

Info

Publication number: CN104218893B
Application number: CN201410436398.3A
Authority: CN
Inventors: 郭斌
Original assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Current assignee: CHANGSHA JINGJIA MICROELECTRONIC Co Ltd
Priority date: 2014-09-01
Filing date: 2014-09-01
Publication date: 2017-07-28
Anticipated expiration: 2034-09-01
Also published as: CN104218893A

Abstract

The invention discloses a kind of low varactor control circuit of amplitude-frequency mudulation effect and its implementation, described varactor control circuit includes numerical-control direct-current voltage generation circuit, fixed capacitance electric capacity and varactor；The varactor control circuit working characteristics includes：First：By controlling digital input signals D, varactor VAR_MOS to be operated in two kinds of capacitance stable regions, two kinds of functions of maximum capacitance and minimum capacitance are realized；Second：Pass through fixed capacitance electric capacity C1 switching nodes OUT exchange variation characteristic, it is ensured that varactor VAR_MOS two ends AC characteristic is offseted, and DC differential pressure is constant, realizes that its equivalent capacitance does not change with node OUT voltage changes.Circuit of the present invention is only with four metal-oxide-semiconductors, and a fixed capacitance electric capacity and varactor are realized, with amplitude-frequency mudulation effect it is low, realize that difficulty is low, shake low advantage.

Description

A kind of low varactor control circuit of amplitude-frequency modulation effectiveness and its implementation

Technical field

The invention mainly relates to frequency synthesizer design field, especially a kind of varactor control for realizing gate array column capacitance Circuit structure.

Background technology

Growing with wireless communication technique, the frequency of radio frequency chip work is improved constantly, and frequency range constantly expands Greatly.Because frequency synthesizer has the advantages that the anti-interference that reference frequency output is wide, locking time is short and good, in wireless telecommunications Field is widely used.As a key modules of frequency synthesizer, DCO is mainly that frequency synthesizer provides high frequency Source oscillation signal.Different according to control signal, DCO can produce the high-frequency signal of wider frequency range, and this key characteristic Numerical control gate array column capacitance is mainly based upon to realize.

The varactor control circuit of conventional door array capacitor refers to Fig. 1.Varactor control circuit is main by four in Fig. 1 Metal-oxide-semiconductor and a varactor are constituted, and wherein NMOS tube M1 grid meets bias voltage Vbias, and drain electrode connects PMOS M2 drain electrode, Source electrode and substrate with connecing power supply GND, PMOS M2 grid connect PMOS M4 drain electrode, and drain and gate short circuit, source electrode connects PMOS M3 drain electrode, substrate meets power vd D, and PMOS M3 source electrode and substrate meet power vd D, and grid connects PMOS M2 source Pole, grid and drain electrode short circuit, PMOS M4 grid meet digital input signals D, and drain electrode connects PMOS M2 drain electrode, source electrode and lining Bottom meets power vd D, and varactor VAR_MOS grids meet output node OUT, and source electrode and drain electrode connect PMOS M2 drain electrode.

There is very strong amplitude-frequency mudulation effect (AM-TO-FM) in traditional varactor control circuit.Fig. 2 describes traditional The DCO circuit structures that gate array capacitor cell is constituted.When DCO normal works, OUT and OUTBAR output periodic sinusoidal letters Number, i.e., the grid voltage of varactor can periodically be changed；The other end (the drain terminal of varactor in gate array capacitor cell And source) voltage is straight due to by Digital Signals, being output as V1 (some DC voltage between 0 and VDD) or VDD two Flow voltage, amplitude of variation very little (relative to grid end voltage change amplitude).Therefore, the control voltage V of varactor_{G_DS}Can be with The change of DCO output waveforms and the change of generating period, cause the equivalent capacitance of varactor also can generating period change, i.e., And occur mudulation effect of the amplitude to frequency, phase noise is introduced, DCO jitter performance is reduced.

The design defect that circuit structure is present is controlled for traditional varactor, designer is proposed using fixed capacitance electric capacity Coupling process realizes that varactor two ends AC characteristic is offseted, it is ensured that varactor two ends pressure difference is basically unchanged (shown in Fig. 3).In order to The phase noise that amplitude-frequency mudulation effect is introduced in the varactor course of work is reduced, the present invention adds one in traditional structure The electric capacity C1 of fixed capacitance.Physical circuit is described as follows：NMOS tube M1 grid meets bias voltage Vbias, and drain electrode connects PMOS M2 drain electrode, source electrode and substrate with connecing power supply GND, PMOS M2 grid connect PMOS M4 drain electrode, drain and gate short circuit, Source electrode connects PMOS M3 drain electrode, and substrate meets power vd D, and PMOS M3 source electrode and substrate meet power vd D, and grid connects PMOS M2 source electrode, grid and drain electrode short circuit, PMOS M4 grid meet digital input signals D, and drain electrode connects PMOS M2 drain electrode, Source electrode and substrate meet power vd D, and fixed capacitance electric capacity C1 bottom crowns connect PMOS M2 drain electrode, and top crown meets output node OUT, Varactor VAR_MOS grids meet output node OUT, and source electrode and drain electrode connect PMOS M2 drain electrode.

Circuit is controlled for the varactor after improvement, metal-oxide-semiconductor M1, M2, M3 and M4 are varactor VAR_MOS and fixed capacitance Electric capacity C1 provides different DC voltages, and drain electrodes and source electrode of the fixed capacitance voltage C1 for varactor VAR_MOS are provided and node AC signal consistent OUT, it is ensured that varactor VAR_MOS control voltage V in the course of work_{G_DS}It is constant, it is to avoid amplitude-frequency Modulation introduces the phenomenon that shake deteriorates phase noise.

Circuit is controlled for the varactor of the present invention that Fig. 3 is provided, when digital controlled signal D is VDD, its equivalent circuit can To be expressed as Fig. 5.Assuming that the small signal amplitudes of OUT nodes, which become, turns to v_out, then varactor two ends voltage difference change can represent For：

Wherein R_eq=(R_eq2+R_eq3)//r_o1=2R_eq。

When digital controlled signal is 0, its equivalent circuit can be expressed as Fig. 6.Now the voltage difference at varactor two ends becomes Change can be expressed as：

It can to sum up obtain, work as C₁During for certain certain value, v can be effectively reduced_{G_DS}Change, that is, weaken varactor capacitance Change.

The content of the invention

The problem to be solved in the present invention is：The problem of existing for prior art, the present invention provides a kind of amplitude-frequency modulation The low varactor control circuit structure of effect, the gate array capacitor cell of the control circuit realiration can reduce gate array column capacitance and draw The phase noise entered；The present invention also provides the implementation method that a kind of varactor controls circuit.

To realize above-mentioned technical problem, solution proposed by the present invention is：A kind of low varactor of amplitude-frequency mudulation effect Control circuit, it is characterised in that：It includes the first NMOS tube (M1), the first PMOS (M2), the second PMOS (M3), the 3rd PMOS (M4), first fix capacitance electric capacity (C1), the first varactor (VAR_MOS), wherein the grid of the first NMOS tube (M1) Connect bias voltage (Vbias), drain electrode connects the first PMOS (M2) drain electrode, source electrode and substrate with connecing power supply (GND), the first PMOS The grid of pipe (M2) connects the drain electrode of the 3rd PMOS (M4), and drain and gate short circuit, source electrode connects the second PMOS (M3) drain electrode, Substrate connects power supply (VDD), and the source electrode and substrate of the second PMOS (M3) connect power supply (VDD), and grid connects the first PMOS (M2) Source electrode, grid and drain electrode short circuit, the grid of the 3rd PMOS (M4) connect digital input signals (D), and drain electrode connects the first PMOS (M2) drain electrode, source electrode and substrate connect power supply (VDD), and first fixation capacitance electric capacity (C1) bottom crown connects the first PMOS (M2) Drain electrode, top crown connects output node (OUT), and the first varactor (VAR_MOS) grid connects output node (OUT), source electrode and drain electrode Connect the first PMOS (M2) drain electrode.

The present invention is realized only with four NMOS tubes, a fixed capacitance electric capacity and a varactor, simple in construction, is had The characteristic of low jitter.

Brief description of the drawings

Fig. 1 is the schematic diagram that traditional varactor controls circuit；

Fig. 2 is the DCO structural representations that traditional varactor controls circuit realiration；

Fig. 3 is varactor control circuit diagram of the present invention；

Fig. 4 is the DCO schematic diagrames that varactor of the present invention controls circuit realiration；

Fig. 5 is the schematic diagram one that varactor of the present invention controls circuit embodiments；

Fig. 6 is the schematic diagram two that varactor of the present invention controls circuit embodiments；

Reference is in figure：D1~DN-digital controlled signal；VDD-power supply；GND-ground；Vbias-metal-oxide-semiconductor M1 Bias voltage；M1-NMOS tube；M2, M3, M4-PMOS；OUT, OUTBAR-output end；(R_eq1+R_eq2)//r_o1- D believes Number input be VDD when, the equiva lent impedance of varactor drain-source node；r_o1When the input of-D signals is 0, varactor drain-source node etc. Imitate impedance；MN1, MN2, MP1 and MP2-negative resistance structure；L and C₀- LC resonators.

Embodiment

The present invention is described in further details below with reference to the drawings and specific embodiments.

Referring to Fig. 2, Fig. 2 is the schematic diagram that varactor of the present invention controls circuit.It includes the first NMOS tube (M1), first PMOS (M2), the second PMOS (M3), the 3rd PMOS (M4), first fix capacitance electric capacity (C1), the first varactor (VAR_ MOS), wherein the grid of the first NMOS tube (M1) connects bias voltage (Vbias), drain electrode connects the first PMOS (M2) drain electrode, source With connecing power supply (GND), the grid of the first PMOS (M2) connects the drain electrode of the 3rd PMOS (M4) for pole and substrate, and drain and gate is short Connect, source electrode connects the second PMOS (M3) drain electrode, substrate connects power supply (VDD), and the source electrode and substrate of the second PMOS (M3) connect electricity Source (VDD), grid connects the first PMOS (M2) source electrode, grid and drain electrode short circuit, and the grid of the 3rd PMOS (M4) connects numeral Input signal (D), drain electrode connects the first PMOS (M2) drain electrode, and source electrode and substrate connect power supply (VDD), and first fixes capacitance electric capacity (C1) bottom crown connects the first PMOS (M2) drain electrode, and top crown connects output node (OUT), the first varactor (VAR_MOS) grid Pole connects output node (OUT), and source electrode and drain electrode connect the first PMOS (M2) drain electrode.

Varactor shown in Fig. 2 controls circuit when realizing, by controlling digital input signals D, DC voltage produces electricity Road produces different DC voltages for the drain-source end of varactor so that varactor is operated in two different capacitance saturation regions.By Change in OUT node voltages meeting generating period, and varactor VAR_MOS drain-source end is coupled to by electric capacity C1, that is, make Obtain the change of varactor both end voltage to be offseted, it is ensured that varactor two ends pressure difference ensures constant.

Varactor of the present invention control the embodiment one of circuit referring to Fig. 5, when input signal D be high level when, direct current Pressure generation circuit provides a certain DC voltage V1 (between 0 and VDD) for the drain-source end of varactor, and the both end voltage difference of varactor is V_OUT-V₁, varactor is operated in the saturation region of capacitance maximum.Electric capacity C1 couples the AC characteristic of OUT nodes so that varactor Two ends pressure difference be basically unchanged, now, varactor is operated in the maximum area of capacitance.

Varactor of the present invention control the embodiment two of circuit referring to Fig. 6, when input signal D be low level when, direct current Pressure generation circuit provides DC voltage VDD for the drain-source end of varactor, and the both end voltage difference of varactor is V_OUT-V_DD, transfiguration plumber Make in the saturation region of capacitance minimum value.Electric capacity C1 couples the AC characteristic of OUT nodes so that the two ends pressure difference of varactor is substantially not Become, now, varactor is operated in capacitance smallest region.

Each figure DC voltage generation circuit can both be realized using metal-oxide-semiconductor above, it would however also be possible to employ other devices are realized.With Circuit shown in upper each figure is merely illustrative, and device is simply replaced to the protection model that caused circuit variation also belongs to the present invention Enclose, protection scope of the present invention should be defined by claims.

Claims

1. a kind of low varactor control circuit of amplitude-frequency mudulation effect, it is characterised in that：It includes the first NMOS tube（M1）, first PMOS（M2）, the second PMOS（M3）, the 3rd PMOS（M4）, first fix capacitance electric capacity（C1）, the first varactor（VAR_ MOS）, wherein the first NMOS tube（M1）Grid connect bias voltage（Vbias）, the first NMOS tube（M1）Drain electrode meet the first PMOS Pipe（M2）Drain electrode, the first NMOS tube（M1）Source electrode and substrate with connecing power supply（GND）, the first PMOS（M2）Grid connect Three PMOSs（M4）Drain electrode, the first PMOS（M2）Drain and gate short circuit, the first PMOS（M2）Source electrode connect second PMOS（M3）Drain electrode, the first PMOS（M2）Substrate connect power supply（VDD）, the second PMOS（M3）Source electrode and substrate connect Power supply（VDD）, the second PMOS（M3）Grid connect the first PMOS（M2）Source electrode, the second PMOS（M3）Grid and leakage It is extremely short to connect, the 3rd PMOS（M4）Grid connect digital input signals（D）, the second PMOS（M3）Drain electrode connect the first PMOS （M2）Drain electrode, the second PMOS（M3）Source electrode and substrate connect power supply（VDD）, first fixes capacitance electric capacity（C1）Bottom crown connects First PMOS（M2）Drain electrode, first fix capacitance electric capacity（C1）Top crown connects output node（OUT）, the first varactor （VAR_MOS）Grid connect output node（OUT）, the first varactor（VAR_MOS）Source electrode and drain electrode connect the first PMOS （M2）Drain electrode.