CN104218893A - Varactor control circuit low in amplitude-frequency modulation efficiency and implementing method of varactor control circuit - Google Patents

Abstract

The invention discloses a varactor control circuit low in amplitude-frequency modulation efficiency and an implementing method of the varactor control circuit. The varactor control circuit comprises a numerical-control direct-current voltage generating circuit, a fixed-capacitance capacitor and a varactor, and is characterized in that the varactor VAR_MOS operates in two capacitance stability areas by controlling digital input signals D, and the maximum capacitance and the minimum capacitance are realized; according to alternating current change characteristics that the fixed-capacitance capacitor C1 is coupled with a node OUT, alternating current characteristics of two ends of the varactor VAR_MOS are offset, direct-current voltage difference is kept constant, and equivalent capacitance cannot change as change of voltage of the node OUT. By adopting four MOS tubes, one fixed-capacitance capacitor and one varactor, the varactor control circuit has the advantages of low amplitude-frequency modulation efficiency, low implementation difficulty and shaking and the like.

Description

The varactor control circuit that a kind of amplitude-frequency modulation effectiveness is low and its implementation

Technical field

The present invention relates generally to frequency synthesizer design field, especially a kind of varactor control circuit structure realizing gate array electric capacity.

Background technology

Growing along with wireless communication technique, the frequency of radio frequency chip work improves constantly, and frequency range constantly expands.There is because of frequency synthesizer the advantages such as the anti-interference that reference frequency output is wide, locking time is short and good, be widely used in field of wireless communication.As a key modules of frequency synthesizer, DCO is mainly frequency synthesizer and provides high-frequency oscillation signal source.Different according to control signal, DCO can produce the high-frequency signal of wider frequency range, and this key characteristic mainly realizes based on numerical control gate array electric capacity.

The varactor control circuit of conventional door array capacitor refers to Fig. 1.In Fig. 1, varactor control circuit is formed primarily of four metal-oxide-semiconductors and a varactor, wherein the grid of NMOS tube M1 meets bias voltage Vbias, drain electrode connects the drain electrode of PMOS M2, source electrode and substrate meet power supply ground GND, the grid of PMOS M2 connects the drain electrode of PMOS M4, drain and gate short circuit, source electrode connects the drain electrode of PMOS M3, substrate meets power vd D, the source electrode of PMOS M3 and substrate meet power vd D, grid connects the source electrode of PMOS M2, grid and drain electrode short circuit, the grid of PMOS M4 meets digital input signals D, drain electrode connects the drain electrode of PMOS M2, source electrode and substrate meet power vd D, varactor VAR_MOS grid meets output node OUT, source electrode and drain electrode connect the drain electrode of PMOS M2.

There is very strong amplitude-frequency mudulation effect (AM-TO-FM) in traditional varactor control circuit.Fig. 2 describes the DCO circuit structure that traditional gate array capacitor cell is formed.When DCO normally works, OUT and OUTBAR exports periodic sinusoidal signal, and namely the grid voltage of varactor can periodically change; The other end (drain terminal and the source) voltage of the varactor in gate array capacitor cell is owing to being subject to Digital Signals, export as V1 (the some direct voltages between 0 and VDD) or VDD two direct voltages, amplitude of variation very little (relative to grid terminal voltage amplitude of variation).Therefore, the control voltage V of varactor _{g_DS}meeting change of generating period along with the change of DCO output waveform, causes the equivalent capacitance of varactor also to change by generating period, namely the mudulation effect of amplitude to frequency occurs, introduces phase noise, reduce the jitter performance of DCO.

For the design defect that traditional varactor control circuit structure exists, designer proposes to adopt fixing capacitance capacitive coupling method to realize varactor two ends AC characteristic and offsets, and ensures varactor two ends pressure reduction substantially constant (shown in Fig. 3).In order to reduce the phase noise that in the varactor course of work, amplitude-frequency mudulation effect is introduced, the present invention adds the electric capacity C1 of a fixing capacitance in traditional structure.Physical circuit is described below: the grid of NMOS tube M1 meets bias voltage Vbias, drain electrode connects the drain electrode of PMOS M2, source electrode and substrate meet power supply ground GND, the grid of PMOS M2 connects the drain electrode of PMOS M4, drain and gate short circuit, source electrode connects the drain electrode of PMOS M3, substrate meets power vd D, the source electrode of PMOS M3 and substrate meet power vd D, grid connects the source electrode of PMOS M2, grid and drain electrode short circuit, the grid of PMOS M4 meets digital input signals D, drain electrode connects the drain electrode of PMOS M2, source electrode and substrate meet power vd D, fixing capacitance electric capacity C1 bottom crown connects the drain electrode of PMOS M2, top crown meets output node OUT, varactor VAR_MOS grid meets output node OUT, source electrode and drain electrode connect the drain electrode of PMOS M2.

For the varactor control circuit after improvement, metal-oxide-semiconductor M1, M2, M3 and M4 provide different direct voltages for varactor VAR_MOS and fixing capacitance electric capacity C1, the drain electrode that fixing capacitance voltage C1 is varactor VAR_MOS provides the AC signal consistent with node OUT with source electrode, ensure that the control voltage V of varactor VAR_MOS in the course of work _{g_DS}constant, avoid amplitude-frequency modulation and introduce the phenomenon that shake worsens phase noise.

For the varactor control circuit of the present invention that Fig. 3 provides, when digital controlled signal D is VDD, its equivalent electric circuit can be expressed as Fig. 5.Suppose that the small signal amplitudes of OUT node is changed to v _out, then the voltage difference change at varactor two ends can be expressed as:

$v_{G\_\mathrm{DS}}=\frac{v_{\mathrm{OUT}}}{1+2(C_1+C_{\mathrm{VAR}\_\mathrm{MOS}})s{R}_{\mathrm{eq}}}---\left(1\right)$

Wherein R _eq=(R _eq2+ R _eq3) //r _o1=2R _eq.

When digital controlled signal is 0, its equivalent electric circuit can be expressed as Fig. 6.The now voltage difference change at varactor two ends can be expressed as:

$v_{G\_\mathrm{DS}}=\frac{v_{\mathrm{OUT}}}{1+(C_1+C_{\mathrm{VAR}\_\mathrm{MOS}})s{r}_{o1}}---\left(2\right)$

To sum up can obtain, work as C ₁during for certain certain value, v can be effectively reduced _{g_DS}change, namely weaken the change of varactor capacitance.

Summary of the invention

The problem to be solved in the present invention is: for prior art Problems existing, the invention provides the varactor control circuit structure that a kind of amplitude-frequency mudulation effect is low, the gate array capacitor cell that this control circuit realizes can reduce the phase noise that gate array electric capacity is introduced; The present invention also will provide a kind of implementation method of described varactor control circuit.

For realizing above-mentioned technical problem, the solution that the present invention proposes is: the varactor control circuit that a kind of amplitude-frequency mudulation effect is low, it is characterized in that: it comprises the first NMOS tube (M1), first PMOS (M2), second PMOS (M3), 3rd PMOS (M4), first fixing capacitance electric capacity (C1), first varactor (VAR_MOS), wherein the grid of the first NMOS tube (M1) connects bias voltage (Vbias), drain electrode connects the drain electrode of the first PMOS (M2), source electrode and substrate be (GND) with connecing power supply, the grid of the first PMOS (M2) connects the drain electrode of the 3rd PMOS (M4), drain and gate short circuit, source electrode connects the drain electrode of the second PMOS (M3), substrate connects power supply (VDD), the source electrode of the second PMOS (M3) and substrate connect power supply (VDD), grid connects the source electrode of the first PMOS (M2), grid and drain electrode short circuit, the grid of the 3rd PMOS (M4) connects digital input signals (D), drain electrode connects the drain electrode of the first PMOS (M2), source electrode and substrate connect power supply (VDD), first fixing capacitance electric capacity (C1) bottom crown connects the drain electrode of the first PMOS (M2), top crown connects output node (OUT), first varactor (VAR_MOS) grid connects output node (OUT), source electrode and drain electrode connect the drain electrode of the first PMOS (M2).

The present invention only adopts four NMOS tube, a fixing capacitance electric capacity and a varactor to realize, and structure is simple, has the characteristic of low jitter.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of traditional varactor control circuit;

Fig. 2 is the DCO structural representation that traditional varactor control circuit realizes;

Fig. 3 is varactor control circuit schematic diagram of the present invention;

Fig. 4 is the DCO schematic diagram that varactor control circuit of the present invention realizes;

Fig. 5 is the schematic diagram one of varactor control circuit embodiment of the present invention;

Fig. 6 is the schematic diagram two of varactor control circuit embodiment of the present invention;

In figure, Reference numeral is: D1 ~ DN-digital controlled signal; VDD-power supply; GND-ground; The bias voltage of Vbias-metal-oxide-semiconductor M1; M1-NMOS tube; M2, M3, M4-PMOS; OUT, OUTBAR-output; (R _eq1+ R _eq2) //r _o1when-D signal is input as VDD, the equiva lent impedance of varactor drain-source node; r _o1when-D signal is input as 0, the equiva lent impedance of varactor drain-source node; MN1, MN2, MP1 and MP2-negative resistance structure; L and C ₀-LC resonant cavity.

Embodiment

Below with reference to the drawings and specific embodiments, the present invention is described in further details.

Refer to Fig. 2, Fig. 2 is the schematic diagram of varactor control circuit of the present invention.It comprises the first NMOS tube (M1), first PMOS (M2), second PMOS (M3), 3rd PMOS (M4), first fixing capacitance electric capacity (C1), first varactor (VAR_MOS), wherein the grid of the first NMOS tube (M1) connects bias voltage (Vbias), drain electrode connects the drain electrode of the first PMOS (M2), source electrode and substrate be (GND) with connecing power supply, the grid of the first PMOS (M2) connects the drain electrode of the 3rd PMOS (M4), drain and gate short circuit, source electrode connects the drain electrode of the second PMOS (M3), substrate connects power supply (VDD), the source electrode of the second PMOS (M3) and substrate connect power supply (VDD), grid connects the source electrode of the first PMOS (M2), grid and drain electrode short circuit, the grid of the 3rd PMOS (M4) connects digital input signals (D), drain electrode connects the drain electrode of the first PMOS (M2), source electrode and substrate connect power supply (VDD), first fixing capacitance electric capacity (C1) bottom crown connects the drain electrode of the first PMOS (M2), top crown connects output node (OUT), first varactor (VAR_MOS) grid connects output node (OUT), source electrode and drain electrode connect the drain electrode of the first PMOS (M2).

Varactor control circuit shown in Fig. 2 is when realizing, and by control figure input signal D, DC voltage generation circuit is that the drain-source end of varactor produces different direct voltages, makes varactor be operated in two different capacitance saturation regions.Because OUT node voltage can change by generating period, and be coupled to the drain-source end of varactor VAR_MOS by electric capacity C1, namely make varactor both end voltage change and offset, ensure that varactor two ends pressure reduction ensures constant.

The embodiment one of varactor control circuit of the present invention refers to Fig. 5, and when input signal D is high level, the drain-source end that DC voltage generation circuit is varactor provides a certain direct voltage V1 (between 0 and VDD), and the both end voltage difference of varactor is V _oUT-V ₁, varactor is operated in the saturation region of capacitance maximum.The AC characteristic of electric capacity C1 coupling OUT node, make the two ends pressure reduction of varactor substantially constant, now, varactor is operated in the maximum district of capacitance.

The embodiment two of varactor control circuit of the present invention refers to Fig. 6, and when input signal D is low level, the drain-source end that DC voltage generation circuit is varactor provides direct voltage VDD, and the both end voltage difference of varactor is V _oUT-V _dD, varactor is operated in the saturation region of capacitance minimum value.The AC characteristic of electric capacity C1 coupling OUT node, make the two ends pressure reduction of varactor substantially constant, now, varactor is operated in capacitance smallest region.

Each figure DC voltage generation circuit both can adopt metal-oxide-semiconductor to realize above, and other devices also can be adopted to realize.Circuit shown in each figure is only example above, and device is replaced simply caused circuit variation and also belong to protection scope of the present invention, protection scope of the present invention should be as the criterion with claims.

Claims (1)

1. the varactor control circuit that an amplitude-frequency mudulation effect is low and its implementation, it is characterized in that: it comprises the first NMOS tube (M1), first PMOS (M2), second PMOS (M3), 3rd PMOS (M4), first fixing capacitance electric capacity (C1), first varactor (VAR_MOS), wherein the grid of the first NMOS tube (M1) connects bias voltage (Vbias), drain electrode connects the drain electrode of the first PMOS (M2), source electrode and substrate be (GND) with connecing power supply, the grid of the first PMOS (M2) connects the drain electrode of the 3rd PMOS (M4), drain and gate short circuit, source electrode connects the drain electrode of the second PMOS (M3), substrate connects power supply (VDD), the source electrode of the second PMOS (M3) and substrate connect power supply (VDD), grid connects the source electrode of the first PMOS (M2), grid and drain electrode short circuit, the grid of the 3rd PMOS (M4) connects digital input signals (D), drain electrode connects the drain electrode of the first PMOS (M2), source electrode and substrate connect power supply (VDD), first fixing capacitance electric capacity (C1) bottom crown connects the drain electrode of the first PMOS (M2), top crown connects output node (OUT), first varactor (VAR_MOS) grid connects output node (OUT), source electrode and drain electrode connect the drain electrode of the first PMOS (M2).