CN104217938B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN104217938B CN104217938B CN201410425745.2A CN201410425745A CN104217938B CN 104217938 B CN104217938 B CN 104217938B CN 201410425745 A CN201410425745 A CN 201410425745A CN 104217938 B CN104217938 B CN 104217938B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
Abstract
A kind of forming method of semiconductor structure, including: providing surface to be formed with the substrate of some grid structures, and gate structure sidewall surface is formed with side wall, the substrate surface between adjacent side wall has impurity；Being placed in by substrate in ise chamber, the substrate surface between adjacent side wall carries out first step ise process, first step ise processes and goes the removal of impurity for for the first time, and first step ise processes provides the first radio-frequency power and the first Dc bias；Substrate surface is carried out second step ise process, second step ise processes and goes the removal of impurity for for the second time, second step ise processes provides the second radio-frequency power and the second Dc bias, and second radio-frequency power less than the first radio-frequency power, the second Dc bias is more than the first Dc bias.The present invention makes the direction of advance of the plasma beam during sputter etching craft be perpendicular to substrate surface, and etching is gone deimpurity better, and reduces the beam-plasma bombardment to side wall surface.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, particularly to the forming method of a kind of semiconductor structure.
Background technology
Along with semiconductor device integrated level constantly increases, the critical dimension that semiconductor device is relevant constantly reduces,
Occur in that a lot of problem accordingly, as semiconductor device drain-source pole and grid structure sheet resistance with contact
Resistance increases accordingly, causes the response speed of semiconductor device to reduce, and postponing occurs in signal.Therefore, low
The interconnection structure of resistivity becomes the key element manufacturing highly intergrated semiconductor device.
In order to reduce the contact resistance of semiconductor device drain-source pole and grid structure, introduce metal silicide
Process, described metal silicide has relatively low resistivity, can be substantially reduced drain-source pole and grid
The contact resistance of electrode structure.Metal silicide and self-aligned metal silicate and formation process are by widely
For reducing sheet resistance and the contact resistance of semiconductor device source-drain electrode and grid structure, thus reduce electricity
The resistance capacitance delays time.
But, the electric property of the semiconductor structure that prior art is formed still has much room for improvement.
Summary of the invention
The present invention solve problem be how to improve etching remove impurity on substrate surface ability, reduce wait from
The daughter bundle etching to side wall surface, thus improve reliability and the electric property of semiconductor structure.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: provide
Substrate, described substrate surface is formed with several grid structures, and gate structure sidewall surface is formed with side
Wall, the substrate surface between adjacent side wall has impurity；Described substrate is placed in ise chamber,
Substrate surface between described adjacent side wall carries out first step ise process, and the described first step sputters
Etching processing provides the first radio-frequency power and the first Dc bias, and described first step ise processes to be used
Described impurity is removed in for the first time；Substrate surface between described adjacent side wall carries out second step sputtering carve
Erosion processes, and described second step ise processes provides the second radio-frequency power and the second Dc bias, and
Described second radio-frequency power is less than the first radio-frequency power, and the second Dc bias is more than the first Dc bias, institute
State the process of second step ise and remove described impurity for for the second time.
Optionally, described first step ise processes and in second step ise processing procedure, to
Thering is provided working gas in ise chamber, described working gas is Ar.
Optionally, described first radio-frequency power and the second radio-frequency power are used for being formed Ar plasma beam, and
Under the second radio-frequency power, Ar plasma beam energy is less than Ar plasma beam energy under the first radio-frequency power
Amount.
Optionally, described first Dc bias and the second Dc bias are before adjusting Ar plasma beam
Enter direction.
Optionally, in first step ise processing procedure, Ar flow is 45sccm to 55sccm,
In second step ise processing procedure, Ar flow is 45sccm to 55sccm.
Optionally, described first Dc bias is 80V to 100V, and described second Dc bias is 110V
To 130V.
Optionally, described first radio-frequency power includes the first bias power and first coil power, described
Second radio-frequency power includes the second bias power and the second coil power, and the first bias power is 50W
To 70W, first coil power is 280W to 320W, and the second bias power is 40W to 60W, the
Two coil power is 160W to 200W.
Optionally, before carrying out first step ise process, further comprise the steps of: and carve to described sputtering
It is passed through working gas in erosion chamber.
Optionally, after carrying out second step ise process, further comprise the steps of: and make ise chamber
It is in Dc bias closed mode, trickle state and state of bleeding.
Optionally, further comprise the steps of: the substrate surface in grid structure both sides and form metal level；To described
Metal level makes annealing treatment, and metal level is converted into metal silicide layer.
Compared with prior art, technical scheme has the advantage that
In the forming method of the semiconductor structure that the embodiment of the present invention provides, substrate is placed in ise chamber
In room, the substrate surface between adjacent side wall carrying out first step ise process, the described first step is spattered
Penetrate etching processing and go the removal of impurity for for the first time, first step ise process provide the first radio-frequency power with
And first Dc bias；Substrate surface between adjacent side wall is carried out second step ise process, the
Two step ises process and go the removal of impurity for for the second time, and second step ise processes provides the second radio frequency
Power and the second Dc bias, and the second radio-frequency power is less than the first radio-frequency power, the second Dc bias
More than the first Dc bias.Owing to the second Dc bias is more than the first Dc bias, therefore spatter at second step
Penetrating in etch processes, plasma beam is more perpendicular to substrate surface so that arrive substrate surface
Plasma content is bigger, thus improves etching and remove the ability of impurity on substrate surface；Further, due to
In second step ise processing procedure, plasma beam, more perpendicular to substrate surface, reduces side wall
Surface is by the probability of plasma bombardment, thus prevents the particle on side wall surface from being fallen by corrasion
Fall at substrate surface.
Meanwhile, in second step ise processing procedure, the second radio-frequency power is less than the first radio-frequency power,
Reduce second step ise processing procedure plasma bundle energy (plasma content reduce, etc.
Energy of plasma reduces), thus prevent from causing second step ise owing to the second Dc bias is relatively big
Process excessive to the etch rate of substrate surface, it is to avoid second step ise processes and substrate was caused quarter
Erosion.
Further, in first step ise processing procedure, if the first Dc bias is excessive, then Ar
The speed moved to substrate surface will be very big, easily cause first step ise and process substrate surface
Etch rate is excessive, and substrate surface is caused etching injury, affects the performance of semiconductor structure.For this
In inventive embodiments, first step ise processes the first Dc bias providing less, described second direct current
Bias is 80V to 100V.
Further, after carrying out second step ise process, further comprise the steps of: and make sputtering carve successively
Erosion chamber is in Dc bias closed mode and trickle state.Described Dc bias closed mode is still to spattering
There is provided plasma in penetrating etching cavity, prevent from causing owing to plasma suddenly disappears substrate surface to have
There is more impurity；Described trickle state provides electroneutral Ar, makes the positively charged transfer of substrate surface
To electroneutral Ar, so that substrate surface presents electric neutrality state, it is to avoid substrate surface positive charge is assembled
The infringement that semiconductor structure is brought.
Accompanying drawing explanation
The cross-sectional view of the semiconductor structure that Fig. 1 provides for an embodiment；
The cross-section structure that Fig. 2 to Fig. 9 forms process for the semiconductor structure that one embodiment of the invention provides shows
It is intended to.
Detailed description of the invention
From background technology, the electric property of the semiconductor structure that prior art is formed still has much room for improvement.
It has been investigated that, during semiconductor structure is formed, forming source region, drain region and grid knot
After structure, in order to reduce the contact resistance of semiconductor structure, generally at source region, drain region and grid structure
Surface forms metal silicide, in order to improve the quality of the metal silicide of formation, reduces metal silicide
The resistivity of material, it is desirable to source region, drain region and grid structure surface have higher cleanliness factor.To this end,
Before forming metal silicide, it is cleaned source region, drain region and grid structure surface processing, goes
Except source region, drain region and the impurity on grid structure surface.
Concrete, refer to Fig. 1, it is provided that substrate 100, be formed with some grid on described substrate 100 surface
Electrode structure 101, grid structure 101 sidewall surfaces is formed with side wall 102, the lining of grid structure 101 both sides
Source region and drain region it is formed with at the end 100；To substrate 100 surface between described neighboring gate structures 101
It is cleaned processing 103, removes the impurity on substrate 100 surface.
In order to avoid cleaning processes 103, substrate 100 surface is brought unnecessary impurity, use physics to spatter
Penetrate etching method carry out described cleaning process 103, during physical sputtering, it is provided that working gas, such as,
Ar, it is provided that radio-frequency power (RF Power), described radio-frequency power is for forming Ar plasma by Ar ionization
Body bundle.The size of described radio-frequency power and the energy direct proportionality of Ar plasma beam, Ar plasma
The energy of body bundle removes the ability direct proportionality of the impurity on substrate 100 surface with etching.
Therefore to make cleaning process 103 etchings remove the impurity ability on substrate 100 surface relatively by force, generally
Using bigger radio-frequency power that Ar is carried out ionization process, radio-frequency power includes bias power (Bias Power)
And coil power (Coil Power), described bias power is 50W to 70W, and described coil power is
280W to 320W.
During physical sputtering, in addition it is also necessary to DC offset voltage (DC Bias), Ar plasma are provided
Bundle is in positive ion mode, it is provided that after DC offset voltage, in the environment of DC offset voltage, Ar etc. from
Daughter bundle is advanced to substrate 100 surface direction, thus reaches etching and remove the mesh of substrate 100 surface impurity
's.
Owing to providing bigger radio-frequency power during physical sputtering, if reoffering bigger direct current biasing
Voltage, the etch rate on the most described physical sputter etch substrate 100 surface is excessive, easily to substrate 100
Unnecessary etching is caused on surface；Therefore the DC offset voltage provided during physical sputtering should not mistake
Greatly, described DC offset voltage is 80V to 100V.
But, owing to described DC offset voltage is relatively low, the electric field intensity that DC offset voltage produces is relatively low,
Advancing in the direction causing Ar plasma beam to be difficult to be exactly perpendicularly to substrate 100 surface, causes Ar etc.
Part plasma in gas ions bundle does not bombards substrate 100 surface and bombards side wall 101 surface.One side
Face causes the amount of plasma arriving substrate 100 surface to reduce, and cleaning processes 103 etchings and removes substrate 100
The ability of surface impurity reduces；On the other hand side wall 101 is caused due to plasma bombardment side wall 101
Atom drop and form oxide impurity or organonitrogen impurities on substrate 100 surface.
As the above analysis, after cleaning processes 103, substrate 100 surface still has more impurity；
When described substrate 100 surface with impurity forms metal silicide, the property of the metal silicide of formation
Can be poor, the resistivity of metal silicide is higher, and the electric property causing semiconductor structure is poor.
To this end, the present invention provides the forming method of a kind of semiconductor structure, it is provided that substrate, described substrate table
Face is formed with several grid structures, and gate structure sidewall surface is formed with side wall, between adjacent side wall
Substrate surface there is impurity；Described substrate is placed in ise chamber, to described adjacent side wall it
Between substrate surface carry out first step ise process, described first step ise processes offer first
Radio-frequency power and the first Dc bias, described first step ise processes for removal for the first time described
Impurity；Substrate surface between described adjacent side wall is carried out second step ise process, described second
Step ise processes provides the second radio-frequency power and the second Dc bias, and described second radio-frequency power
Less than the first radio-frequency power, the second Dc bias is more than the first Dc bias, described second step ise
Process and remove described impurity for for the second time.The present invention sputters in the first step with the first Dc bias and carves
After erosion processes, it is provided that the second step ise with the second bigger Dc bias processes, bigger
Under second Dc bias effect, plasma beam is more perpendicular to substrate surface, reaches substrate surface
Plasma beam is more so that etching remove substrate surface impurity ability more preferably, and due to etc. from
Daughter bundle is more perpendicular to substrate surface, decreases the plasma beam bombardment to side wall, and preventing need not
The impurity wanted drops at substrate surface, improves reliability and the electric property of semiconductor structure.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
The cross-section structure that Fig. 2 to Fig. 9 forms process for the semiconductor structure that one embodiment of the invention provides shows
It is intended to.
Refer to Fig. 2, it is provided that substrate 200, form several grid structures on described substrate 200 surface.
Described substrate 200 is the one in the silicon on monocrystal silicon, polysilicon, non-crystalline silicon or insulator；Institute
Stating substrate 200 can also be for Si substrate, Ge substrate, GeSi substrate or GaAs substrate；Described substrate
200 surfaces can also form some epitaxial interface layers or strained layer to improve the electric property of semiconductor device.
Can also form isolation structure in described substrate 200, existing isolation structure generally uses shallow ridges
Groove is isolated.The packing material of described fleet plough groove isolation structure can be silicon oxide, silicon nitride, silicon oxynitride
In one or more, fleet plough groove isolation structure is mainly used for isolating adjacent active regions (AA, Active
Area), prevent from being electrically connected between different semiconductor device.
Described grid structure includes: is positioned at the gate dielectric layer 201 on substrate 200 surface and is positioned at gate medium
The grid conductive layer 202 on layer 201 surface.
Described grid structure is polysilicon gate construction, dummy gate structure or metal gate structure.
In one embodiment, when described grid structure is polysilicon gate construction, described gate dielectric layer 201
Material be silicon oxide, silicon nitride or silicon oxynitride, the material of described grid conductive layer 202 be polysilicon or
The polysilicon of doping.
In another embodiment, when described grid structure is dummy gate structure, described gate dielectric layer 201
Material is silicon oxide, silicon nitride or silicon oxynitride, and the material of described grid conductive layer 202 is polysilicon.
In other embodiments, described grid structure is metal gate structure, and described gate dielectric layer 201 is
Single layer structure or laminated construction.When described gate dielectric layer 201 is single layer structure, described gate dielectric layer 201
Material be that (high K medium material refers to relative dielectric constant more than silicon oxide to high K medium material
The material of relative dielectric constant), wherein, described high K medium material is HfO2、HfSiO、HfSiON、
HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3；When described gate dielectric layer 201 is laminated construction, institute
Stating gate dielectric layer 201 and include boundary layer and dielectric layer, wherein, the material of boundary layer is silicon oxide, nitrogen
SiClx or silicon oxynitride, the material of dielectric layer is high K medium material.The material of described grid conductive layer 202
For Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN or
WSi。
The present embodiment does exemplary illustrated as a example by described grid structure is as polysilicon gate construction.Concrete,
The processing step forming described grid structure includes: form gate dielectric film on described substrate 200 surface；?
Described gate dielectric film surface forms gate-conductive film；Patterned mask layer is formed on described gate-conductive film surface；
With described patterned mask layer as mask, etch described gate-conductive film and gate dielectric film forms grid knot
Structure, described grid structure includes being positioned at the gate dielectric layer 201 on substrate 200 surface and being positioned at gate dielectric layer
The grid conductive layer 202 on 201 surfaces.
The present embodiment does exemplary illustrated as a example by being formed with 2 grid structures on substrate 200 surface,
In other embodiments, could be formed with several grids such as 1,3,4 or 8 at substrate surface
Structure.
Refer to Fig. 3, formed and be covered in substrate 200 surface, gate structure sidewall and the side wall of top surface
Film 203.
Described side wall film 203 provides basis for being subsequently formed side wall, uses chemical gaseous phase deposition, physics gas
Deposition or atom layer deposition process, form described side wall film 203 mutually.
Described side wall film 203 is single layer structure or laminated construction, and the material of described side wall film 203 is oxidation
Silicon, silicon nitride or silicon oxynitride.
The present embodiment does exemplary illustrated as a example by described side wall film 203 is as single layer structure, uses chemistry gas
Phase depositing operation forms described side wall film 203, and the material of described side wall film 203 is silicon nitride.
Refer to Fig. 4, use non-mask etching technique to etch described side wall film 203 (refer to Fig. 3),
Gate structure sidewall surface forms side wall 204.
Described non-mask etching technique is dry etching.
In the present embodiment, described dry etch process is reactive ion etching process, and described reactive ion is carved
The etching gas of etching technique includes CF4And CHF3。
Along with the bulk between neighboring gate structures is more and more less, dry etch process is to grid structure
The etch rate of bottom section is more and more obvious with the difference of the etch rate of grid structure top area, dry
Method etching technics is less than the etching to grid structure top area to the etch rate of grid structure bottom section
Speed, therefore after non-mask etching technique completes, the cross-section structure of the side wall 204 of formation presents narrow
Lower wide pattern.
Refer to Fig. 5, the substrate 200 of described grid structure both sides is doped process, at described substrate
Forming doped region 205 in 200, substrate 200 surface between adjacent side wall 204 has impurity.
The dopant ion of described doped region 205 is N-type ion or p-type ion.In one embodiment,
When the semiconductor structure formed is nmos device, the dopant ion of described doped region 205 is N-type ion,
Described N-type ion is P, As or Sb；In another embodiment, the semiconductor structure of formation is PMOS
During device, the dopant ion of described doped region 205 is p-type ion, described p-type ion be B, Ga or
In。
In the present embodiment, ion implantation technology is used to carry out described doping treatment.
In other embodiments, can also be formed with stressor layers in doped region, described stressor layers is used for improving
Put on the stress effect of channel region, improve the carrier mobility in channel region, thus improve quasiconductor
The operating rate of structure.The processing step forming described stressor layers includes: at the substrate of grid structure both sides
Interior formation groove；Selective epitaxial process is used to form the stressor layers filling full groove；Described grid is tied
The substrate of structure both sides and stressor layers carry out ion implanting, form doped region.In one embodiment, half
When conductor structure is nmos device, the material of described stressor layers is SiC or SiCP；In another embodiment
In, when semiconductor structure is PMOS device, the material of described stressor layers is SiGe or SiGeB.
In order to reduce the contact resistance of semiconductor structure, improve the operating rate of semiconductor structure, formed
After doped region 205, in addition it is also necessary to form metal silicide layer on substrate 200 surface of grid structure both sides,
That is, metal silicide layer is formed on doped region 205 surface, to reduce the contact resistance of semiconductor structure.
The processing step forming metal silicide layer includes: form gold on substrate 200 surface of grid structure both sides
Belong to layer；Making annealing treatment described metal level, the material of the material of described metal level and substrate 200 is sent out
Raw metal silication reaction, is converted into metal silicide layer by metal level.
Owing to being formed between metal level, the substrate 200 of grid structure both sides experienced by repeatedly PROCESS FOR TREATMENT,
Such as, form grid structure, form side wall 204 and form the PROCESS FOR TREATMENT such as doped region 205, described
PROCESS FOR TREATMENT can cause substrate 200 remained on surface to have impurity；Directly there is the substrate 200 of impurity if follow-up
Forming metal layer on surface and carry out metal silication reaction, can cause the metal silicide layer material of formation
Resistivity is higher, substrate 200 and the contact interface poor performance of metal silicide interlayer.
To this end, the present embodiment is before forming metal level, further comprises the steps of: etching and remove substrate 200 table
The impurity in face.
Refer to Fig. 6, substrate 200 is placed in ise chamber, between described adjacent side wall 204
Substrate 200 surface carry out first step ise process 206, described first step ise process 206
Go the removal of impurity for for the first time, first step ise processes 206 offer the first radio-frequency powers and first
Dc bias.
During described first step ise processes 206, in ise chamber, provide working gas,
Plasma beam is formed, the plasma bombardment lining in beam-plasma after described working gas is plasmarized
The impurity on surface, the end 200 removes described impurity with etching.In the present embodiment, described working gas is Ar,
Ar flow is 45sccm to 55sccm.
Described first radio-frequency power is used for being formed Ar plasma beam, and the first radio-frequency power includes the first biasing
Power and first coil power.First step ise is used to process 206, by Ar plasma beam
The effect on bombardment substrate 200 surface, passes to the miscellaneous of substrate 200 surface by the energy of Ar plasma beam
Matter, impurity departs from substrate 200 surface after obtaining energy, thus it is miscellaneous to reach etching removal substrate 200 surface
The effect of matter.
If during first step ise processes 206, the energy of Ar plasma beam is excessive, then substrate
Atom beyond 200 surface impurities obtains bigger energy, described in there is the atom of large energy depart from substrate
200 surfaces, can cause unnecessary etching to substrate 200；The most described first step ise processes
The energy of the Ar plasma beam in 206 is unsuitable too high.If the energy of Ar beam-plasma is too low, impurity obtains
The energy obtained is relatively low, and the most described impurity is difficult to depart from from substrate 200 surface.
And the size of the first radio-frequency power and the energy proportional of Ar plasma beam.First radio frequency
Power is the biggest, and the Ar plasma content in Ar plasma beam is the most, and the energy of Ar plasma is more
Greatly, then the energy of Ar beam-plasma is the biggest；First radio-frequency power is the least, the Ar in Ar plasma beam
Plasma content is the fewest, and the energy of Ar plasma is the lowest, then the energy of Ar plasma beam is the least.
Amid all these factors considering, in the present embodiment, the first bias power is 50W to 70W, First Line
Circle power is 280W to 320W.As a specific embodiment, the first bias power is 60W, first
Coil power is 300W.
Ar plasma beam is with positive electricity, in the case of not applying Dc bias, Ar plasma beam
Direction of advance is disordered state, the Ar plasma i.e. in ise chamber, in Ar plasma beam
The probability advanced to all directions is essentially identical.In order to make Ar plasma beam towards before substrate 200 surface
Entering, first step ise processes 206 and also provides for the first Dc bias, and described first Dc bias is used for
Adjust the direction of advance of Ar plasma beam；Under the effect of the first Dc bias, make Ar plasma
Advance in Shu Chaoxiang substrate 200 surface, thus the Ar plasma bombardment substrate 200 in Ar plasma beam
Surface, reaches etching and removes the purpose of substrate 200 surface impurity.
First Dc bias also with Ar beam-plasma advanced speed proportional, if the first Dc bias
Excessive, then Ar beam-plasma will quickly arrive substrate 200 surface, easily cause working gas and also be not up to
Reach substrate 200 surface during plasmoid, cause the Ar plasma arriving substrate 200 surface
Physical ability is less is even not up to plasmoid, causes first step ise to process 206 etchings and goes
Deimpurity ability is low.
Further, owing in the present embodiment, the first bias voltage and first coil voltage are the biggest, Ar etc. from
The energy of daughter is relatively big, if the first Dc bias is the biggest, then Ar plasma reaches substrate 200 surface
Speed quickly, easily cause first step ise process 206 etch rates to substrate 200 surface
Excessive, over etching is caused on substrate 200 surface, affects the performance of semiconductor structure.
To this end, the first Dc bias is unsuitable excessive in the present embodiment, described first Dc bias be 80V extremely
100V.As a specific embodiment, described first Dc bias is 90V.
In the present embodiment, process before 206 carrying out first step ise, it is also possible to include step:
Being passed through working gas in ise chamber, described working gas is Ar.At first step ise
Before reason 206, it is filled with Ar in making ise chamber, by unnecessary for other in ise chamber
Gas is discharged；Further, owing to there is Ar in ise chamber so that first step ise processes 206
I.e. can ionize more sufficient Ar to form Ar plasma beam at the etching initial stage, improve semiconductor production
Efficiency.
Refer to Fig. 7, substrate 200 surface between adjacent side wall 204 is carried out at second step ise
Reason 207, described second step ise processes 207 offer the second radio-frequency power and the second Dc biases,
And described second radio-frequency power is more than the first Dc bias less than the first radio-frequency power, the second Dc bias,
Described second step ise processes 207 and goes the removal of impurity for for the second time.
During second step ise processes 207, in ise chamber, provide working gas, institute
State working gas be Ar, Ar flow be 45sccm to 55sccm；Described second radio-frequency power is used for being formed
Ar plasma beam.
During processing 206 (refer to Fig. 6) due to first step ise, the first Dc bias is relatively low
(for 80V to 100V), under described the first less Dc bias, first step ise processes 206
In Ar plasma beam be difficult to be exactly perpendicularly to the direction on substrate 200 surface and advance so that arrive lining
The plasma limited amount on surface, the end 200, etching removes the ability of substrate 200 surface impurity for the first time
Limited.
To this end, the present embodiment processes after 206 at first step ise, substrate 200 surface is carried out the
Two step ises process 207, and described second step ise processes 207 offer the second Dc biases, and
Second Dc bias is more than the first Dc bias.Described second Dc bias is used for adjusting Ar plasma beam
Direction of advance, owing to the second Dc bias is more than the first Dc bias, therefore with first step ise
Processing 206 to compare, second step ise processes the Ar plasma beam in 207 more perpendicular to substrate 200
Surface, so that more Ar plasma arrives substrate 200 surface, reduces bombardment side wall 204 table
The Ar plasma quantity in face, thus improve second step ise and process 206 etching removal substrates 200
The ability of surface impurity, and reduce the etch rate to side wall 204 surface.
In the present embodiment, described second Dc bias is 110V to 130V.As a specific embodiment,
Described second Dc bias is 110V to 130V.
There is the second bigger Dc bias, therefore with the first step owing to second step ise processes 207
Ise processes 206 and compares, for being provided with the Ar plasma of the Ar plasma of equal number
Shu Eryan, second step ise processes the Ar plasma utilization rate of the Ar plasma beam in 207
Bigger, i.e. the etch rate of substrate 200 surface impurity is compared the first step by second step ise process 207
It is big to the etch rate of substrate 200 surface impurity that ise processes 206.In order to avoid second step sputters
Unnecessary etching is caused in substrate 200 surface by etching processing 207, it is desirable to the energy of Ar plasma beam
Reducing, concrete, the Ar plasma content in Ar plasma beam reduces, the energy of Ar plasma
Amount reduces.
Amid all these factors considering, in the present embodiment, the second radio-frequency power is less than the first radio-frequency power, the
Under two radio-frequency powers, Ar plasma beam energy is less than Ar plasma beam energy under the first radio-frequency power.
Described second radio-frequency power includes the second bias power and the second coil power, the second bias power
For 40W to 60W, the second coil power is 160W to 200W.As a specific embodiment, institute
Stating the second bias power is 50W, and the second coil power is 180W.
After second step ise process 207 completes, the impurity on substrate 200 surface is gone by etching completely
Remove.
Substrate table is removed with processing etching only with the first step ise with relatively low first Dc bias
Comparing of face impurity, by increasing the process of second step ise in the present embodiment, thus decreases first
The time that step ise processes, decrease the time of Ar plasma beam bombardment side wall 204 sidewall surfaces,
The particle avoiding side wall 204 surface drops and forms new impurity on substrate 200 surface, improves substrate 200
The cleanliness factor on surface.And process etching only with the first step ise with relatively low first Dc bias
When removing impurity on substrate surface, in order to ensure that first step ise processes etching completely and removes substrate surface
Impurity, first step ise process etching duration longer, in first step ise processing procedure
Middle Ar plasma beam is not exactly perpendicularly to substrate surface, causes the Ar plasma in Ar plasma beam
Body bombardment side wall sidewall surfaces, the particle on side wall surface departs from side wall and drops at substrate surface, at substrate
Surface forms new impurity.
After second step ise processes 207, it is also possible to include step: make ise chamber successively
It is in Dc bias closed mode (turn-off), trickle state (bleed) and state of bleeding (pump).
Concrete, acting as of described Dc bias closed mode: in this condition, close direct current inclined
Pressure, and the Ar plasma of certain content is still provided in ise chamber, prevent due to Ar etc. from
The problem that daughter suddenly disappears (plasma charge collapse) and causes substrate 200 surface to have impurity.
During the removal of impurity is gone on Ar plasma beam bombardment substrate 200 surface, partial impurities can stick to
On Ar plasma, so that impurity comes off from substrate 200 surface, by constantly to ise chamber
The Ar plasma that interior offer is new, the Ar plasma being stained with impurity is taken away by described Ar plasma
Ise chamber.
(new Ar plasma i.e., is no longer produced if Ar plasma suddenly disappears in ise chamber
Body), then the Ar plasma being stained with impurity is difficult to leave ise chamber, causes and sticks to Ar etc.
Impurity in gas ions drops on substrate 200 surface, and the cleanliness factor affecting substrate 200 surface is inclined at direct current
In pressure closed mode, it is provided that radio-frequency power (including bias power and coil power) bias power is 0.5W
To 5W, coil power be 90W to 110W, Ar flow be 1sccm to 10sccm.
Acting as of described trickle state: owing to Ar plasma beam is with positive electricity, at Ar plasma
Behind bundle bombardment substrate 200 surface, substrate 200 surface also will present positively charged state；Under trickle state,
Dc bias and radio-frequency power, all by closedown, are only passed through Ar in ise chamber, make substrate 200
The positively charged state on surface is transferred to depart from substrate 200 surface on Ar ion, and then makes substrate 200 table
Face presents electric neutrality, it is to avoid due to substrate 200 positive surface charge assemble semiconductor structure is caused unnecessary
Infringement.In trickle state, Ar flow is 15sccm to 25sccm.
Acting as of described state of bleeding: extract remaining Ar in ise chamber out, reduces ise
Chamber inner pressure is strong.
Refer to Fig. 8, at substrate 200 forming metal layer on surface 208 of described grid structure both sides.
The material of described metal level 208 is one or more in Ni, Pt, W, Ti, Ta or Co.Institute
The formation process stating metal level 208 is physical vapour deposition (PVD), metal sputtering or ald.
In the present embodiment, the material of described metal level 208 is Co, uses physical gas-phase deposition to be formed
Described metal level 208.
Refer to Fig. 9, described metal level 208 (refer to Fig. 8) is made annealing treatment, by metal level
208 are converted into metal silicide layer 209.
Described annealing is that a step annealing processes or multiple step anneal processes.Described multiple step anneal processes and includes
First step annealing and second step make annealing treatment.The present embodiment is to carry out multiple step anneal to metal level 208
Process is done exemplary illustrated.
Described first step annealing can be rapid thermal annealing, and annealing temperature is 450 degree to 500 degree,
At N2Carry out under atmosphere.Described first step annealing can also be Millisecond annealing.
Described second step annealing can be rapid thermal annealing, and annealing temperature is 750 degree to 850 degree,
At N2Carry out under atmosphere.Described second step annealing can also be spike annealing.
The material of described metal silicide layer 209 is CoSi2。
After the annealing process, the metal level 208 that removal does not reacts is further comprised the steps of: with substrate 200.
To sum up, the technical scheme of the forming method of the semiconductor structure that the present invention provides has the advantage that
First, substrate is placed in ise chamber, the substrate surface between adjacent side wall is carried out
One step ise processes, and described first step ise processes and goes the removal of impurity, the first step for for the first time
Ise processes provides the first radio-frequency power and the first Dc bias；To the substrate between adjacent side wall
Surface carries out second step ise process, and second step ise processes and goes the removal of impurity for for the second time,
Second step ise processes provides the second radio-frequency power and the second Dc bias, and the second radio-frequency power
Less than the first radio-frequency power, the second Dc bias is more than the first Dc bias.Owing to the second Dc bias is big
In the first Dc bias, therefore in second step ise processing procedure, plasma beam is more vertical
In substrate surface so that the plasma content arriving substrate surface is bigger, thus improves etching and remove lining
The ability of basal surface impurity；Further, due in second step ise processing procedure, plasma beam
More perpendicular to substrate surface, reduce the side wall surface probability by plasma bombardment, thus prevent
The particle on side wall surface is dropped at substrate surface by corrasion.
Secondly, in second step ise processing procedure, the second radio-frequency power is less than the first radio-frequency power,
Reduce second step ise processing procedure plasma bundle energy (plasma content reduce, etc.
Gas ions energy reduces), thus prevent from causing at second step ise owing to the second Dc bias is relatively big
Manage excessive to the etch rate of substrate surface, it is to avoid second step ise processes and substrate is caused over etching.
Again, in first step ise processing procedure, if the first Dc bias is excessive, then Ar to
The speed that substrate surface moves will be very big, easily cause first step ise and process the quarter to substrate surface
Erosion speed is excessive, affects the performance of semiconductor structure, for first step ise in this embodiment of the present invention
Processing the first Dc bias providing less, described second Dc bias is 80V to 100V.
Finally, after carrying out second step ise process, further comprise the steps of: and make ise chamber successively
Room is in Dc bias closed mode and trickle state.Described Dc bias closed mode is still carved to sputtering
There is provided plasma in erosion chamber, prevent from causing owing to plasma suddenly disappears substrate surface to have relatively
Many impurity；Described trickle state provides electroneutral Ar, makes the positively charged of substrate surface transfer to electricity
Neutral Ar, so that substrate surface presents electric neutrality state, it is to avoid owing to substrate surface positive charge is assembled
Semiconductor structure is brought infringement.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (10)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided substrate, described substrate surface is formed with several grid structures, and gate structure sidewall surface
Being formed with side wall, the substrate surface between adjacent side wall has impurity；
Described substrate is placed in ise chamber, the substrate surface between described adjacent side wall is carried out
First step ise processes, and described first step ise processes provides the first radio-frequency power and first
Dc bias, described first step ise processes removes described impurity for for the first time；
Substrate surface between described adjacent side wall is carried out second step ise process, described second step
Ise processes provides the second radio-frequency power and the second Dc bias, and described second radio-frequency power is little
In the first radio-frequency power, the second Dc bias is more than the first Dc bias, at described second step ise
Reason removes described impurity for for the second time.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the described first step sputters
In etching processing and second step ise processing procedure, in ise chamber, provide work gas
Body, described working gas is Ar.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that described first radio frequency merit
Rate and the second radio-frequency power are used for being formed Ar plasma beam, and under the second radio-frequency power Ar etc. from
Daughter beam energy is less than Ar plasma beam energy under the first radio-frequency power.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that described first direct current is inclined
Pressure and the second Dc bias are for adjusting the direction of advance of Ar plasma beam.
5. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that carve in first step sputtering
In erosion processing procedure, Ar flow is 45sccm to 55sccm, in second step ise processing procedure
In, Ar flow is 45sccm to 55sccm.
6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described first direct current is inclined
Pressure is 80V to 100V, and described second Dc bias is 110V to 130V.
7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described first radio frequency merit
Rate includes that the first bias power and first coil power, described second radio-frequency power include the second biasing
Power and the second coil power, and the first bias power is 50W to 70W, first coil power
For 280W to 320W, the second bias power is 40W to 60W, and the second coil power is 160W
To 200W.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that spatter carrying out the first step
Before penetrating etching processing, further comprise the steps of: and be passed through working gas in described ise chamber.
9. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that spatter carrying out second step
After penetrating etching processing, further comprise the steps of: and make ise chamber be in Dc bias closed mode, tiny stream
Stream mode and state of bleeding.
10. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that remove institute in second time
After stating impurity, further comprise the steps of: the substrate surface in grid structure both sides and form metal level；To institute
State metal level to make annealing treatment, metal level is converted into metal silicide layer.
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| CN113257663A (en) * | 2021-07-15 | 2021-08-13 | 广州粤芯半导体技术有限公司 | Method for forming cobalt silicide film layer |
| CN114927413B (en) * | 2022-07-19 | 2022-11-04 | 广州粤芯半导体技术有限公司 | Sputtering method for adhering metal layer and method for manufacturing semiconductor device |
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| US6239006B1 (en) * | 1999-07-09 | 2001-05-29 | Advanced Micro Devices, Inc. | Native oxide removal with fluorinated chemistry before cobalt silicide formation |
| CN1627483A (en) * | 2003-12-12 | 2005-06-15 | 联华电子股份有限公司 | Method for fabricating silicate metal |
| CN1993808A (en) * | 2004-07-29 | 2007-07-04 | 德克萨斯仪器股份有限公司 | Method for manufacturing a semiconductor device having silicided regions |
| CN101553905A (en) * | 2005-09-14 | 2009-10-07 | 飞思卡尔半导体公司 | Semiconductor fabrication process including silicide stringer removal processing |
| CN101689489A (en) * | 2008-05-30 | 2010-03-31 | 佳能安内华股份有限公司 | Silicide forming method and system thereof |
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| US6239006B1 (en) * | 1999-07-09 | 2001-05-29 | Advanced Micro Devices, Inc. | Native oxide removal with fluorinated chemistry before cobalt silicide formation |
| CN1627483A (en) * | 2003-12-12 | 2005-06-15 | 联华电子股份有限公司 | Method for fabricating silicate metal |
| CN1993808A (en) * | 2004-07-29 | 2007-07-04 | 德克萨斯仪器股份有限公司 | Method for manufacturing a semiconductor device having silicided regions |
| CN101553905A (en) * | 2005-09-14 | 2009-10-07 | 飞思卡尔半导体公司 | Semiconductor fabrication process including silicide stringer removal processing |
| CN101689489A (en) * | 2008-05-30 | 2010-03-31 | 佳能安内华股份有限公司 | Silicide forming method and system thereof |
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