CN1041149C - 巳知为好的管芯阵列和它的制造方法 - Google Patents

巳知为好的管芯阵列和它的制造方法 Download PDF

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CN1041149C
CN1041149C CN94103819A CN94103819A CN1041149C CN 1041149 C CN1041149 C CN 1041149C CN 94103819 A CN94103819 A CN 94103819A CN 94103819 A CN94103819 A CN 94103819A CN 1041149 C CN1041149 C CN 1041149C
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chip
test
lead frame
lead
wire
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CN1098226A (zh
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金一雄
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
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    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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    • Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals

Abstract

通过一般的半导体封装技术获得已知为好的管芯阵列，通过对从晶片分离的若干IC芯片同时进行AC和老化测试，使能批量生产已知为好的管芯，其中IC芯片贴在涂有粘结剂的引线框架的管芯焊盘上并连线连接，引线框架与已引线连接的引线电气分离，合成的引线框架被插入测试夹具以进行AC和老化测试，运用具有金刚石和/或类似金刚石刀片的剪切装置切去接合线，附着已进行最后测试无缺陷的若干已知为好的管芯作为阵列。

Description

巳知为好的管芯阵列和它的制造方法
本发明涉及已知为好的管芯(die)阵列(下文简称为“KGD”阵列)和它的制造方法，尤其涉及这样的KGD阵列和它的制造方法，其中使用一般的半导体组装工艺，从晶片分隔的若干集成电路芯片(下文简称为“IC芯片”)要同时受到交流电流(AC)或老化测试，因而能批量生产无缺陷的KGD阵列。
众所周知为了找出不合格IC芯片，在制造半导体器件时IC芯片实质上要经受AC测试或老化测试。然而，在从晶片分隔的裸露的芯片情况下，测试信号发生电路不能与电信号线相连，以致不能进行AC测试或老化测试。因此，如图1所示，一般AC测试或老化测试在用EMC塑封IC芯片的封装状态下进行的。
参阅图1，与芯片座(未图示)连接的外引线12沿封装10的侧壁伸出。
用于固定封装10的测试插座有若干个孔14，用以接纳外引线12，而硬引线14从孔14的下部向外伸出。
具有伸出的外引线12的封装10固定在测试插座15的孔14中，而测试插座15固定在未图示的老化板上。这样当将封装10固定在测试插座15上时就可进行AC测试和老化测试。
在AC测试和老化测试时，在升高的温度下或比正常运行更高的电压下给IC芯片加以测试信号。那末在加以测试信号状态下检查在任何芯片有否出现缺陷。例如，在DRAM中可以检查到不合格的短路，不合格的存储单元和不合格的连接线。
因此，当在正常状态使用时会引起一些问题的任何IC芯片在老化测试时必定会出现缺陷(例如由于栅极氧化物缺陷引起的绝缘层击穿)。因此，在进行老化测试时可以检出有这种缺陷的IC芯片，将该芯片作为次品处理。如上所述，不合格芯片在进入市场前被检出，以保证产品可靠性。
然而，因为使用测试插座的老化测试是以封装的半导体芯片执行的，IC芯片一旦被判为不合格就不能再使用。
为此，不使用单芯片封装，近来已提出多芯片技术，它使用倒装芯片，用以将若干裸露的芯片热固定在瓷板上。已提出运用各种集成方法的多芯片技术，从而能大规模集成并达到高速，高容量和小尺寸。其中一个代表性方法是运用多芯片组件的集成方法。
多芯片组件以这样的方式来获得非常大规模集成，在其底部具有密集排列的互连线的多层陶瓷或塑料板上具有并与之公共连接的若干IC芯片。目前，多芯片组件已由例如IMB，DEC和Hitachi公司成功地应用于超级计算机等。
尽管这优点，多芯片组件由于下列原因在技术和经济上仍受限制。
即与单芯片封装技术比较，包括若干IC芯片的多芯片组件已增加集成规模，但生产率明显降低，而又大大增加制造成本。
由于可以适用于所有封装技术的上述原因，多芯片组件难以占据充分的市场。多芯片组件的最困难问题是要充分地获得KGD(即未被封装的但在完成与常规封装技术相同程度的测试后证明为可靠的IC芯片)，这与生产率直接相关。
为了充分地获得KGD而提出了本发明。下文中已经历所有测试而没有任何缺陷的裸露的IC芯片将称为KGD。裸露的芯片表示作为象倒装芯片(flip chip)，引线芯片(wire chip)等的单个芯片从晶片上分离后未曾封装的普通IC芯片。KGD的较详细概念在1992年的微电子和计算机技术协会的《潜在的科研项目报告》一文中介绍。
尽管应用于多芯片组件的KGD的重要性正被增大，低成本KGD的批量生产仍非常困难。
更详细地说，从晶片分离的单个裸露芯片没有外引线，阻碍能适用于芯片测试的测试插座的使用。因此，在裸露芯片情况下在IC芯片安装在电路板上之前不能进行AC测试和老化测试。
作为解决这问题的技术，已提出容许在裸露芯片状态进行AC测试和老化测试的倒装芯片测试插座转接器，它为芯片的每个电极焊盘提供焊接凸缘(solderbump)。这技术已在例如美国专利No.5006792的专利中公开，并在图2和3中图示说明。
图2是表示具有焊接凸缘的常规倒装芯片的透视图。图3是表示图2的倒装芯片安装在测试插座转接器的状态的截面图。
参阅图2，IC芯片22包括其上具有若干焊接凸缘24的连接焊盘。结合图3说明测试插座转接器，IC芯片22插入它自己的测试插座转接器，然后进行测试。
参阅图3，测试插座转接器20包括衬底28，它有悬壁杆26相对应地与插入的IC芯片22的焊接凸缘24相连接，衬底被外壳20包围。标号23表示与悬臂杆26相连的引线；27是突出在外壳20外面的引线；和25是导向杆，用于当插入IC芯片22时稳定地支撑IC芯片22。
使用依照上述结构的测试插座转接器的IC芯片测试方法容许裸露的芯片在末被封装之前就进行测试。
在常规技术中单个IC芯片22从晶片上分离，芯片测试和老化一定要在裸露芯片状态下进行，而焊接凸缘24是在IC芯片22的每个电极焊盘上形成的金属突出物。但是在单个IC芯片的电极焊盘上形成焊接凸缘时由于电极焊盘之间间距极小，要达到较高的存储密度必须高精度的昂贵设备。
另外，在测度时芯片应该个别地处理，使得芯片处理困难。
依照常规技术制造KGD的问题可以归结如下：
(1)因为普通IC芯片无法进行AC测试和老化测试，形成焊接凸缘和使用它自己的插座，因此产品只能小批量地提供。
(2)IC芯片要个别地处理，使芯片处理困难。
(3)与封装的IC芯片比较，KGD相当昂贵。
(4)难以形成测试夹具。
(5)没有标准化的IC芯片。
设计本发明是为了解决上述问题。因此，本发明的目的是提供能使从晶片分离的普通IC芯片不形成焊接凸缘就可进行AC和老化测试的KGD阵列和它的制造方法。
本发明的另一目的是提供能同时对若干IC芯片进行AC和老化测试的KGD阵列和它的制造方法。
本发明的另一目的是提供能使用典型的IC组装设备进行AC和老化测试的KGD阵列和它的制造方法。
为了达到本发明的上述目的，已知为好的管芯阵列包括引线框架，引线框架有若干规则排列的由拉杆支持的管芯座，在引线框架的各个管芯座上涂以粘结剂，还包括若干已知为好的无缺陷的管芯，它作为单个管芯粘结在涂以粘结剂的每个管芯焊盘上和已经过最终测试。
为了达到本发明的另一目的，还提供制造已知为好的管芯阵列的方法，它包括下列步骤：
制备具有若干引线和若干规则排列的由拉杆支持的管芯焊盘的引线框架；
贴上胶带，用以将管芯焊盘固定在引线框架的引线上；
将从晶片分离的具有若干电极焊盘的IC芯片贴在引线框架的涂有粘结剂的各个管芯焊盘上，固定管芯，
连接IC芯片的电极焊盘和与电极片对应的各引线端；
进行修整，用以将引线框架与焊线引线电气分离；
通过将形成的引线框架插入测试夹具，进行AC和老化测试；
在完成AC和老化测试后检查不合格IC芯片；和
使用剪切装置，切断连接引线球的上部。
通过结合附图详细说明其推荐实施例，将会更清楚本发明的以上目的和其他优点，附图如下：
图1是表示依照常规技术的测试插座的透视图；
图2是表示依照常规技术的有连接块的倒装芯片的透视图；
图3是表示图2的倒装芯片固定在测试插座转接器的状态的截面图；
图4是表示在制造依照本发明的KGD阵列中所使用的引线框架的平面图；
图5A和5B表示依据本发明制造KGD阵列的过程；
图6是表示依照本发明的KGD了阵列中单个KGD的透视图；和
图7表示在依照本发明制造KGD阵列中使用的剪切装置状态。
图4表示依照本发明制造KGD阵列中所使用的引线框架，其中引线框架通过一般的设计方法形成。
参阅图4，引线框架30具有尺寸相同的规则排列的管芯焊盘32，在各个管芯焊盘32的两侧上有若干引线34。
因为引线框架不是用于一般的IC芯片封装，不形成密封条dam bar)。
标号36是开口，用于防止引线34在修整工艺时变形，和38是用以支持管芯焊盘32的拉杆。
图6是表示依照本发明的KGD阵列中单个KGD的透视图。在将若干KGD放入图4的引线引线框架30中，以供连接IC芯片31的电极焊盘和引线，在进行整个AC和老化测试以后就得到KGD阵列。为方便起见，KGD阵列的结构将在以后介绍，先在下文介绍它的制造方法。
图5A和5B表示依照本发明的制造KGD阵列的过程。
参阅图5A，如图4所示的由一般引线框架设计方法构成的引线框架30已制好。贴上胶带39，用以将引线34固定在引线框架30上。此处具有极强的粘结特性的聚酰亚胺类物质用作为胶带39。
参阅图5B，从晶片分离的具有若干电极焊盘的IC芯片31被固定在引线框架30的各个管芯焊盘32上。为了使管芯固定，贴住管芯的粘结剂采用例如焊料的导电材料，热圆树脂或热塑树脂等(按其用途而分)。
当使用作为焊料的导电材料时，在管芯焊盘32上加入适当量的焊料，将IC芯片热压。使用导电材料作为焊料的原因是假如其后部用作为地部，容许电流可流过引线框架，或容许管芯焊盘贴在分离的KGD的下表面，以供用作散热器。
同时，被聚酰亚胺固化的环氧树脂和聚酰胺酸可以用作热凝树脂。
当要求KGD不是被贴住管芯焊盘的底表面时可以使用包括聚芳基化聚醚聚砜树脂，聚丙烯酸树脂的热塑树脂作为粘结剂。此时，由于在预定温度下的回流的流动，KGD必定很容易地从管芯焊盘上脱开。
在完成管芯的粘贴以后，使用金(Au)，通过热压方法将IC芯片31的各电极焊盘与对电极焊盘分别对应的引线34端部连线连接。对于接合线37，可以通过超声波方法与普通IC芯片31的铝电极焊盘相连接的例如铝等任何材料均可被使用。
在引线连接以后进行修整工艺，使引线框架30与引线连接的引线34电气分离。开口36使修整工艺变得方便。
在使引线绝缘的修整工艺以后，进行AC和老化测试。至今所述的一般IC组装工艺，例如引线框架制备，引线连接和将与IC芯片的电极焊盘电连接的引线分离，只是为进行测试和老化所做的一系列工作。
这里各个芯片不是分别地被测试，而是装有与引线34相连接的若干IC芯片31阵列的整个引线框架30同时被测试。
可以设计适用于同时测试整个引线框架30的测试夹具。
每个IC芯片的电极焊盘通过接合线37与引线34相连，而引线34使用作为测试电极针脚，因此测试夹具的设计要比通过形成细小焊接凸缘的常规测试插座转接器的设计更容易。
使用测试夹具，在一个引线框架30上大约16个IC芯片31同时被测试。通过连续的AC和老化测试，可以检出不合格的IC芯片，并作为次品处理。
在KGD阵列制造方法的最后一步，也可看为本新方法中最重要的一步，是在完成AC测试和老化测试以后产生KGD，即将IC芯片31的各电极焊盘和与电极焊盘对应的引线34电连接的接合线37切去。
接合线37在AC测试和老化测试时提供了测试电极针脚，它要被切去是因为对于依照本发明的KGD阵列它不是直接需要的。
对于连接连线37的切除工艺，使用图7所示的剪切装置40。剪切装置40形状象凿刀，在其端部有锋利的刀刃，刀片主要使用金刚石。其他材料也可以用作刀片，例如具有金铡石涂层的碳化钨，磨锐的钢片等。切除装置40固定在直臂上，由公差约为1μm的精密步进电机上下移动。在前后和左右方向的移动也可以由高精度的X-Y横向移动台控制。
图7表示在依照本发明制造KGD阵列中使用的切除装置的使用状态。此处重要的特点是在所有必需的测试和老化以后用金钢石刀片切去连线。
参阅图7，移动切除装置40靠近贴在引线框架30上并与它引线连接的IC芯片31的中央面。通过X-Y横向移动台调节左右方向移动，切去接合线37的引线球37a的上部。为了精密控制引线球尺寸的目的，应该运用真空吸盘将引线框架固定在X-Y横向移动台上。
在切去接合线37以后在Ic芯片31的电极座上只留下切剩的引线球33。切剩的引线球33可以作为焊接凸缘块使用。此时通过调节切除装置40的下降高度很容易地解决焊接的形成和高度。
可以在切剩的引线球33的上表面上重复进行引线连接，从而能按要求在连接焊盘上实现多次焊接凸缘。为了确保引线连接芯片的可靠性，将连线切去并再连接来进行拉力试验，其结果为与第一次连接一样良好的数据。而且，本申请人进行的实验在5次重复测试中没有任何缺陷提供相同的数据。
在接合线的切除工艺后所形成的结构如图6所示，其中接合线，胶带皆已除去，已经AC测试和老化测试的无缺陷的IC芯片31贴在涂有粘结剂35的引线框架30上。
在依照本发明最终获得的KGD阵列中，图6所示的单个KGD装在作为若干阵列的引线框架30上，在现行使用的送往市场的引线框架箱上可以装载几层这些引线框架30。而且，已经测试的芯片被包装在便宜的易处置的箱中，送往最终用户。送往买方的若干IC芯片在切去拉杆后可以用作单个KGD，管芯焊盘贴在其底表面上。如上所述管芯焊盘可以当作散热器使用。
如上所说明的，在本发明中IC芯片不是个别地处理，因此在处理基芯片时易于发生的缺陷可以减至最小。
依照本发明的KGD阵列和它的制造方法的效果可以归结如下：
(1)可以使用普通IC芯片大量生产已经过AC和老化测试的没有缺陷的KGD。
(2)在芯片送往买方后切去拉杆，使得在芯片级处理芯片来得简便。
(3)因为可未经变化地利用典型IC封装设备，不需要附加设备。
(4)该测试夹具容易制造。
(6)按照最终用户要求，IC芯片容易分类为引线(焊接)芯片，倒装(焊接)芯片和凸缘(焊接)芯片。
(7)KGD的成本可以显著地降低，从而使多芯片组件或ASIC组件的适用领域从现在应用的超级计算机扩展到个人计算机。
因此，在依照本发明的KGD阵列和制造方法中，至少一个KGD装在作为若干阵列的引线框架上，从而获得许多KGD同时测试。而且，通过切去拉杆，若干IC芯片可以被用作为单个KGD，管芯焊盘贴在其底表面上，可以在本发明的形式和细节上作出各种变化，而不偏离由所附的权利要求所规定的本发明的精神和范围。

Claims (6)

1.已知为好的管芯阵列由以下组成：
具有若干个规则排列的由拉杆支持的管芯焊盘的引线框架；
粘结剂涂在所述引线框架的各个管芯焊盘上；
若干已知为好的无缺陷的管芯，各个管芯贴在涂有所述粘结剂的每个管芯焊盘上，并已经过最终测试；
其特征在于：所述若干IC芯片在每个各自电极焊盘上有焊接凸缘。
2.制造已知为好的管芯阵列的方法由以下步骤组成：
制备具有若干引线和若干规则排列的由拉杆支持的管芯座的引线框架；
贴上胶带，用以将所述管芯焊盘固定在所述引线框架的所述引线上；
将从晶片分离的具有若干电极焊盘的IC芯片贴在所述引线框架涂有粘结剂的各个管芯焊盘上，固定管芯；
将所述IC芯片的所述电极焊盘连接到与所述电极焊盘对应的各引线端；
进行修整，用以将所述引线框架与所述焊线引线电气分离；
通过将所形成的引线框架插入测试线，进行AC测试和老化测试；
在完成所述AC测试和老化测试后检出不合格IC芯片；和
使用剪切装置切去焊线球的上部。
3.依照权利要求2的已知为好的管芯阵列的制造方法，其特征在于：具有极强粘结特性的聚酰亚胺类物质被用作为所述胶带。
4.依照权利要求2的已知为好的管芯阵列的制造方法，其特征在于：在切去焊线的所述步骤，使用金刚石或类似金刚石刀片，所述剪切装置的高度加以调整，以控制切去和余留的引线球的尺寸，从而形成焊接凸缘。
5.依照权利要求2的已知为好的管芯阵列的制造方法，其特征在于：所述粘结剂是由从为焊料的导电材料，热凝树脂和热塑树脂所组成的这组材料中按其用途目的选择的材料构成的。
6.依照权利要求2的已知为好的管芯阵列的制造方法，其特征在于：通过切去所述拉杆，所述若干IC芯片用作各个已知为好的管芯，所述管芯焊盘贴在其底表面上。
CN94103819A 1993-04-07 1994-04-07 巳知为好的管芯阵列和它的制造方法 Expired - Fee Related CN1041149C (zh)

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