CN104104368A - Four-channel dynamic amplitude-modulated signal generator - Google Patents

Abstract

The invention provides a four-channel dynamic amplitude-modulated signal generator, wherein the traditional 32-bit MCU is combined with an FPGA, the traditional 32-bit MCU is simulated to a dual-channel DAC, and the MCU is used as the peripheral of the FPGA instead of usual main equipment, so as to realize the four-channel dynamic amplitude-modulated signal generator. After a data interface between the FPGA and a DAC module (which actually is simulated by the MCU) is configured with a signal time sequence, the FPGA can realize the purpose only by conveying DDS data into the 'DAC' module according to time sequence requirements. The four-channel dynamic amplitude-modulated signal generator provided by the invention breaks through the top-to-bottom design method of the traditional signal generator, and originally simulates the traditional 32-bit MCU to the peripheral of the DAC; in the other hand, hardware characteristics are adequately utilized, and software intervention is furthest reduced, thus the running efficiency is great.

Description

A kind of four-way dynamic amplitude modulation signal generator

Technical field

The present invention relates to signal source hormone field, in particular to a kind of four-way dynamic amplitude modulation signal generator.

Background technology

After electric current of intermediate frequency is modulated by low-frequency current, its amplitude and frequency are along with the amplitude of low-frequency current and the variation of frequency and the electric current changing is called modulating frequency current.The method of applying this electric current treatment disease is called modulated medium frequency elec trotherapy.The features such as this therapy has fast, the no pain of producing effects, side effect is little, curative effect is lasting, are extensively adopted clinically.

In medical electrotherapy equipment, most crucial part is the generation of amplitude modulation(PAM) waveform (AM), by different modulation waveforms, the variation of carrier wave, after signal is amplified, and outputs to human body.

The angle occurring from signal, in the definition of medical electric current, the frequency range of the medical electric current of intermediate frequency is 1KHz～5KHz, not high.But in conjunction with the consideration of feature and the equipment cost of medicine equipment itself, rarely have and can accomplish unified, low-cost medical signal generator of intermediate frequency, particularly for some special applications, as three-dimensional intermediate frequency interference electric therapeutic equipment, also need to accomplish the Phase synchronization of signal, modulation depth adjusting etc.The application of this complexity, even almost cannot realize in the system of 8 singlechip chips 32 of traditional uses.

Summary of the invention

A first aspect of the present invention discloses a kind of four-way dynamic amplitude modulation signal generator, by traditional 32 MCU and FPGA combination, adopt 32 traditional MCU to be modeled to binary channels DAC, the peripheral hardware using MCU as FPGA, instead of common main equipment, realize four-way dynamic amplitude modulation signal generator.

In the disclosure, described four-way dynamic amplitude modulation signal generator, comprise a MCU, the 2nd MCU and a fpga chip, between a MCU and fpga chip and between the 2nd MCU and fpga chip, disposing respectively data/address bus, common clock bus and low speed communication bus;

Configuration-direct in described fpga chip, produce unified reference clock signal also by described common clock bus synchronous to the MCU, the 2nd MCU for the oscillator signal providing according to outside, and calculate the data transaction of 4 DAC passages for timesharing, this data transaction produces AM synthetic waveform based on DDS (Direct Digital frequency synthesis) algorithm, and transfers to a MCU and the 2nd MCU by described data/address bus timesharing under the distribution of sequential;

A described MCU, the 2nd MCU are used for the peripheral hardware as described fpga chip, for:

By described common clock bus, the one MCU, the 2nd MCU and described fpga chip are remained under same reference clock signal;

Be connected to receive described AM synthetic waveform by data/address bus and described fpga chip; And

Provide respectively the output of two output amplitude-modulated signals according to the AM synthetic waveform of described fpga chip transmission.

In further implementing, a described MCU, the 2nd MCU all adopt the one in STM32F10x/STM32F20x/STM32F40x family chip, and a MCU is identical with the 2nd MCU.

In further implementing, a described MCU is configured to main logic control chip, passes through spi bus communication with described fpga chip.

In further implementing, the reference clock signal of the fixed frequency that described fpga chip produces, is applied to common clock bus;

The timer of a described MCU, the 2nd MCU all works in external timing signal pattern, and a MCU, the 2nd MCU are respectively to this signals collecting counting;

A described MCU, the 2nd MCU, for signal-count result, within a sequential cycle, complete task separately according to different time slots;

In the processing time slot of the 2nd MCU, the waveform that calculates respectively 4 DAC passages adopts data, and transfers to described data/address bus;

In the processing time slot of a MCU, gather respectively the data on described data/address bus and complete a DAC conversion.

From the above technical solution of the present invention shows that, beneficial effect of the present invention is to propose a kind of four-way dynamic amplitude modulation signal generator of simplification, four-way signal can synchronous, asynchronous two kinds of modes be exported, and allow frequency range in exportable AM random waveform; On the one hand, break through the traditional signal generator top-down method for designing, Promethean 32 MCU of tradition are modeled to DAC peripheral hardware; On the other hand, make full use of ardware feature, reduce to greatest extent software intervention, operational efficiency is splendid.

Brief description of the drawings

Fig. 1 is the theory diagram of the four-way dynamic amplitude modulation signal generator of an embodiment of the present invention.

Embodiment

In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and coordinate appended graphic being described as follows.

As shown in Figure 1, according to preferred embodiment of the present invention, a kind of four-way dynamic amplitude modulation signal generator, by traditional 32 MCU and FPGA combination, adopt 32 traditional MCU to be modeled to binary channels DAC, peripheral hardware using MCU as FPGA, instead of common main equipment, realize four-way dynamic amplitude modulation signal generator.

In the present embodiment, as shown in Figure 1, four-way dynamic amplitude modulation signal generator, comprise a MCU1a, the 2nd MCU1b and a fpga chip 2, between a MCU and fpga chip and between the 2nd MCU and fpga chip, disposing respectively data/address bus 3, common clock bus 4 and low speed communication bus 5.

Wherein, low speed communication bus 5 is the low speed PORT COM between MCU<->FPGA, for preparing the transmission of data.

In the present embodiment, clock signal is produced by fpga chip 2, and is synchronized to MCU (1a and 1b) by common clock bus 4, for coordinating the control sequential of MCU (1a and 1b) and fpga chip.

Aforementioned fpga chip 2, also calculates the translation data of each DAC passage for timesharing, under the distribution of sequential, the data/address bus of MCU<->FPGA is sent in timesharing, thus two MCU (1a and 1b) that transfer to.

The interior configuration-direct of this fpga chip 2, produce unified reference clock signal also by described common clock bus synchronous to the MCU, the 2nd MCU for the oscillator signal providing according to outside, and calculate the data transaction of 4 DAC passages for timesharing, this data transaction produces AM synthetic waveform based on DDS (Direct Digital frequency synthesis) algorithm, and transfers to a MCU and the 2nd MCU by described data/address bus timesharing under the distribution of sequential;

A described MCU, the 2nd MCU are used for the peripheral hardware as described fpga chip, for:

By described common clock bus, the one MCU, the 2nd MCU and described fpga chip are remained under same reference clock signal;

Be connected to receive described AM synthetic waveform by data/address bus and described fpga chip; And

Provide respectively the output of two output amplitude-modulated signals according to the AM synthetic waveform of described fpga chip transmission.

As preferably, a described MCU1a can be configured to main logic control chip, with described fpga chip 2 by spi bus communication.For example in the present embodiment, a MCU adopts STM32F1031RC chip, and the 2nd MCU also adopts STM32F103RC.

In the enforcement of alternative, an aforementioned MCU1a, the 2nd MCU1b all adopt the one in STM32F10x/STM32F20x/STM32F40x family chip, and a MCU is identical with the 2nd MCU.

As previously mentioned, in the present embodiment, complete the synthetic of AM waveform by fpga chip 2, by means of DDS (Direct Digital frequency synthesis) algorithm, high frequency synthetic waveform can be produced, due to the AM synthesizer that adopts high speed fpga chip to realize, the synthetic of any AM waveform can be met.

Shown in figure 1, the reference clock signal of the fixed frequency that described fpga chip 2 produces, is applied to common clock bus 4;

The timer (TIM5CH1 in figure) of a described MCU1a, the 2nd MCU1b all works in external timing signal pattern, and a MCU, the 2nd MCU are respectively to this signals collecting counting;

A described MCU, the 2nd MCU, for signal-count result, within a sequential cycle, complete task separately according to different time slots;

In the processing time slot of the 2nd MCU, the waveform that calculates respectively 4 DAC passages adopts data, and transfers to described data/address bus;

In the processing time slot of a MCU, gather respectively the data on described data/address bus and complete a DAC conversion.

In the present embodiment, the processing logic order of the one MCU is that < timer gathers reference clock >, < time slot judges that >, < image data >, <DAC change >, this process has hardware to complete completely, without any need for the intervention of software, therefore embody high efficiency and the uniqueness (being the specificity of MCU model) of whole four-way dynamic amplitude modulation signal generator.

Two MCU (1a, 1b) and fpga chip 2 (4.19430MHz) under identical clock bus, simultaneously to driving clock count, (4.19430MHz), to ensure that DAC synchronously exports.

In the present embodiment, described outside oscillator signal is the active crystal oscillator of a HS-A370-67.108864MHz, offers fpga chip 2, distributes corresponding clock by it:

1) after 8 frequency divisions, obtain 8.388608MHz and offer each MCU.

2) after 16 frequency divisions, obtain 4.194304MHz and export to as CPLD/FPGA the clock signal of the counter of each MCU.

This signal again 16 frequency divisions obtains the DDS clock of 262.144KHz.This signal also can be by 1) two divided-frequency again.

3) and the work such as the internal memory operation of CPLD/FPGA work under 67.108864MHz speed completely.

Two MCU (1a, 1b) determine current behavior separately with fpga chip 2 according to count value, as shown in the table:

Shown in figure 1, TI1S:0, selects the input of TIM5_CH1 as TI1, MMS[2:0], 010, selection TIM5 more new events inputs (TROG) as triggering.CCDS:1, in the time there is more new events, sends the DMA request of CCx.

In the DAC of STM32 design, DMA2_CH3 and DMA2_CH4 are that hardware is distributed to DMA " exclusive " passage, just DAC module has been opened DMA function, no matter which kind of mode triggering DAC by changes, hardware will use DMA passage to transmit data for DAC automatically, so in the time that TIM5 overflows, formulate him and produce a TRGO signal, DMA1,2 will complete DMA transfer of data and two work of DAC conversion automatically.Therefore 14,15 two behaviors in former sequential, can omit.

Although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on claims person of defining.

Claims (4)

1. a four-way dynamic amplitude modulation signal generator, it is characterized in that, comprise: a MCU, the 2nd MCU and a fpga chip, disposing respectively data/address bus, common clock bus and low speed communication bus between a MCU and fpga chip and between the 2nd MCU and fpga chip;

Configuration-direct in described fpga chip, produce unified reference clock signal also by described common clock bus synchronous to the MCU, the 2nd MCU for the oscillator signal providing according to outside, and calculate the data transaction of 4 DAC passages for timesharing, this data transaction is based on the frequency synthesis of DDS(Direct Digital) algorithm and produce AM synthetic waveform, and transfer to a MCU and the 2nd MCU by described data/address bus timesharing under the distribution of sequential;

A described MCU, the 2nd MCU are used for the peripheral hardware as described fpga chip, for:

By described common clock bus, the one MCU, the 2nd MCU and described fpga chip are remained under same reference clock signal;

Be connected to receive described AM synthetic waveform by data/address bus and described fpga chip; And

Provide respectively the output of two output amplitude-modulated signals according to the AM synthetic waveform of described fpga chip transmission.

2. four-way dynamic amplitude modulation signal generator according to claim 1, is characterized in that, a described MCU, the 2nd MCU all adopt the one in STM32F10x/STM32F20x/STM32F40x family chip, and a MCU is identical with the 2nd MCU.

3. four-way dynamic amplitude modulation signal generator according to claim 1, is characterized in that, a described MCU is configured to main logic control chip, passes through spi bus communication with described fpga chip.

4. four-way dynamic amplitude modulation signal generator according to claim 1, is characterized in that, the reference clock signal of the fixed frequency that described fpga chip produces, is applied to common clock bus;

The timer of a described MCU, the 2nd MCU all works in external timing signal pattern, and a MCU, the 2nd MCU are respectively to this signals collecting counting;

A described MCU, the 2nd MCU, for signal-count result, within a sequential cycle, complete task separately according to different time slots;

In the processing time slot of the 2nd MCU, the waveform that calculates respectively 4 DAC passages adopts data, and transfers to described data/address bus;

In the processing time slot of a MCU, gather respectively the data on described data/address bus and complete a DAC conversion.