CN103972155A - Method for itching through hole in silicon substrate - Google Patents

Method for itching through hole in silicon substrate Download PDF

Info

Publication number
CN103972155A
CN103972155A CN201310046733.4A CN201310046733A CN103972155A CN 103972155 A CN103972155 A CN 103972155A CN 201310046733 A CN201310046733 A CN 201310046733A CN 103972155 A CN103972155 A CN 103972155A
Authority
CN
China
Prior art keywords
gas
etching
photoresist
plasma etching
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310046733.4A
Other languages
Chinese (zh)
Inventor
许颂临
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Fabrication Equipment Inc Shanghai
Advanced Micro Fabrication Equipment Inc
Original Assignee
Advanced Micro Fabrication Equipment Inc Shanghai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Fabrication Equipment Inc Shanghai filed Critical Advanced Micro Fabrication Equipment Inc Shanghai
Priority to CN201310046733.4A priority Critical patent/CN103972155A/en
Priority to TW103103185A priority patent/TW201442110A/en
Publication of CN103972155A publication Critical patent/CN103972155A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Abstract

The invention discloses a method for itching a through hole in a silicon substrate. The method has the advantages that a hard mask in the prior art is replaced by photoresist to serve as a mask, key size change may be caused by image transfer among multiple mask layers is avoided, the itching process is simplified, and cost is saved; in order to guarantee that the silicon substrate using the photoresist as the mask has sufficient selection ratio, oxygen which easily reacts with the photoresist is replaced by CO and/or CO2 to provide oxygen free radical for the reaction of a deposition protecting layer; O2 in a plasma itching chamber is kept below 5% to increase the selection ratio of the photoresist mask layer and the silicon substrate, and particles such as C free radical dissociated from CO and/or CO2 form a protecting layer on the surface of the photoresist to prevent the oxygen free radical from reacting with the photoresist.

Description

A kind of method at silicon base etching through hole
Technical field
The present invention relates to semiconductor chip processing technology field, relate in particular to a kind of technical field of etch silicon base substrate.
Background technology
In technical field of manufacturing semiconductors, often need on silicon substrate or other silicon materials, patterned etch form hole, in prior art, conventionally be all the RIE lithographic technique that adopts dry method, by the γ-ray emission F plasma (Plasma) containing F element, carry out etch silicon material, for example, at MEMS((Micro-Electro-Mechanical Systems, MEMS (micro electro mechanical system)) and the field such as 3D encapsulation technology, conventionally need to carry out body silicon etching and form the dark silicon through hole (Through-Silicon-Via that the degree of depth reaches hundreds of micron, TSV), the etching of dark silicon through hole adopts and can produce the etching gas of fluorine ion and can provide the deposition gases cooperation of sidewall protection to carry out.
Before semiconductor chip etching, first to apply photoresist at substrate surface; utilize the accurate exposure of photoresist required etching figure to be transferred in the etching substrate of semiconductor chip; photoresist can be used as mask and covers region in addition, etched area, and the semiconductor base beyond protection etched area is not etched.To take substrate that silicon materials are substrate while carrying out deep hole etching, conventionally need to adopt can produce the gas of fluorine ion as the etching gas of silicon base, because chemical reaction does not have directivity, in the process of deep hole etching, sidewall pattern is difficult to guarantee smooth.In order to meet the requirement of deep hole etching, conventionally need to be at side wall deposition protective layer, to prevent that chemical reaction from carrying out in all directions of through-hole side wall.
In order to form deposition protective layer at silicon deep hole sidewall; in prior art, the normal halide of silicon that adopts is deposited on silicon deep hole sidewall and bottom as SiF4 or SiCl4 etc. reacts generation silica with O2; as passivation layer; due to the bombardment intensity of ion pair sidewall a little less than; the etch rate of F ion pair silicon deep hole sidewall passivation layer is very slow, therefore, and in whole etching process; lateral etching speed is slow, has good anisotropic feature.Because oxygen very easily reacts with the photoresist as mask layer, can reduce the selection ratio of photoresist and target etch layer, can not complete smoothly etching technics, for this reason, be everlasting the hard mask of one deck is set between photoresist and silicon base, as silicon oxide layer, first figure to be etched is transferred on hard mask, then the mask layer using described hard mask as etch silicon substrate.The preparation of hard mask needs comparatively complicated step, first on silicon base surface, by methods such as chemical vapour deposition (CVD)s, prepares certain thickness hard mask, then prepares photoresist coating above hard mask; On photoresist surface, accurately exposure obtains after the figure of wanted etching, described figure first need to be transferred on described hard mask and photoresist is removed, then the described hard mask of usining carries out etching as mask to silicon base, also needs described hard mask to remove after etching completes.Above-mentioned complex process and costly, is unfavorable for cost control, and the figure between a plurality of mask layer shifts the variation may cause critical size, affects the accuracy of substrate etching.
Summary of the invention
In order to address the above problem, the invention provides a kind of method at silicon base etching through hole, described silicon base surface-coated has photoresist mask layer, described lithographic method carries out plasma etching is indoor, described method comprises the following steps: that the first gas that provides fluorine-containing is indoor to plasma etching, and described the first gas is for carrying out etching to silicon base; Provide siliceous the second gas indoor to plasma etching, the second described gas also comprises hydrocarbon, O in described the second gas 2content is less than 5%.
Further, described hydrocarbon is CO, CO 2in one or both mist, described CO is or/and CO 2flow is 50sccm-300sccm.
Further, described the first fluorine-containing gas comprises SF 6or NF 3in one or both mist, described SF 6or/and NF 3gas flow scope be 100sccm-500sccm.
Further, described the second gas comprises SiF 4, SiCl 4in one or both mist, described SiF 4and/or SiCl 4gas flow scope be 50sccm-300sccm.
Further, described in described the second gas, the ratio of hydrocarbon gas and the ratio of described silicon-containing gas are 4:1-1:1.
Further, described the second gas comprises NO, NO 2in one or both mist.
Further, described the first gas also comprises Cl 2, one or both the mist in HBr, described Cl 2and/or the gas flow scope of HBr is 50sccm-200sccm.
Further, described plasma etching chamber is inductively coupled plasma etching chamber or electron cyclotron resonace etching chamber.
Further, the power bracket of the high frequency power source that described plasma etching is indoor is 500w-1000w, and the power bracket in low frequency power source is 50w-100w, and the indoor pressure limit of described plasma etching is 20mT-100mT.
Further, in described the first gas and the second gas injected plasma simultaneously etching chamber.
Further, described the first gas and the second gas replace in injected plasma etching chamber.
The invention has the advantages that: the present invention utilizes photoresist to substitute hard mask of the prior art as mask, avoided the figure between a plurality of mask layers to shift the variation that may cause critical size, simplified etching technics, provide cost savings, in order to guarantee, adopt photoresist to have enough large selection ratio as mask and silicon base, the present invention adopts CO and/or CO simultaneously 2replace O easy and that photoresist reacts 2for depositing the reaction of protective layer, provide oxygen radical.Maintain the indoor O of plasma etching 2lower than 5%, to have improved the selection ratio of photoresist mask layer and silicon base, while CO and/or CO 2the particles such as the C free radical dissociateing form layer protective layer on photoresist surface, prevent that oxygen radical and photoresist from reacting.
Accompanying drawing explanation
Fig. 1 illustrates ICP reaction chamber structure schematic diagram of the present invention;
Fig. 2 illustrates a kind of structural representation of silicon base substrate.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The invention provides a kind of method at silicon base etching through hole, method of the present invention is carried out plasma etch chamber is indoor, especially, because the speed that this etching reaction needs is very fast, need to be at the plasma etching of high concentration indoor carrying out, as carried out in inductively coupled plasma reative cell (ICP) or electron cyclotron resonace reative cell (ECR).Fig. 1 illustrates the structural representation of a kind of inductively coupled plasma reative cell described in the present embodiment.ICP reaction chamber 100 comprises and is substantially metal sidewall cylindraceous 105 and insulation top board 107, and formation can be evacuated the airtight space that device 125 vacuumizes.Pedestal 110 supports chuck 115, and described chuck 115 supports pending substrate 120.Radio-frequency power from radio frequency power source 145 is applied to the antenna 140 that is coiled type.Processing gas from source of the gas 150 is supplied in reaction chamber, to light and to maintain plasma, and thus substrate 120 is processed.In standard inductor coupled reaction chamber, reacting gas together injects to be fed in vacuum tank by one of the injector/shower nozzle 130 around reaction chamber and middle shower nozzle 135 or both.Reacting gas dissociates after entering plasma reaction chamber under the effect of radio frequency power source 145, and at solution 155 places, abscission zone, the dissociate required ion of reaction of formation and free radical
Fig. 2 illustrates a kind of structural representation of silicon base substrate, and one deck photoresist mask layer 102 is prepared in silicon base 104 tops, and photoresist mask layer 102 obtains the figure of wanted etching by accurate exposure.In etching process, provide fluorine-containing the first gas in plasma etching chamber 100, described the first gas mainly comprises SF 6or NF 3in one or both mist, for silicon base is carried out to etching, the etching gas that the present embodiment is selected is SF 6; Provide siliceous the second gas indoor to plasma etching, described siliceous gas comprises SiF 4, SiCl 4in one or both mist, the present embodiment is selected SiF 4.The second described gas also comprises hydrocarbon, and described hydrocarbon is CO, CO 2in one or both mist.Especially, O in the second described gas 2content is lower than 5%.
Etching gas SF described in the present embodiment 6in plasma etching chamber, 100 internal disintegrations generations include but not limited to following particle to gas: F free radical, F +ion, SF x +and other particles.F free radical can carry out chemical reaction with silicon base 104, generates the SiF of gas 4, F F +ion can bombard silicon base 104 under the effect of electric field, thereby according to the figure of photoresist mask layer 102, silicon base 104 is carried out to etching.In order there to be good anisotropic characteristic aligned in the process at plasma etching silicon, the gas in described the second gas can produce at through-silicon via sidewall the passivation layer of protective effect, and the second gas that the present embodiment is selected comprises siliceous gas and hydrocarbon gas.Described siliceous gas can be SiF 4, SiCl 4in one or both mixing.In plasma-reaction-chamber 100, can dissociate and generate SiF x +, F +the particles such as ion, F free radical; Described hydrocarbon gas comprises CO and CO 2in one or both mixing, it can dissociate and generate C +ion, C free radical, O +the particles such as ion, O free radical, O free radical and SiF x +reaction generates SiO 2with F free radical, F +ion, SiO 2the sidewall surfaces that is deposited on silicon through hole is not corroded by F free radical as passivation layer protective side wall, produced simultaneously F +ion and SF 6the F that dissociates and produce +passivation layer and the silicon base of ion vertical bombardment bottom under high-power condition, thus realize the quick etching to silicon deep hole bottom, and at the sidewall of hole, F +the bombardment intensity of ion pair sidewall a little less than, F plasma is very slow to the etch rate of silicon deep hole sidewall passivation layer, therefore, in whole etching process, lateral etching speed is slow, has good anisotropic feature.
Because oxygen very easily with photoresist mask layer 102, chemical reactions occurs, and the present invention needs to utilize the halide of oxygen radical and silicon to react to generate the protective layer of protection through-silicon via sidewall, therefore the present invention use CO and CO 2in oxo for O 2in oxygen.CO or CO 2in ICP or ECR, dissociate and generate C free radical and O free radical; C free radical generates layer protecting film at photoresist mask layer 102 surface aggregations; protection photoresist mask layer 102 does not react with O free radical, thereby improves the selection ratio of photoresist mask layer 102 and silicon base 104.
In silicon base lithographic technique, utilizing SiF 4or SiCl 4with in oxygen, dissociate oxygen free radical reaction generate in reacting of silicon deep hole side wall protective layer, because oxygen is easy to photoresist mask layer reaction, conventionally adopt hard mask that silica or silicon nitride support as the mask layer of etch silicon substrate.The preparation of hard mask needs comparatively complicated step, first on silicon base surface, by methods such as chemical vapour deposition (CVD)s, prepares certain thickness hard mask, then prepares photoresist coating above hard mask; On photoresist surface, accurately exposure obtains after the figure of wanted etching, described figure first need to be transferred on described hard mask and be removed described photoresist layer, then the described hard mask of usining carries out etching as mask to silicon base, also needs described hard mask to remove after etching completes.Above-mentioned complex process and costly, is unfavorable for cost control, and the figure between a plurality of mask layer shifts the variation may cause critical size, affects the accuracy of substrate etching.The present invention adopts photoresist as mask layer, has replaced existing hard mask, has simplified the etching technics of substrate, has saved cost, adopts photoresist to have enough large selection ratio as mask and silicon base in order to guarantee simultaneously, and the present invention adopts CO and/or CO 2replace O easy and that photoresist reacts 2for depositing the reaction of protective layer, provide oxygen radical.Improved the selection ratio of photoresist mask layer and silicon base.By adopting method of the present invention, the selection ratio of silicon substrate layer 104 and photoresist mask layer 102 is greater than 20.
The etching gas that participates in the present embodiment reaction is mainly SF 6, its flow can be 100sccm-500sccm, can also have a certain amount of Cl 2or HBr, flow can be 50sccm-200sccm; The second gas that generates protective layer comprises SiF 4or SiCl 4in one or both mixture, flow can be 50sccm-300sccm; The gas that generates protective layer also comprises CO or CO 2in one or both mixture, flow can be 50sccm-300sccm.Described in the second gas of described generation protective layer, the ratio of hydrocarbon gas and the ratio of described silicon-containing gas are 4:1-1:1, in order to improve the selection ratio of silicon substrate layer 104 and photoresist mask layer 102, and O in reaction chamber 2content should be less than 5%.
In this execution mode, it is example that the reactive ion etching of take forms TSV, the TSV degree of depth reaches 50-200 μ m, method by the dark silicon etching process of stationary state (Steady-state deep silicon etch process) completes, the reactive ion etching method of this invention concentrates on the control of the gas flow of etching, and therefore, other parameter of reactive ion etching method arranges, for example, radio frequency (RF) power, air pressure, vacuum degree etc. are not limited by the present invention.In this way of example, in etching process, the scope of air pressure be 20 millitorrs (mTorr) to 100 millitorrs (mTorr), radio-frequency power scope is 500W-1000W, rf frequency is 60MHz, the power bracket in bias power source is 50W-100W.
The second gas of fluorine-containing etching gas of the present invention and generation side wall protective layer can inject in ICP reaction chamber simultaneously, and etching reaction and protective layer deposition reaction are carried out simultaneously; Also can control two groups of gases by a gas flow control device (not shown) and alternately enter respectively, etching reaction and protective layer deposition reaction hocket.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Those skilled in the art, read after foregoing, for multiple modification of the present invention with to substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims (11)

1. the method at silicon base etching through hole, described silicon base surface-coated has photoresist mask layer, described lithographic method carries out plasma etching is indoor, it is characterized in that: described method comprises the following steps: that the first gas that provides fluorine-containing is indoor to plasma etching, described the first gas is for carrying out etching to silicon base; Provide siliceous the second gas indoor to plasma etching, the second described gas also comprises hydrocarbon, O in described the second gas 2content is less than 5%.
2. method according to claim 1, is characterized in that: described hydrocarbon is one or both the mist in CO, CO2, and described CO is or/and CO 2flow is 50sccm-300sccm.
3. method according to claim 1, is characterized in that: described the first fluorine-containing gas comprises SF 6or NF 3in one or both mist, described SF 6or/and NF 3gas flow scope be 100sccm-500sccm.
4. method according to claim 1, is characterized in that: described the second gas comprises SiF 4, SiCl 4in one or both mist, described SiF 4and/or SiCl 4gas flow scope be 50sccm-300sccm.
5. method according to claim 1, is characterized in that: described in described the second gas, the ratio of hydrocarbon gas and the ratio of described silicon-containing gas are 4:1-1:1.
6. method according to claim 1, is characterized in that: described the second gas comprises NO, NO 2in one or both mist.
7. method according to claim 1, is characterized in that: described the first gas comprises Cl 2, one or both the mist in HBr, described Cl 2and/or the gas flow scope of HBr is 50sccm-200sccm.
8. method according to claim 1, is characterized in that: described plasma etching chamber is inductively coupled plasma etching chamber or electron cyclotron resonace etching chamber.
9. method according to claim 7, it is characterized in that: the power bracket of the high frequency power source that described plasma etching is indoor is 500w-1000w, the power bracket in low frequency power source is 50w-100w, and the indoor pressure limit of described plasma etching is 20mT-100mT.
10. method according to claim 1, is characterized in that: in described the first gas and the second gas injected plasma simultaneously etching chamber.
11. methods according to claim 1, is characterized in that: described the first gas and the second gas replace in injected plasma etching chamber.
CN201310046733.4A 2013-02-05 2013-02-05 Method for itching through hole in silicon substrate Pending CN103972155A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201310046733.4A CN103972155A (en) 2013-02-05 2013-02-05 Method for itching through hole in silicon substrate
TW103103185A TW201442110A (en) 2013-02-05 2014-01-28 Method for etching through holes on silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310046733.4A CN103972155A (en) 2013-02-05 2013-02-05 Method for itching through hole in silicon substrate

Publications (1)

Publication Number Publication Date
CN103972155A true CN103972155A (en) 2014-08-06

Family

ID=51241506

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310046733.4A Pending CN103972155A (en) 2013-02-05 2013-02-05 Method for itching through hole in silicon substrate

Country Status (2)

Country Link
CN (1) CN103972155A (en)
TW (1) TW201442110A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035694A (en) * 2019-12-25 2021-06-25 中微半导体设备(上海)股份有限公司 Etching method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303512B1 (en) * 1997-02-20 2001-10-16 Robert Bosch Gmbh Anisotropic, fluorine-based plasma etching method for silicon
CN101800175A (en) * 2010-02-11 2010-08-11 中微半导体设备(上海)有限公司 Plasma etching method of silicon-containing insulating layer
CN102031525A (en) * 2009-09-29 2011-04-27 中微半导体设备(上海)有限公司 Method for etching deep through silicon via (TSV)
CN102187437A (en) * 2008-10-23 2011-09-14 朗姆研究公司 Silicon etch with passivation using chemical vapor deposition

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303512B1 (en) * 1997-02-20 2001-10-16 Robert Bosch Gmbh Anisotropic, fluorine-based plasma etching method for silicon
CN102187437A (en) * 2008-10-23 2011-09-14 朗姆研究公司 Silicon etch with passivation using chemical vapor deposition
CN102031525A (en) * 2009-09-29 2011-04-27 中微半导体设备(上海)有限公司 Method for etching deep through silicon via (TSV)
CN101800175A (en) * 2010-02-11 2010-08-11 中微半导体设备(上海)有限公司 Plasma etching method of silicon-containing insulating layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035694A (en) * 2019-12-25 2021-06-25 中微半导体设备(上海)股份有限公司 Etching method

Also Published As

Publication number Publication date
TW201442110A (en) 2014-11-01
TWI541892B (en) 2016-07-11

Similar Documents

Publication Publication Date Title
CN102031525B (en) Method for etching deep through silicon via (TSV)
JP7344867B2 (en) Selective deposition of SiN on horizontal surfaces
US9378975B2 (en) Etching method to form spacers having multiple film layers
US9378978B2 (en) Integrated oxide recess and floating gate fin trimming
US6372655B2 (en) Two etchant etch method
KR20190049482A (en) Method for etching features in a stack
CN100405551C (en) Method to improve profile control and N/P loading in dual doped gate applications
US20150371861A1 (en) Protective silicon oxide patterning
CN105762073A (en) Method and apparatus for anisotropic tungsten etching
JP6423534B2 (en) Etching method and etching apparatus for silicon dioxide substrate
WO2001061750A2 (en) Method of etching a shaped cavity
US20120083128A1 (en) Method for etching high-aspect-ratio features
CN103871956A (en) Silicon deep via etching method
US20150097276A1 (en) Etching oxide-nitride stacks using c4f6h2
CN104347389A (en) Plasma etching method
US20070232070A1 (en) Method and device for depositing a protective layer during an etching procedure
CN103972155A (en) Method for itching through hole in silicon substrate
Lin et al. Deep dry etching of fused silica using C 4 F 8/Ar inductively coupled plasmas
CN103035508B (en) Critical dimension shrink method
CN101928941B (en) Reactive ion etching method for etching silicon
KR101207447B1 (en) Dry-etching method by low pressure capacitively coupled plasma
CN108133888B (en) Deep silicon etching method
US10991595B1 (en) Dry etching process for manufacturing trench structure of semiconductor apparatus
CN105097440A (en) Deep silicon etching method
CN104752191A (en) Inductive Coupled Plasma (ICP) processing chamber, gas injection device thereof and Through-Silicon-Via (TSV) etching method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20140806

RJ01 Rejection of invention patent application after publication