CN103972152A - Manufacturing method for tungsten metal interconnecting wires - Google Patents

Manufacturing method for tungsten metal interconnecting wires Download PDF

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Publication number
CN103972152A
CN103972152A CN201310037708.XA CN201310037708A CN103972152A CN 103972152 A CN103972152 A CN 103972152A CN 201310037708 A CN201310037708 A CN 201310037708A CN 103972152 A CN103972152 A CN 103972152A
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China
Prior art keywords
interlayer dielectric
dielectric layer
grid
tungsten metal
manufacture method
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CN201310037708.XA
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Chinese (zh)
Inventor
蒋莉
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201310037708.XA priority Critical patent/CN103972152A/en
Publication of CN103972152A publication Critical patent/CN103972152A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

The invention provides a manufacturing method for tungsten metal interconnecting wires. The manufacturing method comprises the following steps of providing a semiconductor structure with a grid electrode with grid insulating layers on two sides; surrounding the grid insulating layers by using first interlayer dielectric layers; performing back etching on the grid electrode so as to remove part of the grid electrode and form a groove in the grid electrode; filling the groove by using a deposited silicon nitride layer; grinding the silicon nitride layer by using a chemical and mechanical planarization method; depositing a second interlayer dielectric layer on the surface of a structure formed in the above steps; forming a self-alignment contact hole; and filling the self-alignment contact hole by using deposited tungsten metal so as to form a tungsten metal interconnecting wire. By using the manufacturing method for the tungsten metal interconnecting wires, the tungsten metal interconnecting wires which are not in short-circuiting with the grid electrode can be manufactured, and the problem that the tungsten metal interconnecting wires and the grid electrode can be in short-circuiting easily is solved.

Description

The manufacture method of tungsten metal interconnecting wires
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of manufacture method of tungsten metal interconnecting wires.
Background technology
Semiconductor fabrication process enters the 22nm node epoch at a quick pace.Because critical size reduces, the contact hole forming in semiconductor device is also more and more less, traditional metallic aluminium can not be deposited in contact hole well, thereby people utilize tungsten substitution of Al to make metal interconnecting wires, because the gap filling(trench fill of tungsten) ability is better.
The manufacture method of existing tungsten metal interconnecting wires can, with reference to as shown in Figures 1 to 3, first provide the semiconductor structure with tungsten grid 10, as shown in Figure 1.These tungsten grid 10 both sides include insulation side wall 11, and can include etching stopping layer 12.On etching stopping layer 12, include the first interlayer dielectric layer 13, and on tungsten grid 10, include the second interlayer dielectric layer 14.In subsequent technique, need to make contact hole 15 in tungsten grid 10 both sides, as shown in Figure 2.Now, contact hole 15 passes original the first interlayer dielectric layer 13 and the second interlayer dielectric layer 14, and has passed etching stopping layer 12 simultaneously, thereby forms new the first interlayer dielectric layer 13 ', the second interlayer dielectric layer 14 ' and etching stopping layer 12 '.This contact hole 15 has top and divides opening large, and bottom separates young feature (this feature is because the formation technique of this contact hole 15 determines).Thereby part is easy to expose the corner part (as the border circular areas 17 being marked in Fig. 3) of tungsten grid 10 on this contact hole 15.Like this, when form tungsten metal interconnecting wires 16 in contact hole 15 time, this tungsten metal interconnecting wires 16 easily comes in contact (as the border circular areas 17 being marked in Fig. 3) with tungsten grid 10, thereby tungsten metal interconnecting wires 16 and tungsten grid 10 are short-circuited.
For this reason, need to provide a kind of manufacture method of tungsten metal interconnecting wires to be short-circuited to prevent tungsten metal interconnecting wires and grid.
Summary of the invention
The problem to be solved in the present invention is: in semiconductor device manufacturing process, tungsten metal interconnecting wires and the grid of made are easily short-circuited.
For this reason, the invention provides a kind of manufacture method of tungsten metal interconnecting wires, the tungsten metal interconnecting wires that utilizes this manufacture method to make is not short-circuited with grid.The manufacture method of this tungsten metal interconnecting wires comprises:
The semiconductor structure with grid is provided, and described grid both sides include gate insulation layer, and described gate insulation layer is surrounded by the first interlayer dielectric layer;
Described grid is carried out to etch-back, to remove the described grid of part, form groove;
Deposited silicon nitride layer is filled described groove, and described silicon nitride layer covers described the first interlayer dielectric layer simultaneously;
Adopt chemical mechanical planarization method to grind described silicon nitride layer, be ground to after touching described the first interlayer dielectric layer and stop;
Deposit the body structure surface that the second interlayer dielectric layer forms in above step;
Form self-aligned contact hole, described self-aligned contact hole is through described the first interlayer dielectric layer and described the second interlayer dielectric layer, and described self-aligned contact hole is greater than the aperture at the first interlayer dielectric layer in the aperture of described the second interlayer dielectric layer;
Deposits tungsten metal fills up described self-aligned contact hole;
Described tungsten metal is carried out to planarization, form tungsten metal interconnecting wires.
Optionally, between described gate insulation layer and described the first interlayer dielectric layer, also include etch stop layer.
Optionally, the degree of depth of described groove is 100 dust to 300 dusts.
Optionally, the deposit thickness of described silicon nitride layer is 500 dust to 1000 dusts.
Optionally, the thickness of described the second interlayer dielectric layer is 500 dust to 2000 dusts.
Optionally, described chemical mechanical planarization method adopts concretion abrasive polishing pad.
Optionally, described chemical mechanical planarization method adopts proline homologue to participate in grinding as surfactant.
Optionally, in the scope that described chemical mechanical planarization method is 2.5 ~ 4.8 at pH value, carry out.
Optionally, the down force pressure of described chemical mechanical planarization method is 0.5pSi ~ 3.0pSi.
Optionally, the grinding rotating speed of the described concretion abrasive polishing pad of described chemical mechanical planarization method employing is 10rpm ~ 40rpm.
Optionally, described chemical-mechanical planarization adopts optical end point detector or eletrokinetic potential endpoint detecting device to detect grinding endpoint.
Optionally, described grid is tungsten grid.
Optionally, the width of described grid is less than 20nm.
Compared with prior art, the present invention has the following advantages:
In the manufacture method of tungsten metal interconnecting wires provided by the present invention, may be nitrided silicon insulating material with the grid part of tungsten metal interconnecting wires short circuit replaces, even if thereby tungsten metal interconnecting wires is upper wider and enter grid upper area, also can not there is the short circuit problem of tungsten metal interconnecting wires and grid.
The manufacture method of tungsten metal interconnecting wires provided by the present invention utilizes chemical-mechanical planarization to carry out planarization silicon nitride layer wherein, and makes chemical planarization stop at the first interlayer dielectric layer, forms each layer of smooth semiconductor device.
Brief description of the drawings
Fig. 1 to Fig. 3 is the each step structural representation of the manufacture method of existing tungsten metal interconnecting wires;
Fig. 4 to Figure 11 is the each step structural representation of the manufacture method of embodiment of the present invention tungsten metal interconnecting wires and principle schematic.
Embodiment
The embodiment of the present invention provides a kind of manufacture method of tungsten metal interconnecting wires, utilizes the method can produce the semiconductor device that tungsten metal interconnecting wires and grid are not short-circuited.Manufacture method described in the present embodiment comprises that step S1, to step S7, sets forth the content of each step below in conjunction with Fig. 4 to Figure 11.
Step S1, provides the semiconductor structure with grid, and described grid both sides include gate insulation layer, and described gate insulation layer is surrounded by the first interlayer dielectric layer.
Please refer to Fig. 4, the semiconductor structure of what the present embodiment provided have grid 20, as seen from Figure 4, this semiconductor structure includes grid 20 and gate insulation layer 21.Grid 20 can be to be made by tungsten, titanium or tantalum and their nitride, and the preferred tungsten of the present embodiment is as the material of this grid 20, because the gap filling(trench fill of tungsten) ability is better.And in the present embodiment, the width of grid 20 (that is for the groove of deposition of gate material or the width of through hole below 20nm) below 20nm.Below the width 20nm of groove or through hole time, conventional metal interconnecting wires materials of aluminum metal can not have been filled corresponding groove well, and tungsten metal can be filled corresponding groove or through hole preferably, forms the good tungsten metal interconnect structure of electric conductivity.
This grid 20 can carry out deposit by the method for evaporation, also can form by sputter or chemical vapor deposition (CVD) method.CVD film is compared sputtered film a lot of advantages: low-resistivity, to electromigratory high resistance and fill excellent planarization when small through hole, and CVD tungsten can also provide on metal and silicon, carry out selectively deposited, so the present embodiment preferably adopts CVD method to form grid 20.Concrete, the grid 20 of this CVD method can be prepared from by tungsten chloride, tungsten fluoride and hydroxyl tungsten, and key reaction gas can adopt tungsten hexafluoride and hydrogen or monosilane.This gate insulation layer 21 can be grown by thermal oxidation process, and its material can be all kinds of oxides (for example silica).
Please continue to refer to Fig. 4, in the present embodiment, described gate insulation layer 21 is surrounded by the first interlayer dielectric layer 23, and between described gate insulation layer 21 and described the first interlayer dielectric layer 23, also includes shown in etch stop layer 22(Fig. 4 in structure etch stop layer 22 and be L-type and be positioned at grid 20 both sides).
Step S2, carries out etch-back to described grid, to remove the described grid of part, forms groove.
Please refer to Fig. 5, the present embodiment carries out etch-back to form groove 24 to grid 20.The degree of depth of this groove 24 is 100 dust to 300 dusts, the degree of depth of this groove 24 be chosen in above-mentioned scope be because, in the present embodiment, the thickness of grid 20 is about 300 dust to 600 dusts, thereby the degree of depth of this groove 24 conventionally will be below the half of grid 20 height, thereby the degree of depth of this groove 24 is less than 300 dusts, to ensure that original grid 20 retains height over half.Meanwhile, this groove 24 again can not be too shallow, otherwise follow-uply cannot be used for filling well corresponding material layer, thereby more than the degree of depth of this groove 24 is preferably in 100 dusts.Form after groove 24, original grating 20 becomes grid 20 '.
Step S3, deposited silicon nitride layer is filled described groove, and described silicon nitride layer covers described the first interlayer dielectric layer simultaneously.
Please refer to Fig. 6, the present embodiment is after etching forms above-mentioned groove 24, and deposited silicon nitride layer 25 is filled this groove 24 immediately.As can see from Figure 6, described silicon nitride layer 25 covers described the first interlayer dielectric layer 23 simultaneously, and this silicon nitride layer 25 presents low-lying shape above groove 24.
The present embodiment is preferred, and the deposit thickness of this silicon nitride layer 25 is 500 dust to 1000 dusts.If this silicon nitride layer 25 is too thin, cannot fill up this groove 24 completely.And if this silicon nitride layer 25 is too thick, can increase the weight of the burden of subsequent planarization.Therefore, the thickness of this silicon nitride layer 25 is preferably 500 dust to 1000 dusts.
Step S4, adopts chemical mechanical planarization method to grind described silicon nitride layer, is ground to after touching described the first interlayer dielectric layer and stops.
Incorporated by reference to reference to figure 6, Fig. 7 and Fig. 8, the present embodiment is by chemical-mechanical planarization (ChemicalMechanical Polishing/Planarization, CMP) method, remove the silicon nitride layer 25 of the uneven part shown in Fig. 6, and this planarisation step stops at the first interlayer dielectric layer 23, the structure obtaining structure as shown in Figure 7, wherein uneven silicon nitride layer 25 forms smooth silicon nitride layer 25 ' after being flattened.
In prior art, normally carry out CMP in alkalescence (refer to that polishing fluid is alkalescence, its pH value is greater than 7) under condition, and the normally oxide skin(coating) (for example silicon oxide layer) removed of existing CMP.And the present embodiment adopts carry out CMP in 2.5 ~ 4.8 pH value (refer to the pH value of polishing fluid, available for example PH conditioning agent regulates) scope, and the present embodiment CMP removes is part silicon nitride layer 25, and the stop-layer of planarization is the first interlayer dielectric layer 23.
The present embodiment adopts concretion abrasive polishing pad (Fixed abrasive pad, FAP) to carry out CMP.Polishing pad is the important component part in CMP, and its even wearing performance is the key factor of planeness of workpiece after impact processing.It is excellent and steadily that the present embodiment adopts concretion abrasive polishing pad to carry out surface quality that planarization obtains, and removal efficiency is high.
The present embodiment adopts zwitterionic surfactant to participate in CMP as surfactant and grinds.CMP has comprised chemistry and mechanical double effect, and surfactant plays very important effect in planarization process.Dispersiveness, particle that it not only affects liquid adsorb the rear problems such as complexity and metal ion contamination of cleaning, the more important thing is that surfactant can improve quality transfering rate to improve planarization evenness and to reduce surface tension, reduce damage layer thickness, reduce damage.
The selected zwitterionic surfactant of the present embodiment can include carboxylic acid type (comprising amino acid pattern and betaine type) amphoteric surfactant, sulfuric acid ester type amphoteric surfactant, sulfonate amphoteric surfactant and phosphate ester salt type amphoteric surfactant etc.The present embodiment is further preferred, uses proline homologue to participate in grinding as surfactant.
The present embodiment adopts CeO 2participating in CMP grinds.CeO 2there is chemism height and the less feature of hardness, and be not easy scratch abradant surface at process of lapping, thereby the surface smoothness that can ensure.Meanwhile, CeO 2particle grinding rate is fast, thereby selects CeO 2can improve grinding rate.
The present embodiment is specifically taking L-PROLINE as surfactant, and carries out CMP in the scope that is 2.5 ~ 4.8 at pH value.Described silicon nitride layer 25(SiN), the first interlayer dielectric layer 23(ILD1) and L-PROLINE (L-proline) in corresponding pH value and the scope that is 2.5 ~ 4.8 at pH value, shown while reaching isoelectric point (IEP) electrically as shown in the table:
In CMP process, although each layer all among identical polishing fluid, their Zeta potential (Zeta potential is again electro kinetic potential or eletrokinetic potential, and Zeta-potential or ζ-electromotive force refer to the current potential of shear surface) is different.Isoelectric point (IEP) refers to the situation that the Zeta potential of the surface of solids is zero.In the time that material pH value of living in is less than the pH value that it reaches isoelectric point (IEP), this material can present electropositive.Otherwise when pH value in the time that material pH value of living in is greater than it and reaches isoelectric point (IEP), this material presents elecrtonegativity.In summary, in above table, its current potential is for just within the scope of 2.5 ~ 4.8PH value for the material that tertial positive sign represents this row, and positive sign is more, is more just representing this material current potential now.Tertial negative sign represents that the current potential of this row material within the scope of 2.5 ~ 4.8PH value is for negative, and negative sign is more, represents that this material current potential is now more negative.
Known, in above-mentioned pH value scope (2.5 ~ 4.8), silicon nitride layer 25(SiN), L-PROLINE (L-proline) and abrasive particles CeO 2be positive potential, and electromotive force strength increase, and the first interlayer dielectric layer 23(ILD1) be negative potential.
Please refer to Fig. 8, the present embodiment is with representing L-PROLINE (L-proline) with the ball of positive sign.Polishing particles CeO 2all be positive potential with L-PROLINE (L-proline), although there is the active force of mutual repulsion with the charged particle of same potential, but due to the effect of the amphiprotic group of surfactant, still have part L-PROLINE (L-proline) orientation and be adsorbed in CeO 2surface.And silicon nitride layer 25(SiN) be positive potential, thus the more difficult silicon nitride layer 25(SiN that is adsorbed in of L-PROLINE (L-proline)) surface, as shown in Figure 8, only have a small amount of L-PROLINE (L-proline) to be adsorbed in silicon nitride layer 25(SiN) surface.And the first interlayer dielectric layer 23(ILD1) be negative potential, thereby have a large amount of L-PROLINE (L-proline) and be adsorbed in the first interlayer dielectric layer 23(ILD1) surface, as shown in Figure 8.
In process of lapping, silicon nitride layer 25(SiN) be equivalent to exposedly under concretion abrasive polishing pad, be polished, thereby its can be ground and remove very soon.And conversely, the first interlayer dielectric layer 23(ILD1) by whole protection of L-PROLINE (L-proline), be difficult for being polished.In fact, inventor draws, now the process of lapping of CMP is to silicon nitride layer 25(SiN) removal speed (remove rate) reached 500 A/min of clocks (A/min) to 2000 A/min of clocks, and to the first interlayer dielectric layer 23(ILD1) removal speed be less than 50 A/min of clocks.Thereby the present embodiment can adopt this CMP method to remove uneven silicon nitride layer 25(SiN as shown in Figure 6) and rest on the first interlayer dielectric layer 23(ILD1), form structure as shown in Figure 7.
In the present embodiment, the down force pressure of described CMP method is 0.5pSi ~ 3.0pSi, and the grinding rotating speed of described concretion abrasive polishing pad is 10rpm ~ 40rpm simultaneously, and adopts optical end point detector or eletrokinetic potential endpoint detecting device to detect grinding endpoint.
Step S5, the body structure surface that deposition the second interlayer dielectric layer forms in above step.
The present embodiment, after completing above-mentioned planarisation step, forms the second interlayer dielectric layer 26 in planarization on the flat surfaces forming, as Fig. 9, and its thickness is 500 dust to 2000 dusts.If this second interlayer dielectric layer 26 is too thick, easily cause increasing the etching difficulty of follow-up contact hole, and if this second interlayer dielectric layer 26 is too thin, may cause reaching the effect of insulation isolation.Thereby preferred, the thickness range of this second interlayer dielectric layer 26 is chosen in 500 dust to 2000 dusts.
Step S6, forms self-aligned contact hole, and described self-aligned contact hole is through described the first interlayer dielectric layer and described the second interlayer dielectric layer, and described self-aligned contact hole is greater than the aperture at the first interlayer dielectric layer in the aperture of described the second interlayer dielectric layer.
The self-aligned contact hole 27 forming in the present embodiment as shown in figure 10, described self-aligned contact hole 27 is through described the first interlayer dielectric layer 23 and described the second interlayer dielectric layer 26, form the first new interlayer dielectric layer 23 ' and the second new interlayer dielectric layer 26 ', and described self-aligned contact hole 27 is greater than the aperture at the first interlayer dielectric layer 23 ' in the aperture of described the second interlayer dielectric layer 26 ', now etching stopping layer 22 is also touched hole 27 and passes, and forms the etching stopping layer 22 ' of remainder.
Step S7, deposits tungsten metal fills up described self-aligned contact hole.Described tungsten metal is carried out to planarization, form tungsten metal interconnecting wires.
The last deposits tungsten metal of the present embodiment, in contact hole, forms tungsten metal interconnecting wires 28, as Figure 11.The tungsten metal interconnecting wires 28 that the present embodiment made obtains due to and grid 20 ' between across silicon nitride layer 25 ', thereby can not be short-circuited, the problem of having avoided tungsten metal interconnecting wires and grid to be short-circuited.
In this specification, various piece adopts the mode of going forward one by one to describe, and what each part stressed is and the difference of other parts, between various piece identical similar part mutually referring to.
The foregoing is only specific embodiments of the invention; object is in order to make those skilled in the art better understand spirit of the present invention; but protection scope of the present invention is not taking the specific descriptions of this specific embodiment as limited range; any those skilled in the art is not departing from the scope of spirit of the present invention; can make an amendment specific embodiments of the invention, and not depart from protection scope of the present invention.

Claims (12)

1. a manufacture method for tungsten metal interconnecting wires, is characterized in that, comprising:
The semiconductor structure with grid is provided, and described grid both sides include gate insulation layer, and described gate insulation layer is surrounded by the first interlayer dielectric layer;
Described grid is carried out to etch-back, to remove the described grid of part, form groove;
Deposited silicon nitride layer is filled described groove, and described silicon nitride layer covers described the first interlayer dielectric layer simultaneously;
Adopt chemical mechanical planarization method to grind described silicon nitride layer, be ground to after touching described the first interlayer dielectric layer and stop;
Deposit the body structure surface that the second interlayer dielectric layer forms in above step;
Form self-aligned contact hole, described self-aligned contact hole is through described the first interlayer dielectric layer and described the second interlayer dielectric layer, and described self-aligned contact hole is greater than the aperture at the first interlayer dielectric layer in the aperture of described the second interlayer dielectric layer;
Deposits tungsten metal fills up described self-aligned contact hole, forms tungsten metal interconnecting wires.
2. manufacture method as claimed in claim 1, is characterized in that, between described gate insulation layer and described the first interlayer dielectric layer, also includes etch stop layer.
3. manufacture method as claimed in claim 1, is characterized in that, the degree of depth of described groove is 100 dust to 300 dusts.
4. manufacture method as claimed in claim 1, is characterized in that, the deposit thickness of described silicon nitride layer is 500 dust to 1000 dusts.
5. manufacture method as claimed in claim 1, is characterized in that, the thickness of described the second interlayer dielectric layer is 500 dust to 2000 dusts.
6. manufacture method as claimed in claim 1, is characterized in that, described chemical mechanical planarization method adopts concretion abrasive polishing pad.
7. manufacture method as claimed in claim 6, is characterized in that, described chemical mechanical planarization method adopts proline homologue to participate in grinding as surfactant.
8. manufacture method as claimed in claim 7, is characterized in that, in the scope that described chemical mechanical planarization method is 2.5 ~ 4.8 at pH value, carries out.
9. manufacture method as claimed in claim 8, is characterized in that, the down force pressure of described chemical mechanical planarization method is 0.5pSi ~ 3.0pSi.
10. manufacture method as claimed in claim 6, is characterized in that, the grinding rotating speed of the described concretion abrasive polishing pad that described chemical mechanical planarization method adopts is 10rpm ~ 40rpm.
11. manufacture methods as claimed in claim 10, is characterized in that, described chemical-mechanical planarization adopts optical end point detector or eletrokinetic potential endpoint detecting device to detect grinding endpoint.
12. manufacture methods as claimed in claim 1, is characterized in that, described grid is tungsten grid, and the width of described grid is less than 20nm.
CN201310037708.XA 2013-01-30 2013-01-30 Manufacturing method for tungsten metal interconnecting wires Pending CN103972152A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218272B1 (en) * 1998-05-12 2001-04-17 Samsung Electronic Co., Ltd. Method for fabricating conductive pad
CN1607655A (en) * 2003-10-13 2005-04-20 南亚科技股份有限公司 Bit line for memory assembly and method for making bit line contact window
CN101055873A (en) * 2006-04-12 2007-10-17 国际商业机器公司 Semiconductor device and its forming method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218272B1 (en) * 1998-05-12 2001-04-17 Samsung Electronic Co., Ltd. Method for fabricating conductive pad
CN1607655A (en) * 2003-10-13 2005-04-20 南亚科技股份有限公司 Bit line for memory assembly and method for making bit line contact window
CN101055873A (en) * 2006-04-12 2007-10-17 国际商业机器公司 Semiconductor device and its forming method

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