CN103943505A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103943505A CN103943505A CN201310026101.1A CN201310026101A CN103943505A CN 103943505 A CN103943505 A CN 103943505A CN 201310026101 A CN201310026101 A CN 201310026101A CN 103943505 A CN103943505 A CN 103943505A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 26
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000010276 construction Methods 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000008393 encapsulating agent Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 230000008901 benefit Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000002955 isolation Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor device provided by the invention comprises a vertical MOS transistor, and a dielectric layer is arranged between the drain of the vertical MOS transistor and the main body. The manufacturing method of the semiconductor device comprises the step of manufacturing the dielectric layer located between the drain of the vertical MOS transistor and the main body. According to the semiconductor device provided by the invention, as the dielectric layer is arranged between the drain of the vertical MOS transistor and the main body, current leakage caused by a parasitical bipolar transistor can be effectively restrained and the threshold voltage can be improved. The semiconductor device manufactured by the manufacturing method of the semiconductor device provided by the invention also has the above advantages.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and manufacture method thereof.
Background technology
In technical field of semiconductors, along with the development of semiconductor device processing technology, vertical MOS transistor (vertical MOSFET is called for short VMOS) is because the good device performance of himself possesses more and more wide application prospect.
But in actual applications, traditional vertical MOS transistor (VMOS) is often because the existence of the parasitical bipolar transistor in device is easy to produce large leakage current.In addition, traditional vertical MOS transistor, due to the impact of grid length (gate length), also causes threshold voltage (Vth) less than being easier to.The problems referred to above of traditional VMOS, have caused it in the time of application, will inevitably to affect to a certain extent the performance of semiconductor device.
Therefore, a kind of new semiconductor device and manufacture method thereof need to be proposed, to solve the above-mentioned problems in the prior art.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of semiconductor device and manufacture method thereof.
On the one hand, the invention provides a kind of manufacture method of semiconductor device, wherein said semiconductor device comprises vertical MOS transistor, and described method comprises the step of manufacturing the dielectric layer between drain electrode and the main body of described vertical MOS transistor.
Further, described method comprises:
Step S101: Semiconductor substrate is provided, forms successively the laminated construction that comprises the first insulating barrier, the first sacrifice layer and the second sacrifice layer in described Semiconductor substrate;
Step S102: etching forms the groove that runs through described laminated construction;
Step S103: form the main body of described vertical MOS transistor in described groove, wherein, the height of described main body is lower than described laminated construction;
Step S104: above described main body, the inner side of described groove forms relative the first side wall and the second sidewall;
Step S105: forming the dielectric layer lower than described laminated construction between described the first side wall and the second sidewall, on described main body.
Wherein, the material of described dielectric layer is silicon dioxide.The method that forms described dielectric layer is thermal oxidation method.
Wherein, the method that forms the main body of described vertical MOS transistor is growing epitaxial silicon.
Further, after described step S105, also comprise the steps:
Step S106: remove described the first side wall and the second sidewall, and form encapsulant layer in described groove;
Step S107: remove described the second sacrifice layer, and form the second insulating barrier at top and the sidewall of described encapsulant layer;
Step S108: remove described the first sacrifice layer;
Step S109: form successively first grid dielectric layer and the second gate dielectric layer of described vertical MOS transistor in the both sides of described main body and be positioned at the first grid and the second grid that is positioned at described second gate dielectric layer outside in described first grid dielectric layer outside;
Step S110: the region that is positioned at described main body both sides in described Semiconductor substrate by Implantation forms the first source electrode and second source electrode of described vertical MOS transistor, forms the drain electrode of described vertical MOS transistor above described dielectric layer.
Wherein, between described step S108 and step S109, also comprise the steps:
Carry out light dope processing, form the first light doping section and the second light doping section, form the 3rd light doping section at described encapsulant layer to be positioned at the region of described main body both sides in described Semiconductor substrate.
On the other hand, the invention provides a kind of semiconductor device, wherein said semiconductor device comprises vertical MOS transistor, between the drain electrode of described vertical MOS transistor and main body, is provided with dielectric layer.
Further, described vertical MOS transistor comprises:
Semiconductor substrate;
Be positioned in described Semiconductor substrate and higher than the main body of described Semiconductor substrate;
Be positioned at first source electrode and second source electrode of described Semiconductor substrate in the region of described main body both sides;
Be positioned at first grid and the second grid of described main body both sides; And
Be positioned at the drain electrode of described main body top.
Further, described vertical MOS transistor also comprises:
At the first insulating barrier between described the first source electrode and described first grid and between described the second source electrode and described second grid;
Between described first grid and described main body and perpendicular to the first grid dielectric layer of described Semiconductor substrate and between described second grid and described main body and perpendicular to the second gate dielectric layer of described Semiconductor substrate;
At the second insulating barrier between described first grid and described main body and between described second grid and described main body.
Wherein, the width of described dielectric layer is less than the width of described main body.
Wherein, the material of described dielectric layer is silicon dioxide.
Wherein, the material of described main body is silicon.
Semiconductor device of the present invention, owing to being provided with dielectric layer between the drain electrode at vertical MOS transistor and main body, can effectively suppress the leakage current that causes due to parasitical bipolar transistor, and can improvement threshold voltage (Vth).The manufacture method of semiconductor device of the present invention, can be for the manufacture of the semiconductor device of said structure, thereby the semiconductor device of its manufacture has above-mentioned advantage equally.
Brief description of the drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 O is the schematic cross sectional view of the each step of manufacture method of a kind of semiconductor device of proposing of the present invention;
Wherein, Fig. 1 O is the exemplary cross sectional view of the structure of a kind of semiconductor device of proposing of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.Although it should be understood that and can use term first, second, third, etc. to describe various elements, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms are only used for distinguishing an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., thereby can be used for convenience of description the relation of element shown in description figure or feature and other element or feature here.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprise use and operate in the different orientation of device.For example, if the device in accompanying drawing upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " can comprise upper and lower two orientations.Device can additionally be orientated (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.In the time that this uses, " one " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.It is also to be understood that term " composition " and/or " comprising ", in the time using in these specifications, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.In the time that this uses, term "and/or" comprises any and all combinations of relevant Listed Items.
Here with reference to the cross-sectional view of the schematic diagram as desirable embodiment of the present invention (and intermediate structure), inventive embodiment is described.Like this, can expect due to for example manufacturing technology and/or tolerance cause from shown in the variation of shape.Therefore, embodiments of the invention should not be confined to the given shape in district shown here, but comprise owing to for example manufacturing the form variations causing.For example, the Qi edge, injection region that is shown as rectangle has round or bending features and/or implantation concentration gradient conventionally, instead of binary from injection region to non-injection regions changes.Equally, when the disposal area forming by injection can cause this disposal area and injection to be carried out some injections in the district between the surface of process.Therefore, the district showing in figure is in fact schematically, their shape be not intended display device district true form and be not intended to limit scope of the present invention.
Unless otherwise defined, all terms (comprising technology and scientific terminology) have the identical implication of conventionally understanding with the those of ordinary skill in field of the present invention as used herein.Also will understand, in dictionary such as common use, defined term should be understood to have the implication consistent with they implications in the environment of association area and/or these specifications, and can not explaining in desirable or excessively formal meaning, unless definition so expressly here.
In order thoroughly to understand the present invention, will detailed step and detailed structure be proposed in following description, so that semiconductor device and manufacture method thereof that explaination the present invention proposes.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Embodiment mono-
The embodiment of the present invention provides a kind of semiconductor device, and this semiconductor device can be vertical MOS transistor (VMOS), also can be for having used the semiconductor device (as semiconductor integrated circuit etc.) of VMOS.Wherein, vertical MOS transistor, refers to the transistor with vertical-channel.
The semiconductor device of the embodiment of the present invention, is provided with dielectric layer (dielectric layer) in drain electrode one side (particularly, between transistorized drain electrode and main body) of vertical MOS transistor.Wherein, the material of this dielectric layer, can be silicon dioxide (SiO2) or other dielectric materials.Preferably, the material of dielectric layer is silicon dioxide.
Exemplarily, the semiconductor device of the embodiment of the present invention, can be as shown in Fig. 1 O.Semiconductor device in Fig. 1 O shows a vertical MOS transistor (VMOS), this VMOS comprises Semiconductor substrate 100, be positioned in Semiconductor substrate 100 and higher than the transistorized main body (body) 105 of Semiconductor substrate 100 upper surfaces, be positioned at the first source electrode 1151 and the second source electrode 1152, first grid 1131 and the second grid 1132 of main body 105 both sides and be positioned at the drain electrode 114 of main body 105 tops.At the first insulating barrier 101 between the first source electrode 1151 and first grid 1131 and between the second source electrode 1152 and second grid 1132; Between first grid 1131 and main body 105 perpendicular to the first grid dielectric layer 1121 of Semiconductor substrate 100 and the second gate dielectric layer 1122 perpendicular to Semiconductor substrate 100 between second grid 1132 and main body 105; At the second insulating barrier 109 between first grid 1131 and main body 105 and between second grid 1132 and main body 105.Wherein, the first insulating barrier 101, the second insulating barrier 109 and first grid dielectric layer 1121, second gate dielectric layer 1122, that in fact plays a part is gate insulator, can be referred to as gate dielectric layer.The special feature of VMOS in the semiconductor device of the present embodiment is mainly, also comprises the dielectric layer 107 between main body 105 and drain electrode 114.Wherein, the width of dielectric layer 107 is less than or equal to the width (direction of described width, the direction that refer to be parallel to Semiconductor substrate 100, connects the first source electrode 1151 and the second source electrode 1152) of main body 105.Preferably, the width of dielectric layer 107 is less than the width of main body 105 and dielectric layer 107 and is arranged at the centre of main body 105, as shown in Fig. 1 O.Now, can ensure to drain 114 extends to first grid dielectric layer 1121 and second gate dielectric layer 1122, and then makes transistor have better electric property.In the present invention, dielectric layer 107 also can be referred to as dielectric pocket (dielectric pocket).
Wherein, the material of transistorized main body 105 is generally silicon, can be identical with the material of Semiconductor substrate 100.The material of grid (comprising first grid 1131 and second grid 1132) can be polysilicon or other materials.The material of the first insulating barrier 101, the second insulating barrier 109 and first grid dielectric layer 1121, second gate dielectric layer 1122 can be all silicon dioxide or other suitable insulating material.Source electrode (comprising the first source electrode 1151 and the second source electrode 1152) and drain electrode 114 all can form by the mode of Implantation.
In the present embodiment, the VMOS in a kind of example semiconductor device of the embodiment of the present invention shown in Fig. 1 O, is obviously bipolar transistor.About the particular location relation of each part of this VMOS, those skilled in the art can know with reference to Fig. 1 O, repeats no more herein.
Although Fig. 1 O only shows a VMOS, but the semiconductor device of the embodiment of the present invention, can also comprise multiple transistors or other devices, and the plurality of transistor can be only a part be wherein VMOS as above.In the time that semiconductor device comprises multiple transistors or other devices, between device, can also comprise isolation structure.
The semiconductor device of the embodiment of the present invention, owing to being provided with dielectric layer between the drain electrode at vertical MOS transistor and main body, can effectively suppress the leakage current causing due to the parasitic components in semiconductor device (such as parasitical bipolar transistor), and, can play to a certain extent the effect that increases threshold voltage (Vth), improve transistorized threshold voltage.Thereby, improve the performance of whole semiconductor device.
Embodiment bis-
The manufacture method of the semiconductor device of the embodiment of the present invention, for the manufacture of the semiconductor device described in embodiment mono-.The manufacture method of the semiconductor device of the present embodiment, for the manufacture of the semiconductor device that comprises vertical MOS transistor, it comprises the step of manufacturing the dielectric layer between drain electrode and the main body of vertical MOS transistor.
The detailed step of an illustrative methods of manufacture method of the semiconductor device of embodiment of the present invention proposition is described with reference to Figure 1A-Fig. 1 O below.Wherein, Figure 1A-Fig. 1 O shows the schematic cross sectional view of each step of this illustrative methods.The method is specific as follows:
Step 1: Semiconductor substrate 100 is provided, forms successively the laminated construction that (such as deposition) comprises the first insulating barrier 101, the first sacrifice layer 102 and the second sacrifice layer 103 in Semiconductor substrate 100.The figure forming, as shown in Figure 1A.
Wherein, the material of the first insulating barrier 101 can be silicon dioxide, and the material of the first sacrifice layer 102 can be that the material of silicon nitride, the second sacrifice layer 103 can be silicon dioxide.
As example, in the present embodiment, described Semiconductor substrate 100 selects single crystal silicon material to form.In described Semiconductor substrate, can also be formed with isolation structure, described isolation structure be shallow trench isolation from (STI) structure or selective oxidation silicon (LOCOS) isolation structure, Semiconductor substrate is divided into nmos area and PMOS district by described isolation structure.The channel layer that can also be formed with various traps (well) structure and substrate surface in described Semiconductor substrate, in order to simplify, is omitted in diagram.In general, the ion doping conduction type that forms trap (well) structure is identical with channel layer ion doping conduction type, but concentration is low compared with gate channel layer, and the degree of depth of Implantation is general encloses extensivelyr, needs to reach the degree of depth that is greater than isolation structure simultaneously.The processing step of above-mentioned formation trap (well) structure, isolation structure, grid structure, by those skilled in the art are had the knack of, is described no longer in detail at this.
Step 2: described laminated construction is carried out to etching, and to form the groove 104 that runs through described laminated construction, the figure of formation as shown in Figure 1B.
Particularly, the laminated construction that comprises the first insulating barrier 101, the first sacrifice layer 102 and the second sacrifice layer 103 is carried out to etching, at the position formation groove 104 of intending forming transistorized main body, groove 104 is positioned at described laminated construction and runs through described laminated construction.
Preferably, the sidewall of groove 104 is perpendicular to the surface of Semiconductor substrate 100.
Step 3: in the transistorized main body 105 of the interior formation of groove 104, wherein, the height of main body 105 is lower than the height of described laminated construction.The figure forming, as shown in Figure 1 C.
Wherein, the material of transistorized main body 105 can be silicon; Forming the method for transistorized main body 105, can be epitaxial growth method.
Step 4: above main body 105, the inner side of groove 104 forms relative the first side wall (spacer) 1061 and the second sidewall 1062.Wherein, the first side wall 1061 is near the transistorized first grid of intending forming, and the second sidewall 1062 is near the transistorized second grid of intending forming.The figure forming is as shown in Fig. 1 E.
Exemplarily, step 4 can comprise the steps:
Step 401 forms the 3rd sacrifice layer 106 in Semiconductor substrate 100, and the figure of formation is as shown in Fig. 1 D.Wherein, the material of the 3rd sacrifice layer 106 can be silicon nitride; The method that forms the 3rd sacrifice layer 106 can be deposition.
Step 402: the 3rd sacrifice layer 106 is carried out to etching, form relative the first side wall (spacer) 1061 and the second sidewall 1062 in the inner side of groove 104, as shown in Fig. 1 E.
Step 5: between described the first side wall 1061 and the second sidewall 1062, main body 105 above form lower than the dielectric layer 107 of described laminated construction, the figure of formation is as shown in Fig. 1 F.
Wherein, the material of dielectric layer 107 can be silicon dioxide.The method that forms dielectric layer 107, is preferably thermal oxidation method.
Due to the existence of this step, can between the drain electrode of the transistor making (for vertical MOS transistor) and main body, form dielectric layer, and then effectively suppress the leakage current causing due to parasitical bipolar transistor, and can improvement threshold voltage (Vth).
After completing steps 5, can implement to form according to variety of way of the prior art the step of the parts such as transistorized source electrode, drain electrode, grid.Exemplarily, in embodiments of the present invention, after completing steps 5, the manufacture method of this semiconductor device also comprises the steps:
Step 6: remove the first side wall 1061 and the second sidewall 1062, and at the interior formation encapsulant layer 108 of groove 104.The figure forming, as shown in Fig. 1 H.
Wherein, the material of encapsulant layer 108, is preferably silicon.
Particularly, step 6 can realize as follows:
Step 601, remove the first side wall 1061 and the second sidewall 1062 by etching or other modes, the figure of formation as shown in Figure 1 G.
Step 602, in groove 104, form silicon materials by epitaxial growth method, and remove unnecessary silicon to form encapsulant layer 108 by CMP.The figure forming, as shown in Fig. 1 H.
Step 7: remove the second sacrifice layer 103, as shown in Figure 1 I; Then, form the second insulating barrier 109 at top and the sidewall of encapsulant layer 108, as shown in Fig. 1 J.
Wherein, exemplarily, the material of the second insulating barrier 109 is silicon dioxide, and the method that forms the second insulating barrier 109 is thermal oxidation method.
Step 8: remove the first sacrifice layer 102.The figure forming, as shown in Fig. 1 K.
Wherein, removing the method for the first sacrifice layer 102, can be etching or other common methods.
Step 9: described Semiconductor substrate 100 is carried out to light dope (LDD) and process, carry out light dope processing, form the first light doping section 1101 and the second light doping section 1102, described encapsulant layer 108 formation the 3rd light doping section 111 above described dielectric layer 107 to be positioned at the region of described main body 105 both sides in described Semiconductor substrate 100; That is, form that the first light doping section 1101, the second source region form the second light doping section 1102, drain region forms the 3rd light doping section 111 in transistorized the first source region, the figure of formation is as shown in Fig. 1 L.
In embodiments of the present invention, can omit the lightly doped step described in step 9.And retain this step, and will prevent to a certain extent short-channel effect, there is better technique effect.
Step 10: form successively first grid dielectric layer 1121, second gate dielectric layer 1122 in the both sides of transistorized main body 105, and be positioned at the first grid 1131 in first grid dielectric layer 1121 outsides and be positioned at the second grid 1132 in second gate dielectric layer 1122 outsides, the figure of formation is as shown in Fig. 1 N.
Wherein, the material of first grid dielectric layer 1121, second gate dielectric layer 1122 can be silicon dioxide.The material of first grid 1131 and second grid 1132 can be polysilicon.
Exemplarily, step 10 can comprise the steps:
Step 1001, form successively first grid dielectric layer 1121 and second gate dielectric layer 1122 in the both sides of transistorized main body 105, and in described Semiconductor substrate 100, form (such as deposition) one deck gate material layers 1130.The figure forming, as shown in Fig. 1 M.
Wherein, gate material layers 1130 can be polysilicon.
Step 1002, described gate material layers 1130 is carried out to etching, form the first grid 1131 that is positioned at first grid dielectric layer 1121 outsides and the second grid 1132 that is positioned at second gate dielectric layer 1122 outsides, as shown in Fig. 1 N.
Step 11: Semiconductor substrate 100 is carried out to Implantation, form transistorized the first source electrode 1151, the second source electrode 1152 and drain electrode 114.The figure forming, as shown in Fig. 1 O.
So far, completed the committed step of the manufacture method of the semiconductor device of the embodiment of the present invention.Next, can, according to the manufacturing process of traditional semiconductor device, complete the manufacture of the semiconductor device of the embodiment of the present invention, repeat no more herein.
The manufacture method of the semiconductor device of the embodiment of the present invention, between transistorized drain electrode and main body, form dielectric layer (dielectric layer), thereby can effectively suppress the leakage current causing due to parasitical bipolar transistor, and can improvement threshold voltage (Vth), can play the effect that increases threshold voltage.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for semiconductor device, is characterized in that, described semiconductor device comprises vertical MOS transistor, and described method comprises the step of manufacturing the dielectric layer between drain electrode and the main body of described vertical MOS transistor.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described method comprises:
Step S101: Semiconductor substrate is provided, forms successively the laminated construction that comprises the first insulating barrier, the first sacrifice layer and the second sacrifice layer in described Semiconductor substrate;
Step S102: etching forms the groove that runs through described laminated construction;
Step S103: form the main body of described vertical MOS transistor in described groove, wherein, the height of described main body is lower than described laminated construction;
Step S104: above described main body, the inner side of described groove forms relative the first side wall and the second sidewall;
Step S105: forming the dielectric layer lower than described laminated construction between described the first side wall and the second sidewall, on described main body.
3. the manufacture method of semiconductor device as claimed in claim 2, is characterized in that, the material of described dielectric layer is silicon dioxide.
4. the manufacture method of semiconductor device as claimed in claim 2, is characterized in that, the method that forms described dielectric layer is: thermal oxidation method.
5. the manufacture method of semiconductor device as claimed in claim 2, is characterized in that, the method that forms the main body of described vertical MOS transistor is growing epitaxial silicon.
6. the manufacture method of the semiconductor device as described in claim 2 ~ 5 any one, is characterized in that, after described step S105, also comprises the steps:
Step S106: remove described the first side wall and the second sidewall, and form encapsulant layer in described groove;
Step S107: remove described the second sacrifice layer, and form the second insulating barrier at top and the sidewall of described encapsulant layer;
Step S108: remove described the first sacrifice layer;
Step S109: form successively first grid dielectric layer and the second gate dielectric layer of described vertical MOS transistor in the both sides of described main body and be positioned at the first grid and the second grid that is positioned at described second gate dielectric layer outside in described first grid dielectric layer outside;
Step S110: the region that is positioned at described main body both sides in described Semiconductor substrate by Implantation forms the first source electrode and second source electrode of described vertical MOS transistor, forms the drain electrode of described vertical MOS transistor above described dielectric layer.
7. the manufacture method of semiconductor device as claimed in claim 6, is characterized in that, between described step S108 and step S109, also comprises the steps:
Carry out light dope processing, form the first light doping section and the second light doping section, form the 3rd light doping section at described encapsulant layer to be positioned at the region of described main body both sides in described Semiconductor substrate.
8. a semiconductor device, is characterized in that, described semiconductor device comprises vertical MOS transistor, between the drain electrode of described vertical MOS transistor and main body, is provided with dielectric layer.
9. semiconductor device as claimed in claim 8, is characterized in that, described vertical MOS transistor comprises:
Semiconductor substrate;
Be positioned in described Semiconductor substrate and higher than the main body of described Semiconductor substrate;
Be positioned at first source electrode and second source electrode of described Semiconductor substrate in the region of described main body both sides;
Be positioned at first grid and the second grid of described main body both sides; And
Be positioned at the drain electrode of described main body top.
10. semiconductor device as claimed in claim 9, is characterized in that, described vertical MOS transistor also comprises:
At the first insulating barrier between described the first source electrode and described first grid and between described the second source electrode and described second grid;
Between described first grid and described main body and perpendicular to the first grid dielectric layer of described Semiconductor substrate and between described second grid and described main body and perpendicular to the second gate dielectric layer of described Semiconductor substrate;
At the second insulating barrier between described first grid and described main body and between described second grid and described main body.
11. semiconductor device as described in claim 8 ~ 10 any one, is characterized in that, the width of described dielectric layer is less than the width of described main body.
12. semiconductor device as described in claim 8 ~ 10 any one, is characterized in that, the material of described dielectric layer is silicon dioxide.
13. semiconductor device as described in claim 8 ~ 10 any one, is characterized in that, the material of described main body is silicon.
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| US20090189217A1 (en) * | 2004-11-08 | 2009-07-30 | Jae-Man Yoon | Semiconductor Memory Devices Including a Vertical Channel Transistor |
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