CN103928434A - FCBGA single-chip package based on Flux and manufacturing process thereof - Google Patents

FCBGA single-chip package based on Flux and manufacturing process thereof Download PDF

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Publication number
CN103928434A
CN103928434A CN201410123344.1A CN201410123344A CN103928434A CN 103928434 A CN103928434 A CN 103928434A CN 201410123344 A CN201410123344 A CN 201410123344A CN 103928434 A CN103928434 A CN 103928434A
Authority
CN
China
Prior art keywords
chip
substrate
flux
flux layer
salient points
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410123344.1A
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Chinese (zh)
Inventor
刘卫东
谌世广
崔梦
马利
李涛涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Xian Co Ltd
Original Assignee
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Xian Co Ltd filed Critical Huatian Technology Xian Co Ltd
Priority to CN201410123344.1A priority Critical patent/CN103928434A/en
Publication of CN103928434A publication Critical patent/CN103928434A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention relates to an FCBGA single-chip package based on Flux and a manufacturing process of the FCBGA single-chip package, and belongs to the technical field of integrated circuit packaging. Sn salient points and Ag salient points on a chip are connected with a substrate through a Flux layer in a reflow soldering mode, the Flux layer is arranged on the substrate, the Sn salient points and the Ag salient points on the chip are arranged on the Flux layer, the substrate is surrounded by a plastic package which can support and protect the chip and the Sn salient points and the Ag salient points on the chip, the Flux layer, the Sn salient points and the Ag salient points on the chip and the substrate form the whole of a circuit, and the chip, the Sn salient points and the Ag salient points on the chip and the substrate form a power supply and signal channel of the circuit. By the adoption of a wafer thinning packaging process based on Flux, the thinning process is conducted after post curing of the package, it is guaranteed that a wafer is thinned under 50 micrometers, the warping probability of the wafer is greatly reduced, the size of the package is smaller, performance is higher, and reliability of the package is remarkably improved.

Description

A kind of FCBGA single-chip package part and manufacture craft thereof based on Flux
Technical field
The present invention relates to a kind of FCBGA single-chip package part and manufacture craft thereof based on Flux, belong to integrated antenna package technical field.
Background technology
Flip Chip is a kind of chip interconnects technology, is again a kind of desirable die bonding technology. as far back as 30Nian Qian IBM Corporation, researched and developed this technology of having used.But until in recent years,, Flip-Chip had become the packing forms often adopting in high-end device and high-density packages field.Today, the range of application of Flip-Chip encapsulation technology is increasingly extensive, and packing forms is variation more, and the requirement of Flip-Chip encapsulation technology is also improved thereupon.Meanwhile, Flip-Chip has also proposed a series of new severe challenges to producer, for this complicated technology provides encapsulation, and the reliable support of assembling and test.One-level sealing technique is in the past all that the active area of chip is faced up, and back to substrate and the rear bonding of subsides, as strong the closing with carrier band that go between perfected (TAB) automatically.FC faces substrate by chip active area, by being the solder bump of arrayed on chip, realize the interconnection of chip and substrate. silicon chip is directly installed to PCB in back-off mode and to surrounding, draws I/O from silicon chip, interconnected length shortens greatly, reduced RC delay, effectively improved electrical property. obviously, this chip interconnects mode can provide higher I/O density. and upside-down mounting occupied area is almost consistent with die size. and in all surface mounting technique, flip-chip can reach minimum, the thinnest encapsulation.But due to the limitation of conventional package in the past, wafer can only be thinned to 200um, and the thickness being particularly thinned to below 150um is easy warpage, and package reliability can not be guaranteed.
Summary of the invention
The problem existing in order to overcome above-mentioned prior art, the object of this invention is to provide a kind of FCBGA single-chip package part and manufacture craft thereof based on Flux, adopt a kind of wafer attenuate packaging technology based on Flux, employing is carried out attenuate operation after solidifying after packaging part again, guaranteed that wafer is thinned to below 50um, and the very big possibility that must reduce silicon wafer warpage, make package size thinner, performance is higher, significantly improves the reliability of packaging part.
The technical solution used in the present invention: single-chip package part comprises substrate, Flux layer, chip, filler 4, corase grind part, fine grinding part, plants ball, plastic-sealed body; Sn in its chips, Ag salient point are connected by Reflow Soldering by Flux layer with substrate; it on substrate, is Flux layer; on Flux layer, be Sn, the Ag salient point on chip; the plastic-sealed body that Sn on chip and chip, Ag salient point have been played to support and protective effect has surrounded the integral body that Sn, Ag salient point and substrate on substrate, Flux layer, chip formed circuit, and the Sn on chip, chip, Ag salient point and substrate have formed power supply and the signalling channel of circuit.
The manufacture craft of described a kind of FCBGA single-chip package part based on Flux, carries out according to step below;
The first step, upper core, Reflow Soldering: on substrate, plate Flux layer, on chip, directly with Sn, Ag and substrate, cross Reflow Soldering, form interconnect;
Second step, utilize plasma cleaner to clean impurity;
The 3rd step, use filler filling product space, protective circuit and salient point;
The 4th step, rear solidifying: adopt traditional handicraft to carry out;
The 5th step, wafer attenuate: thickness thinning is thinned to 50um, rear separation of products;
The 6th step, plant ball, check, packing, warehouse-in; Technique is same traditional handicraft all.
Beneficial effect of the present invention: the present invention adopts a kind of wafer attenuate packaging technology based on Flux, employing is carried out attenuate operation after solidifying after packaging part again, guaranteed that wafer is thinned to below 50um, and the very big possibility that must reduce silicon wafer warpage, make package size thinner, performance is higher, significantly improves the reliability of packaging part.
Accompanying drawing explanation
Fig. 1 substrate profile;
Fig. 2 substrate plating Flux layer product profile;
Product profile after core, Reflow Soldering on Fig. 3;
Fig. 4 fills rear product profile;
Product profile after Fig. 5 chip corase grind;
Fig. 6 refines rear product profile;
Fig. 7 plants finished product profile after ball.
In figure: 1-substrate, 2-Flux layer, 3-chip, 4-filler, 5-corase grind part, 6-fine grinding part, 7-plant ball, 8-plastic-sealed body.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described, to facilitate the technical staff to understand.
As shown in Fig. 1-7: the present invention includes substrate 1, Flux layer 2, chip 3, filler 4, corase grind part 5, fine grinding part 6, plant ball 7, plastic-sealed body 8; Sn in its chips 3, Ag salient point are connected by Reflow Soldering by Flux layer 2 with substrate 1; it on substrate 1, is Flux layer 2; on Flux layer 2, be Sn, the Ag salient point on chip 3; the plastic-sealed body 8 that Sn on chip 3 and chip 3, Ag salient point have been played to support and protective effect has surrounded the integral body that Sn, Ag salient point and substrate 1 on substrate 1, Flux layer 2, chip 3 formed circuit, and the Sn on chip 3, chip 3, Ag salient point and substrate 1 have formed power supply and the signalling channel of circuit.
The manufacture craft of described a kind of FCBGA single-chip package part based on Flux, according to step below, carry out:
The first step, upper core, Reflow Soldering: on substrate 1, plate Flux layer 2, on chip, directly with Sn, Ag and substrate, cross Reflow Soldering, form interconnect;
Second step, utilize plasma cleaner to clean impurity;
The 3rd step, use filler 4 filling product spaces, protective circuit and salient point;
The 4th step, rear solidifying: adopt traditional handicraft to carry out;
The 5th step, wafer attenuate: thickness thinning is thinned to 50um, rear separation of products;
The 6th step, plant ball, check, packing, warehouse-in; Technique is same traditional handicraft all.
The present invention describes by specific implementation process, without departing from the present invention, can also carry out various conversion and be equal to replacement patent of the present invention, therefore, patent of the present invention is not limited to disclosed specific implementation process, and should comprise the whole embodiments that fall within the scope of Patent right requirement of the present invention.
  

Claims (2)

1. the FCBGA single-chip package part based on Flux, is characterized in that: single-chip package part comprises substrate, Flux layer, chip, filler, corase grind part, fine grinding part, plants ball, plastic-sealed body; Sn in its chips, Ag salient point are connected by Reflow Soldering by Flux layer with substrate, it on substrate, is Flux layer, on Flux layer, be Sn, the Ag salient point on chip, plastic-sealed body has surrounded the integral body that Sn, Ag salient point and substrate on substrate, Flux layer, chip formed circuit, and the Sn on chip, chip, Ag salient point and substrate have formed power supply and the signalling channel of circuit.
2. a manufacture craft for the FCBGA single-chip package part based on Flux, is characterized in that: described manufacture craft is carried out according to step below:
The first step, upper core, Reflow Soldering: on substrate, plate Flux layer, on chip, directly with Sn, Ag and substrate, cross Reflow Soldering, form interconnect;
Second step, utilize plasma cleaner to clean impurity;
The 3rd step, use filler filling product space, protective circuit and salient point;
The 4th step, rear solidifying: adopt traditional handicraft to carry out;
The 5th step, wafer attenuate: thickness thinning is thinned to 50um, rear separation of products;
The 6th step, plant ball, check, packing, warehouse-in; Technique is same traditional handicraft all.
CN201410123344.1A 2014-03-31 2014-03-31 FCBGA single-chip package based on Flux and manufacturing process thereof Pending CN103928434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410123344.1A CN103928434A (en) 2014-03-31 2014-03-31 FCBGA single-chip package based on Flux and manufacturing process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410123344.1A CN103928434A (en) 2014-03-31 2014-03-31 FCBGA single-chip package based on Flux and manufacturing process thereof

Publications (1)

Publication Number Publication Date
CN103928434A true CN103928434A (en) 2014-07-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410123344.1A Pending CN103928434A (en) 2014-03-31 2014-03-31 FCBGA single-chip package based on Flux and manufacturing process thereof

Country Status (1)

Country Link
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894108A (en) * 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
CN1750259A (en) * 2004-09-15 2006-03-22 日月光半导体制造股份有限公司 Multiple chip packaged conductor frame, its producing method and its package structure
CN103094236A (en) * 2012-12-28 2013-05-08 华天科技（西安）有限公司 Single-chip package part with wafer thinned after bottom fillers cures and manufacture process thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5894108A (en) * 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
CN1750259A (en) * 2004-09-15 2006-03-22 日月光半导体制造股份有限公司 Multiple chip packaged conductor frame, its producing method and its package structure
CN103094236A (en) * 2012-12-28 2013-05-08 华天科技（西安）有限公司 Single-chip package part with wafer thinned after bottom fillers cures and manufacture process thereof

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Application publication date: 20140716

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