CN103887262A - Stacked package and manufacturing method thereof - Google Patents
Stacked package and manufacturing method thereof Download PDFInfo
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- CN103887262A CN103887262A CN201210554882.7A CN201210554882A CN103887262A CN 103887262 A CN103887262 A CN 103887262A CN 201210554882 A CN201210554882 A CN 201210554882A CN 103887262 A CN103887262 A CN 103887262A
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- stacked
- stacked structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention provides a stacked package and a manufacturing method thereof. The stacked package comprises a substrate, a stacked structure and at least one conductive band. The stacked structure is located on the substrate. The stacked structure comprises a top surface and a plurality of sidewalls. The stacked structure comprises a plurality of conductive pattern layers. The sidewalls are exposed from the conductive pattern layers. The conductive band is arranged on the sidewalls. The conductive band is electrically connected with some of the conductive pattern layers. The conductive band of the stacked package of the invention can be electrically connected with different semiconductor elements.
Description
Technical field
The present invention relates to a kind of stacked package part and its manufacture method, and be particularly related to stacked package part and its manufacture method with conducting wire.
Background technology
The structure of current semiconductor element stacked package part comprises wafer-to-wafer stacking (Die Stacking) and packaged type stacked structure (Package Stacking), for improving the line density of overall semiconductor element and reducing the volume of encapsulation, conventionally semiconductor element stacked package part adopts the combination of three-dimensional perpendicular stacking (Vertically Integrated Circuits, VIC) to integrate.
About the stacking combination of existing three-dimensional perpendicular; common wafer stacked structure is to use silicon perforation (Through Silicon Via; TSV) semiconductor process techniques; on each crystal grain or wafer, make perforation (via); again electric conducting material is inserted in perforation to form internal vertical conducting wire, finally again that wafer is in addition stacking and in conjunction with (bonding).In addition, in packaged type stacking (Package Stacking), conventionally adopt tin ball or tin post as the inner conductive circuit between each layer circuit board, and every layer circuit board all disposes multiple electronic components, then carrying out sealing makes encapsulating structure according to this again.
Generally speaking,, in conducting stacked package part, the conducting wire of the semiconductor element of each layer is all positioned at the inside of stacked package part.Lightening along with stacked package part, the design of conducting wire also gets over densification and complicated, therefore make the encapsulating structure of stacked package part and manufacture method be tending towards complicated, and manufacture difficulty also improves.
Summary of the invention
The manufacture method that the object of this invention is to provide a kind of stacked package part and stacked package part, the conductive strips that stacked package part has can be electrically connected different semiconductor elements.
For achieving the above object, the embodiment of the present invention provides a kind of stacked package part, and described stacked package part comprises substrate, stacked structure and at least one conductive strips.Stacked structure is positioned on substrate, and stacked structure has an end face and multiaspect sidewall, and stacked structure comprises multiple conductive pattern layer, and wherein sidewall exposes conductive pattern layer.Conductive strips are disposed on sidewall, and conductive strips and wherein at least two-layer conductive pattern layer electric connection.
In an embodiment of the present invention, this stacked structure also comprises multiple semiconductor elements, described multiple semiconductor element is laminated to each other side by side, and wherein described in one deck, conductive pattern layer is between adjacent two described semiconductor elements, and described at least one conductive strips are electrically connected wherein two described semiconductor elements.
In an embodiment of the present invention, this semiconductor element is wafer.
In an embodiment of the present invention, this semiconductor element is package module.
In an embodiment of the present invention, this conductive pattern layer is re-wiring layer.
In an embodiment of the present invention, this stacked structure also comprises multiple insulating barriers, and described in each, insulating barrier is wherein between adjacent two described semiconductor elements.
In an embodiment of the present invention, this stacked structure also comprises mould sealing, and this mould sealing covers this stacked structure and this conductive strips and is disposed on this substrate.
In an embodiment of the present invention, this stacked structure comprises conductive layer, and this conductive layer covers this mould sealing.
The embodiment of the present invention provides a kind of manufacture method of stacked package part, in order to improve the technique of the existing electric connection for stacked package part.
The embodiment of the present invention provides a kind of manufacture method of stacked package part, the manufacture method of described stacked package part comprises that formation stacked structure is on substrate, described stacked structure has an end face and multiaspect sidewall, and stacked structure comprises multiple conductive pattern layer, and wherein sidewall exposes conductive pattern layer.Stacked structure is carried out to patterned process, form according to this at least one conductive strips, wherein conductive strips are positioned on sidewall and connect wherein at least two-layer conductive pattern layer.
In an embodiment of the present invention, forming the step of this stacked structure on this substrate comprises:
Multiple semiconductor elements are provided, and described in each, semiconductor element has first surface and the second surface of this first surface relatively; Multiple semiconductor elements described in rewiring, to form this conductive pattern layer of one deck on first surface described in each; Described in each, on first surface, form protective layer, described multiple protective layers cover described multiple conductive pattern layer; And superimposed described multiple semiconductor elements, and wherein described in one this first surface of semiconductor element be positioned under the second surface of semiconductor element described in another, and described in each protective layer between two adjacent described semiconductor elements.
The step of in an embodiment of the present invention, this stacked structure being carried out to patterned process comprises: cover shade on this stacked structure; Deposits conductive material is on this shade; And remove this shade.
In an embodiment of the present invention, this shade has multiple openings, and described multiple openings are in order to expose the described multiple conductive pattern layer of part that are positioned at this end face and this sidewall.
In an embodiment of the present invention, the manufacture method of this stacked package part also comprises: form mould sealing, this mould sealing is covered in this stacked structure and this conductive strips.
In an embodiment of the present invention, the manufacture method of this stacked package part also comprises: form conductive layer and be covered on this mould sealing.
In sum, described stacked package part has conductive strips, and the variation of length, quantity and distributing position by conductive strips, makes conductive strips can serve as the electrically connect of stacked structure, so simplify encapsulating structure with and manufacture method.Because conductive strips are disposed on the sidewall of stacked structure, and be connected at least two-layer conductive pattern layer that sidewall exposes, therefore semiconductor element is able to be electrically connected by conductive strips each other, and can simplify the process structure of encapsulation.
For enabling further to understand feature of the present invention and technology contents, refer to following about detailed description of the present invention and accompanying drawing, but these explanations are only used for illustrating the present invention with accompanying drawing, but not claim scope of the present invention are done to any restriction.
Accompanying drawing explanation
Figure 1A is the schematic top plan view of the stacked package part of the embodiment of the present invention.
Figure 1B is the generalized section that in Figure 1A, P-P section along the line illustrates.
Fig. 2 A ~ Fig. 2 E is half-finished schematic diagram that the manufacture method of the stacked package part in Figure 1B forms in each step
Wherein, description of reference numerals is as follows:
100 stacked package parts
110 substrates
120 stacked structures
122 end faces
124 sidewalls
126 conductive pattern layer
127 insulating barriers
128a, 128b, 128c, 128d semiconductor element
130 conductive strips
140 mould sealings
150 conductive layers
160 shades
162 openings
P1 the first patterned layer
P2 the second patterned layer
S1 first surface
S2 second surface
Embodiment
Show in the accompanying drawings some exemplary embodiments, and below will consult accompanying drawing to describe more fully various exemplary embodiments.What deserves to be explained is, concept of the present invention may be with many multi-form embodiments, and should not be construed as and be limited to the exemplary embodiments set forth herein.Specifically, provide the exemplary embodiments such as all to make the present invention will be for detailed and complete, and will fully pass on the category of concept of the present invention to those of ordinary skills.In each accompanying drawing, can be for explicit and lavish praise on oneself size and the relative size in Ceng Ji district, and similar numeral indication like.
Although may describe various elements by term first, second, third, etc. herein, these elements are not limited by these terms should.These terms are to distinguish an element and another element, and therefore, the first element of below discussing can be described as the second element and do not depart from the teaching of concept of the present invention.In addition, may use herein term " and/or ", this is that indication comprises any one and one or many person's all combinations in project of listing that are associated.
Stacked package part of the present invention can be a kind of encapsulating structure that is applied to semiconductor element.Stacked package part is using the conductive strips on sidewall as the electrically connect between semiconductor element, to simplify process structure and the method flow of encapsulation.Stacked package part of the present invention comprises various embodiments, and the present invention wherein the stacked structure of the stacked package part of an embodiment can be that multiple wafers or multiple circuit board assemblies present three-dimensional stacked arrangement.Below will coordinate Figure 1A to Fig. 2 that above-mentioned stacked package part is described.
Figure 1A is the schematic top plan view of the stacked package part of the embodiment of the present invention, and Figure 1B is the generalized section that in Figure 1A, P-P section along the line illustrates.Refer to Figure 1A and Figure 1B, stacked package part 100 comprises substrate 110, stacked structure 120 and conductive strips 130.Stacked structure 120 is disposed at substrate 110 tops, and conductive strips 130 are disposed at the sidewall 124 of stacked structure 120, by the distribution of conductive strips 130, in stacked structure 120, between the semiconductor element 128 of different layers, is electrically connected.
Stacked structure 120 is disposed on substrate 110, and in practice, substrate 110 can be used as the carrier that circuit and electronic component configure, that is not yet configures wafer carrier or the circuit substrate of wafer/electronic component.On substrate 110, dispose connection pad (Pad) and circuit (trace), and normally epoxy resin (Epoxy resin), cyanogen fat resin core thin plate (Cyanate ester core of the material of substrate 110, CE core) or the material such as two butadiene dilute acid acid imide core thin plate (Bismaleimide core, BMI core).But, the present invention does not limit the material of substrate 110.
Stacked structure 120 has an end face 122 and multiaspect sidewall 124.Each sidewall 124 is all connected with end face 122 and around end face 122.In addition, in this embodiment, the quantity of sidewall 124 is four sides, and but, the present invention does not limit the quantity of sidewall.
It should be noted that conductive pattern layer 126 is for re-wiring layer (redistribution layer, RDL), with so that be disposed at the circuit of semiconductor element 128 and be reconfigured in the edge of semiconductor element 128.Conductive pattern layer 126 comprises the first patterned layer P1 and the second patterned layer P2, and the first patterned layer P1 is connection pad (Pad), and the second patterned layer P2 is circuit (trace), and wherein the second patterned layer P2 is connected with the first patterned layer P1.Accordingly, the signal of telecommunication can input to semiconductor element 128 via conductive pattern layer 126, and exports from semiconductor element 128.
In addition, in the present embodiment, semiconductor element 128 can comprise all kinds, that is the kind of these semiconductor elements 128 can not need identical.Multiple semiconductor elements 128 can be different electronic components, for example, be wafer, electric capacity, inductance or circuit board assemblies (circuit board assembly) etc.The kind of semiconductor element 128 can be differing from each other, and Figure 1B represents with semiconductor element 128a, 128b, 128c and 128d.But, the quantity to semiconductor element 128 and kind are not limited in the present invention.
Stacked structure 120 comprises multiple insulating barriers 127, and each insulating barrier 127 is all disposed between adjacent two semiconductor elements 128.Insulating barrier 127 is in order to avoid the producing unnecessary situation such as electric connection or short circuit between conductive pattern layer 126, and insulating barrier 127 also can and engage these semiconductor elements 128 in order to protection.Insulating barrier 127 is disposed between each semiconductor element 128, makes the outward appearance of stacked structure 120 be presented three-dimensional stacked complexion.On the end face 122 of stacked structure 120, dispose conductive pattern layer 126, and every sidewall 124 all exposes the conductive pattern layer 126 between these semiconductor elements 128.
What deserves to be explained is, insulating barrier 127 can be sticky brilliant glue, in order to engage each wafer, for example, is the sticky brilliant glue-line (Die Attach Film, DAF) of film-type, elargol etc.In addition, insulating barrier 127 can be also to be formed by the prepreg bed of material of tool viscosity (Preimpregnated Material), wherein the prepreg bed of material is for example the materials such as glass fibre prepreg (Glass fiber prepreg), carbon fibre initial rinse material (Carbon fiber prepreg) or epoxy resin (Epoxy resin), in order to engage each package module.
In order to adapt to the stacked package part of different electric connection design, can be according to product demand length, quantity and the distributing position of designed, designed conductive strips 130.Take Figure 1B as example, in all conductive strips 130, some conductive strips 130 can be connection pad and the circuits that is extended to substrate 110 by the conductive pattern layer 126 of semiconductor element 128a, and therefore semiconductor element 128a is able to be electrically connected with substrate 110.Some conductive strips 130 can be also the conductive pattern layer 126 that is extended to semiconductor element 128c by the conductive pattern layer 126 of semiconductor element 128b, and therefore semiconductor element 128b is able to be electrically connected with semiconductor element 128c.But, the shape to conductive strips, quantity and distributing position are not limited in the present invention.
Stacked package part 100 can more comprise mould sealing 140, and mould sealing 140 covers stacked structure 120 and conductive strips 130, and mould sealing 140 is also covered on substrate 110.Generally speaking, mould sealing 140 is adhesive body, in order to coated stacked structure 120, reduces the erosion that stacked structure 120 is subject to the harmful effect of external force, moisture or temperature or is subject to other materials.Mould sealing 140 can be macromolecular material, for example epoxy mould envelope compound (Epoxy Molding Compound, EMC), polyimides (Polyimide, PI), phenolic resins (Phenolics) or silicones (Silicones) etc., be covered on stacked structure 120 to shift forming mode (transfermolding).In addition, mould sealing 140 can be also ceramic material.But, the present invention is not limited the material of mould sealing.
In addition, according to the product demand of each stacked package part, stacked package part 100 can more comprise conductive layer 150, and conductive layer 150 is covered on mould sealing 140.Conductive layer 150 is as ELECTROMAGNETIC OBSCURANT (Electromagnetic Interference, EMI) layer, in order to reduce electromagnetic interference effect and radio frequency interference effect.Conductive layer 150 can be metal material, for example, be the materials such as copper, aluminium or patina nickel.Conductive layer 150 can be also conducting polymer composite, and for example, polyaniline (Polyaniline, PAn), poly-arsenic are coughed up the material such as (Polypyrrole, PYy) or poly-match fen (Polythiophene, PTh).But, the present invention does not limit the material of conductive layer 150.
Fig. 2 A ~ Fig. 2 E is respectively half-finished schematic diagram that the manufacture method of the stacked package part of the embodiment of the present invention forms in each step.Then, please sequentially coordinate Fig. 2 A ~ Fig. 2 E to consult.
First, provide substrate 110, and on substrate 110, configure a stacked structure 120.Refer to Fig. 2 A, specifically, provide semiconductor element 128d, and semiconductor element 128d has the second surface S2 of first surface S1 and relative first surface S1.Semiconductor element 128d is disposed on substrate 110 and with substrate 110 and is electrically connected.
Specifically, first by rewiring semiconductor element 128a, 128b, 128c and 128d, to change circuit (trace) and the connection pad (pad) of designing semiconductor element 128a, 128b, 128c and 128d of original made.Specifically, first, first define with lithography process (Photolithography) conductive pattern of wanting to reconfigure, recycling is electroplated and/or conductive pattern layer 126 is produced in etching, thereby the circuit on semiconductor element 128a, 128b, 128c and 128d is reconfigured on semiconductor element 128a, 128b, 128c and 128d and edge thereof, to form conductive pattern layer 126.Conductive pattern layer 126 is disposed on the first surface S1 of each semiconductor element 128a, 128b, 128c and 128d.Hold above-mentionedly, conductive pattern layer 126 is a re-wiring layer, and the first patterned layer P1 is connection pad (Pad), and the second patterned layer P2 is circuit (trace).
Thereafter can use film-type to glue brilliant glue-line, elargol or resin, is attached at the second surface S2 of semiconductor element 128d wherein on substrate 110.In addition, also can use then technology (SMT) of surface, on substrate 110, adhere to tin cream and make bump, carry out behind element location, then in the mode of reflow (Reflow), semiconductor element 128d is electrically connected on substrate 110.But, the present invention is not limited the mode of sticking of semiconductor element 128d.
Refer to Fig. 2 B, multiple insulating barriers 127 are adhered between each semiconductor element 128, insulating barrier 127 is disposed on the first surface S1 of semiconductor element 128 wherein, and be attached to the second surface S2 of second half conductor element 128, with superimposed each semiconductor element 128, and then form stacked structure 120.Specifically, sticking in the process of insulating barrier 127, first, insulating barrier 127 is configured on semiconductor element 128d, wherein on semiconductor element 128d, dispose conductive pattern layer 126, again semiconductor element 128c is disposed on the insulating barrier 127 being positioned on semiconductor element 128d, then again in the upper configuration of semiconductor element 128c insulating barrier 127.Form according to this, is all disposed at semiconductor element 128a, 128b, 128c and 128d on substrate 110.Then, carry out the flow process of pressing, semiconductor element 128 is bonded together making, and form stacked structure 120.It should be noted that insulating barrier 127 can be also sticky brilliant glue, and the present invention does not limit the method that forms stacked structure 120.
Then, refer to Fig. 2 C, shade 160 is covered on stacked structure 120.Shade 160 has multiple openings 162, and opening 162 can be arranged at end face and the side of shade 160.Opening 162 is in order to expose the conductive pattern layer 126 that is positioned at end face 122 and sidewall 124.What deserves to be explained is, the shape of these openings 162 is generally strip, and can consider and length, quantity and the distributing position of designed, designed opening 162 according to different electric connections, thereby can by the position of the exposed conductive pattern layer 126 of wish expose.For example, opening 162 can be the position that is extended to substrate 110 by the end face of shade 160, thereby expose the conductive pattern layer 126 of sidewall 124 and the connection pad of substrate 110 of stacked structure 120, or the end face of shade 160 can not be provided with any opening 162, and only form opening 162 in the side of shade.But, the present invention is not limited the design of opening 162.
Subsequently, form an electric conducting material on shade 160, and this electric conducting material is not only attached to the outer surface of shade 160, also can be attached on stacked structure 120 by the shape of opening 162, forms according to this conductive strips 130.Specifically,, by techniques such as spraying (Spraying), sputter (Sputtering), ion plating (IonPlating) or evaporations (Evaporation Deposition), electric conducting material is deposited on shade 160.
Refer to Fig. 2 D, take off shade 160, can on the end face of stacked structure 120 122 and sidewall 124, form conductive strips 130.Thickness that it should be noted that conductive strips 130 can be controlled according to the time length of deposits conductive material.In addition, the material of conductive strips 130 is metal, for example, be aluminium, copper or silver etc.But the present invention does not limit film plating process and the material of conductive strips 130.Via above-mentioned steps, stacked package part forms substantially.
Refer to Fig. 2 E, form mould sealing 140, it is covered on stacked structure 120, conductive strips 130 and substrate 110.The material of mould sealing 140 is selected to need to consider that thermal expansion is Number, the situation of buckling deformation is occurred to be reduced to substrate 110.Mould sealing 140 can be macromolecular material, for example epoxy mould envelope compound (Epoxy Molding Compound, EMC), polyimides (Polyimide, PI), phenolic resins (Phenolics) or silicones (Silicones) etc., and mould sealing 140 can utilize and shifts forming mode (transfer molding) and make.Specifically, first stacked package part is inserted in die cavity, the macromolecular material that wish is filled is after preheating cabinet thermoplastic, then the mode of utilizing pressurization to transmit makes the macromolecular material of melting state enter running channel (runner) and die cavity, is covered on stacked structure 120 through cooling slaking and folding glue rear mold sealing 140.In addition, mould sealing 140 can be also ceramic material, forms mould sealing 140 after sintering.But, the material to mould sealing 140 and production method are not limited in the present invention.
Please again consult Figure 1B, conductive layer 150 is formed on mould sealing 140.Conductive layer 150 can be metal material, and available spraying (spraying) or sputter (sputtering) mode are made on mould sealing 140.In addition, conductive layer 150 can be also conducting polymer composite.But, the material of conductive layer 150 and production method are only explanation, and non-limiting the present invention.
In sum, the embodiment of the present invention provides a kind of stacked package part with conductive strips, the variation of length, quantity and distributing position by conductive strips, makes conductive strips can serve as the electrically connect of stacked structure, and then simplifies encapsulating structure and manufacture method.Because conductive strips are disposed on the sidewall of stacked structure, and the conductive pattern layer that exposes of link and some of them sidewall, therefore semiconductor element is able to be electrically connected by conductive strips each other, and can simplify the process structure of encapsulation.
In addition, the embodiment of the present invention provides the formation method of stacked package part, by covering a shade with opening on stacked structure, deposit again an electric conducting material on described shade, and electric conducting material is able to form conductive strips on stacked structure by opening, therefore, can simplify the method flow of encapsulation.
The foregoing is only embodiments of the invention, it is not in order to limit scope of patent protection of the present invention.Any those of ordinary skills are not departing from spirit of the present invention and scope, and the change of doing and the equivalence of retouching are replaced, and are still within the scope of claim of the present invention.
Claims (14)
1. a stacked package part, is characterized in that, this stacked package part comprises:
Substrate;
Stacked structure, is positioned on this substrate, and this stacked structure has end face and multiaspect sidewall, and this stacked structure comprises multilayer conductive patterned layer, and described multiaspect sidewall exposes described multilayer conductive patterned layer; And
At least one conductive strips, are disposed at least one described sidewall, and described at least one conductive strips are electrically connected with at least two-layer described conductive pattern layer.
2. stacked package part as claimed in claim 1, it is characterized in that, this stacked structure also comprises multiple semiconductor elements, described multiple semiconductor element is laminated to each other side by side, and wherein described in one deck, conductive pattern layer is between adjacent two described semiconductor elements, and described at least one conductive strips are electrically connected wherein two described semiconductor elements.
3. stacked package part as claimed in claim 2, is characterized in that, this semiconductor element is wafer.
4. stacked package part as claimed in claim 2, is characterized in that, this semiconductor element is package module.
5. stacked package part as claimed in claim 1, is characterized in that, this conductive pattern layer is re-wiring layer.
6. stacked package part as claimed in claim 2, is characterized in that, this stacked structure also comprises multiple insulating barriers, and described in each, insulating barrier is wherein between adjacent two described semiconductor elements.
7. stacked package part as claimed in claim 1, is characterized in that, this stacked structure also comprises mould sealing, and this mould sealing covers this stacked structure and this conductive strips and is disposed on this substrate.
8. stacked package part as claimed in claim 7, is characterized in that, this stacked structure comprises conductive layer, and this conductive layer covers this mould sealing.
9. a manufacture method for stacked package part, is characterized in that, the manufacture method of this stacked package part comprises:
Form stacked structure on a substrate, this stacked structure has end face and multiaspect sidewall, and this stacked structure comprises multiple conductive pattern layer, and described multiaspect sidewall exposes described multiple conductive pattern layer; And
This stacked structure is carried out to patterned process, form according to this at least one conductive strips, described at least one conductive strips are positioned on described multiaspect sidewall and connect wherein at least two-layer described conductive pattern layer.
10. the manufacture method of stacked package part as claimed in claim 9, is characterized in that, forms the step of this stacked structure on this substrate and comprises:
Multiple semiconductor elements are provided, and described in each, semiconductor element has first surface and the second surface of this first surface relatively;
Multiple semiconductor elements described in rewiring, to form this conductive pattern layer of one deck on first surface described in each;
Described in each, on first surface, form protective layer, described multiple protective layers cover described multiple conductive pattern layer; And
Superimposed described multiple semiconductor elements, and wherein described in one this first surface of semiconductor element be positioned under the second surface of semiconductor element described in another, and described in each protective layer between two adjacent described semiconductor elements.
The manufacture method of 11. stacked package parts as claimed in claim 9, is characterized in that, the step of this stacked structure being carried out to patterned process comprises:
Cover shade on this stacked structure;
Deposits conductive material is on this shade; And
Remove this shade.
The manufacture method of 12. stacked package parts as claimed in claim 11, is characterized in that, this shade has multiple openings, and described multiple openings are in order to expose the described multiple conductive pattern layer of part that are positioned at this end face and this sidewall.
The manufacture method of 13. stacked package parts as claimed in claim 9, is characterized in that, the manufacture method of this stacked package part also comprises:
Form mould sealing, this mould sealing is covered in this stacked structure and this conductive strips.
The manufacture method of 14. stacked package parts as claimed in claim 13, is characterized in that, the manufacture method of this stacked package part also comprises:
Forming conductive layer is covered on this mould sealing.
Priority Applications (1)
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| CN201210554882.7A CN103887262A (en) | 2012-12-19 | 2012-12-19 | Stacked package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210554882.7A CN103887262A (en) | 2012-12-19 | 2012-12-19 | Stacked package and manufacturing method thereof |
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| CN103887262A true CN103887262A (en) | 2014-06-25 |
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| US7208343B2 (en) * | 2002-02-06 | 2007-04-24 | Samsung Electronics Co., Ltd. | Semiconductor chip, chip stack package and manufacturing method |
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| US20120115278A1 (en) * | 2007-10-16 | 2012-05-10 | Hynix Semiconductor Inc. | Stacked semiconductor package without reduction in data storage capacity and method for manufacturing the same |
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Application publication date: 20140625 |