CN103871465A - Nonvolatile memory and operating method thereof - Google Patents
Nonvolatile memory and operating method thereof Download PDFInfo
- Publication number
- CN103871465A CN103871465A CN201410097572.6A CN201410097572A CN103871465A CN 103871465 A CN103871465 A CN 103871465A CN 201410097572 A CN201410097572 A CN 201410097572A CN 103871465 A CN103871465 A CN 103871465A
- Authority
- CN
- China
- Prior art keywords
- nonvolatile memory
- threshold voltage
- drain electrode
- transistorized
- control gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a nonvolatile memory. The nonvolatile memory comprises a substrate, a floating gate, a control grid and a threshold voltage supplying unit, wherein a drain electrode is arranged in the substrate, the floating gate is arranged on the substrate at one side of the drain electrode, the control grid is arranged on the floating gate, the threshold voltage supplying unit is connected with the control grid and is provided with a transistor connected with at least one gate drain, and the threshold voltage supplying unit is used for providing threshold voltage of the transistor connected with at least one gate drain to the control grid. The invention also discloses an operating method of the nonvolatile memory. When the nonvolatile memory is read, the threshold voltage supplying unit provides the threshold voltage of the transistor connected with at least one gate drain to the control grid, the change of the threshold voltage of the transistor connected with the gate drain can justly compensate the change of conductive voltage between the drain electrode and the floating gate, and the temperature influence is avoided.
Description
Technical field
The present invention relates to memory technology field, particularly relate to a kind of nonvolatile memory and method of operating thereof.
Background technology
Integrated circuit technique has developed rapidly since the forties in last century, has greatly improved people's life.Moore's Law points out, along with the progress of technological level, transistor size that can be integrated on monolithic integrated optical circuit approximately increases by four times in every 3 years.
Storer is an important branch of integrated circuit, is the core cell of all electronic systems.Semiconductor memory is divided into volatile storage and non-volatility memorizer two classes, and both differences are to remove loss of data in volatile storage after supply voltage, and in non-volatility memorizer, data still can keep.Non-volatility memorizer has polytype, as ultraviolet erasing programmable storage, EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read Only Memory is called for short EEPROM) and flash memory etc.Compared with other types non-volatility memorizer, EEPROM has the following advantages: the granularity of well programming, very little power consumption, allows a large amount of storage unit simultaneously erasable to reduce the test duration, erasable often etc.So, EEPROM be more suitable for being used in non-volatility memorizer capacity requirement little, require the little and erasable occasion often of circuit power consumption, such as cell phone, automobile, computer communication product and consumer electronics product etc.
Fig. 1 is the array junctions composition of EEPROM (Electrically Erasable Programmable Read Only Memo) in prior art.As shown in Figure 1, the array of EEPROM (Electrically Erasable Programmable Read Only Memo) comprises:
Multirow and multiple row storage unit (as C1);
Multiple word lines (WL<0>～WL<n>), it is coupled to multirow storage unit, the strobe case of the each line storage unit of word line voltage control providing by pre-charge circuit is provided with the grid of each storage unit;
Multiple bit lines (BL<0>～BL<k>), it is coupled to multiple row storage unit, be connected with the active electrode (S/D) of each memory cell, by controlling programming and the read-write motion of the each array storage unit of Control of Voltage of adjacent two bit lines.
Fig. 2 is the schematic diagram of storage unit C1 in Fig. 1.As shown in Figure 2, storage unit C1 is positioned in Semiconductor substrate 10, storage unit C1 has: with bit line 30(BL<0>) drain electrode 11 that links together, the selection grid 40 that link together with word line WL<1>, for storing floating boom 21 and the control gate 22 of data, selecting has insulant 50 intervals between grid 40 and floating boom 21 and control gate 22.Storage unit C1 is in programming process, and electronics 11 enters floating boom 21 from draining; Storage unit C1 is in erase process, and electronics enters and selects grid 40 from floating boom 21, thereby flows out from word line WL<1>.
General, storage unit C1 is reading in (Read) process, need be at the voltage of selecting to apply on grid 40 2.5V left and right, select conducting between grid 40 and substrate 10, and on control gate 22, apply a lower voltage (being generally 0.5V～5V), make to drain 11 and floating boom 21 between conducting, thereby read in floating boom 21 data of storage.But, because drain electrode 11 and the forward voltage between floating boom 21 are subject to the impact of temperature, so, in the time of temperature variation, drain 11 and floating boom 21 between conducting all arrive impact, there is unreliability; And the power consumption of whole storer is larger.
Summary of the invention
The object of the invention is to, a kind of nonvolatile memory and method of operating thereof are provided, can reduce or avoid the impact of temperature, and reduce the power consumption of nonvolatile memory.
For solving the problems of the technologies described above, the invention provides a kind of nonvolatile memory, described nonvolatile memory comprises:
Substrate, has drain electrode in described substrate;
Floating boom, is arranged on the described substrate of described drain electrode one side;
Control gate, is arranged on described floating boom;
Threshold voltage provides unit, is connected with described control gate, and described threshold voltage provides unit to have the transistor that at least one Gate leakage connects, and described threshold voltage provides unit for provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate.
Further, in described nonvolatile memory, described threshold voltage provides unit to comprise a transistor, described transistorized grid is connected with drain electrode, described transistorized source ground, provide a forward current to described transistorized drain electrode, described transistorized drain electrode connects described control gate, for described control gate provides described transistorized threshold voltage.
Further, in described nonvolatile memory, described threshold voltage provides unit to comprise multi-level transistor, every grade of described transistorized grid is connected with the described transistorized drain electrode of the corresponding levels, described in next stage, transistorized drain electrode is connected with transistorized source series described in upper level, transistorized source ground described in afterbody, provide a forward current to transistorized drain electrode described in the first order, described in the first order, transistorized drain electrode connects described control gate, for described control gate provides multistage described transistorized threshold voltage.
Further, in described nonvolatile memory, described nonvolatile memory is EEPROM (Electrically Erasable Programmable Read Only Memo), and described EEPROM (Electrically Erasable Programmable Read Only Memo) also comprises selection grid, and described selection grid are arranged on the described substrate that described floating boom deviates from described drain electrode one side.
Further, in described nonvolatile memory, between described selection grid and substrate, have an insulation course, the thickness of described insulation course is
Further, in described nonvolatile memory, described EEPROM (Electrically Erasable Programmable Read Only Memo) is two floating booms, two control gate structure.
According to another side of the present invention, the present invention also provides a kind of method of operating of nonvolatile memory, and described in it, nonvolatile memory is described above any one nonvolatile memory, and the method for operating of described nonvolatile memory comprises:
When described nonvolatile memory is carried out to read operation, described threshold voltage provides unit to provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate.
Further, in the method for operating of described nonvolatile memory, the method for operating of described nonvolatile memory also comprises, when described nonvolatile memory is carried out to erase operation:
Apply the first voltage to described drain electrode, apply second voltage to described control gate, wherein, described the first voltage is greater than described second voltage, and the electronics being stored in described floating boom flows into described drain electrode.
Further, in the method for operating of described nonvolatile memory, the span of described the first voltage is 3V～10V.
Further, in the method for operating of described nonvolatile memory, the span of described second voltage is-2V～-10V.
Compared with prior art, the method for operating of EEPROM (Electrically Erasable Programmable Read Only Memo) provided by the invention and storer have the following advantages:
In nonvolatile memory provided by the invention and method of operating thereof, described nonvolatile memory comprises: substrate, has drain electrode in described substrate; Floating boom, is arranged on the described substrate of described drain electrode one side; Control gate, is arranged on described floating boom; Threshold voltage provides unit, is connected with described control gate, and described threshold voltage provides unit to have the transistor that at least one Gate leakage connects, and described threshold voltage provides unit for provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate.Compared with prior art, described Gate leaks the inverse ratio that is varied to of the transistorized threshold voltage that connects and temperature, and between described drain electrode and floating boom, forward voltage and temperature variation are also inversely proportional to, in the time of temperature variation, between the variation that described Gate leaks the transistorized threshold voltage connecting and described drain electrode and floating boom, the variation of forward voltage is consistent, in the time that described nonvolatile memory is carried out to read operation, described threshold voltage provides unit to provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate, the variation of the transistorized threshold voltage that described Gate leakage connects just in time can compensate the variation of forward voltage between described drain electrode and floating boom, thereby avoid the impact of temperature.
Further, described nonvolatile memory is EEPROM (Electrically Erasable Programmable Read Only Memo), described EEPROM (Electrically Erasable Programmable Read Only Memo) also comprises selection grid, described selection grid are arranged on the described substrate that described floating boom deviates from described drain electrode one side, between described selection grid and substrate, have an insulation course, the thickness of described insulation course is
the thickness of described insulation course is less, and the forward voltage between described selection grid and substrate is reduced, thereby reduces the power consumption of whole storer.
Accompanying drawing explanation
Fig. 1 is the array junctions composition of EEPROM (Electrically Erasable Programmable Read Only Memo) in prior art;
Fig. 2 is the schematic diagram of storage unit in Fig. 1;
Fig. 3 is the structural drawing of nonvolatile memory in one embodiment of the invention;
Fig. 4 provides the structural drawing of unit for threshold voltage in one embodiment of the invention;
Fig. 5 provides the structural drawing of unit for threshold voltage in another embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, nonvolatile memory of the present invention and method of operating thereof are described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of nonvolatile memory is provided, and described nonvolatile memory comprises: substrate, has drain electrode in described substrate; Floating boom, is arranged on the described substrate of described drain electrode one side; Control gate, is arranged on described floating boom; Threshold voltage provides unit, is connected with described control gate, and described threshold voltage provides unit to have the transistor that at least one Gate leakage connects, and described threshold voltage provides unit for provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate.Compared with prior art, described Gate leaks the inverse ratio that is varied to of the transistorized threshold voltage that connects and temperature, and between described drain electrode and floating boom, forward voltage and temperature variation are also inversely proportional to, in the time of temperature variation, between the variation that described Gate leaks the transistorized threshold voltage connecting and described drain electrode and floating boom, the variation of forward voltage is consistent, in the time that described nonvolatile memory is carried out to read operation, described threshold voltage provides unit to provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate, the variation of the transistorized threshold voltage that described Gate leakage connects just in time can compensate the variation of forward voltage between described drain electrode and floating boom, thereby avoid the impact of temperature.
Below in conjunction with specific embodiment, core concept of the present invention is described.Preferably, in the present embodiment, described nonvolatile memory is EEPROM (Electrically Erasable Programmable Read Only Memo), and described EEPROM (Electrically Erasable Programmable Read Only Memo) is two floating booms, two control gate structure.
Fig. 3 is the structural drawing of nonvolatile memory in one embodiment of the invention.Fig. 3 illustrates a storage unit of described EEPROM (Electrically Erasable Programmable Read Only Memo), and described storage unit comprises that 500,600, two storing sub-units 500,600 of two storing sub-units can store two separate bytes.Described EEPROM (Electrically Erasable Programmable Read Only Memo) comprises: substrate 100, has drain electrode 110/120 in described substrate 100; Floating boom 520/620 is arranged on the described substrate 100 of described drain electrode 1,10/,120 1 sides; Control gate 510/610 is arranged on described floating boom 520/620; Select grid 400 to be arranged on the described substrate 100 that described floating boom 520/620 deviates from described drain electrode 100 1 sides, in the present embodiment, because described EEPROM (Electrically Erasable Programmable Read Only Memo) is two floating booms, two control gate structure, so described selection grid 400 are arranged between described floating boom 520/620.Threshold voltage provides unit 900 to be connected with described control gate 510/610, described threshold voltage provides unit 900 to have the transistor that at least one Gate leakage connects, and described threshold voltage provides unit 900 for provide described at least one Gate to leak the transistorized threshold voltage vt connecting to described control gate 510/610.
Wherein, have an insulation course 700 between described selection grid 400 and substrate 100, preferably, the thickness of described insulation course 700 is
make the thickness of described insulation course 700 less, the forward voltage between described selection grid 400 and substrate 100 is reduced, thereby reduce the power consumption of whole described EEPROM (Electrically Erasable Programmable Read Only Memo).
As shown in Figure 4, in an embodiment of the present invention, described threshold voltage provides unit 900 to comprise a transistor 910, and the grid S of described transistor 910 is connected with drain D, the source S ground connection of described transistor 910, provides a forward current ID to the drain D of described transistor 910.Preferably, provide a forward current ID by a current source 920 to the drain D of described transistor 910, wherein, described forward current ID is about 1mA～10mA, but described forward current ID is not limited to as 1mA～10mA, as long as can make the drain D of described transistor 910 that the threshold voltage vt of described transistor 910 can be provided, also within thought range of the present invention.The drain D of described transistor 910 connects described control gate 510/610, for described control gate 510/610 provides the threshold voltage vt of described transistor 910.Wherein, in the present embodiment, the threshold voltage vt of described transistor 910 is about 0.7V, and, described threshold voltage provides unit 900 to provide to described control gate 510/610 threshold voltage that is about 0.7V.
As shown in Figure 5, in another embodiment of the present invention, described threshold voltage provides unit 900 ' to comprise multi-level transistor 910, for example, comprise 2 grades, 3 grades, 4 grades of transistors 910 etc., the grid G of every grade of described transistor 910 is connected with the drain D of the described transistor 910 of the corresponding levels, described in next stage, described in the drain D of transistor 910 and upper level, the source S of transistor 910 is connected in series, the source S ground connection of transistor 910 described in afterbody, provides a forward current ID to the drain D of transistor described in the first order 910.Preferably, provide a forward current ID by a current source 920 to the drain D of described transistor 910, wherein, described forward current ID is about 1mA～10mA, but described forward current ID is not limited to as 1mA～10mA, as long as can make the drain D of described transistor 910 that the threshold voltage vt of described transistor 910 can be provided, also within thought range of the present invention.Described in the first order, the drain D of transistor 910 connects described control gate 510/610, for described control gate 510/610 provides the threshold voltage vt of multistage described transistor 910.In the present embodiment, described threshold voltage provides unit 900 ' to comprise 2 grades of transistors 910, the threshold voltage vt of every one-level transistor 910 ' be about 0.7V,, described threshold voltage provides unit 900 that the threshold voltage vt (i.e. two threshold voltage vts ' sum) that is about 1.4V is provided to described control gate 510/610.Wherein, the progression of described transistor 910 can arrange according to the need of threshold voltage vt, in the time that needs provide the threshold voltage vt that is about 2.1V, 3 grades of transistors 910 is set, by that analogy.
When described EEPROM (Electrically Erasable Programmable Read Only Memo) is carried out read operation, described threshold voltage provides unit 900 to provide described at least one Gate to leak the transistorized threshold voltage vt connecting to described control gate 510/610, simultaneously, apply the voltage of 1V～2V to described selection grid 400, apply the voltage of 1V～2V to described drain electrode 110, apply induction current (common practise of this area) to described drain electrode 120, can read two storing sub-units 500,600 simultaneously.Because the thickness of described insulation course 700 is less, apply the voltage of 1V～2V to described selection grid 400, can make conducting between described selection grid 400 and substrate 100, thereby reduce the power consumption of whole described EEPROM (Electrically Erasable Programmable Read Only Memo), and can reduce the setting of 2.5V charge pump.
Because described Gate leaks the inverse ratio that is varied to of the transistorized threshold voltage vt that connects and temperature, and between described drain electrode 110/120 and floating boom 520/620, forward voltage and temperature variation are also inversely proportional to, in the time of temperature variation, between the variation that described Gate leaks the transistorized threshold voltage vt connecting and described drain electrode 110/120 and floating boom 520/620, the variation of forward voltage is consistent, in the time that described nonvolatile memory is carried out to read operation, described threshold voltage provides unit 900 to provide described at least one Gate to leak the transistorized threshold voltage vt connecting to described control gate 510/520, the variation of the transistorized threshold voltage vt that described Gate leakage connects just in time can compensate the variation of forward voltage between described drain electrode 110/120 and floating boom 520/620, thereby avoid the impact of temperature.
Preferably, when described EEPROM (Electrically Erasable Programmable Read Only Memo) is carried out to erase operation: apply the first voltage to described drain electrode 110/120, apply second voltage to described control gate 510/520, wherein, described the first voltage is greater than described second voltage, makes the electronics being stored in described floating boom 520/620 flow into described drain electrode.Meanwhile, can also on described selection grid 400, apply tertiary voltage, general, the magnitude of voltage of tertiary voltage is between described the first voltage and second voltage.Thereby, between the drain electrode 110/120 of described storing sub-units and control gate 510/520, form a higher voltage difference, between the drain electrode 110/120 of described storing sub-units and control gate 510/520, form FN tunneling effect, the electronics of storing in the floating boom 520/620 of described storing sub-units is flowed out from the drain electrode 110/120 of described storing sub-units, thereby EEPROM (Electrically Erasable Programmable Read Only Memo) is carried out to erase operation, adopt the EEPROM (Electrically Erasable Programmable Read Only Memo) of this method of operating without between the described storing sub-units of same a line, switch element being set, can realize the erase operation of described storing sub-units, and unaffected with storing sub-units described in other of a line, thereby save the area of EEPROM (Electrically Erasable Programmable Read Only Memo).
Preferably, the span of described the first voltage is 3V～10V, as 4V, 5V, 6V, 7V, 8V, 9V etc., the span of described second voltage is-2V～-10V, as-3V ,-9V ,-5V ,-6V ,-7V ,-8V ,-9V etc., but the span of described the first voltage and second voltage is not limited to above-mentioned scope, as long as described the first voltage is greater than described second voltage, also within thought range of the present invention.
Certainly, described nonvolatile memory and method of operating thereof are not limited to above-described embodiment, for example, described EEPROM (Electrically Erasable Programmable Read Only Memo) is not limited to as two floating booms, two control gate structure, and described nonvolatile memory is not limited to as EEPROM (Electrically Erasable Programmable Read Only Memo), according to foregoing description of the present invention, those having ordinary skill in the art will appreciate that, also within thought range of the present invention.
In sum, the invention provides a kind of nonvolatile memory and method of operating thereof, described nonvolatile memory comprises: substrate, has drain electrode in described substrate; Floating boom, is arranged on the described substrate of described drain electrode one side; Control gate, is arranged on described floating boom; Threshold voltage provides unit, is connected with described control gate, and described threshold voltage provides unit to have the transistor that at least one Gate leakage connects, and described threshold voltage provides unit for provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate.Compared with prior art, provided by the inventionly contain nonvolatile memory and method of operating has the following advantages:
Described Gate leaks the inverse ratio that is varied to of the transistorized threshold voltage that connects and temperature, and between described drain electrode and floating boom, forward voltage and temperature variation are also inversely proportional to, in the time of temperature variation, between the variation that described Gate leaks the transistorized threshold voltage connecting and described drain electrode and floating boom, the variation of forward voltage is consistent, in the time that described nonvolatile memory is carried out to read operation, described threshold voltage provides unit to provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate, the variation of the transistorized threshold voltage that described Gate leakage connects just in time can compensate the variation of forward voltage between described drain electrode and floating boom, thereby avoid the impact of temperature.
Further, described nonvolatile memory is EEPROM (Electrically Erasable Programmable Read Only Memo), described EEPROM (Electrically Erasable Programmable Read Only Memo) also comprises selection grid, described selection grid are arranged on the described substrate that described floating boom deviates from described drain electrode one side, between described selection grid and substrate, have an insulation course, the thickness of described insulation course is
the thickness of described insulation course is less, and the forward voltage between described selection grid and substrate is reduced, thereby reduces the power consumption of whole storer.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. a nonvolatile memory, is characterized in that, described nonvolatile memory comprises:
Substrate, has drain electrode in described substrate;
Floating boom, is arranged on the described substrate of described drain electrode one side;
Control gate, is arranged on described floating boom;
Threshold voltage provides unit, is connected with described control gate, and described threshold voltage provides unit to have the transistor that at least one Gate leakage connects, and described threshold voltage provides unit for provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate.
2. nonvolatile memory as claimed in claim 1, it is characterized in that, described threshold voltage provides unit to comprise a transistor, described transistorized grid is connected with drain electrode, described transistorized source ground, provide a forward current to described transistorized drain electrode, described transistorized drain electrode connects described control gate, for described control gate provides described transistorized threshold voltage.
3. nonvolatile memory as claimed in claim 1, it is characterized in that, described threshold voltage provides unit to comprise multi-level transistor, every grade of described transistorized grid is connected with the described transistorized drain electrode of the corresponding levels, described in next stage, transistorized drain electrode is connected with transistorized source series described in upper level, transistorized source ground described in afterbody, provide a forward current to transistorized drain electrode described in the first order, described in the first order, transistorized drain electrode connects described control gate, for described control gate provides multistage described transistorized threshold voltage.
4. nonvolatile memory as claimed in claim 1, it is characterized in that, described nonvolatile memory is EEPROM (Electrically Erasable Programmable Read Only Memo), described EEPROM (Electrically Erasable Programmable Read Only Memo) also comprises selection grid, and described selection grid are arranged on the described substrate that described floating boom deviates from described drain electrode one side.
5. nonvolatile memory as claimed in claim 4, is characterized in that, between described selection grid and substrate, has an insulation course, and the thickness of described insulation course is
6. nonvolatile memory as claimed in claim 4, is characterized in that, described EEPROM (Electrically Erasable Programmable Read Only Memo) is two floating booms, two control gate structure.
7. a method of operating for nonvolatile memory, is characterized in that, described nonvolatile memory is the nonvolatile memory as described in any one in claim 1-6, and the method for operating of described nonvolatile memory comprises:
When described nonvolatile memory is carried out to read operation, described threshold voltage provides unit to provide described at least one Gate to leak the transistorized threshold voltage connecting to described control gate.
8. the method for operating of nonvolatile memory as claimed in claim 7, is characterized in that, the method for operating of described nonvolatile memory also comprises, when described nonvolatile memory is carried out to erase operation:
Apply the first voltage to described drain electrode, apply second voltage to described control gate, wherein, described the first voltage is greater than described second voltage, and the electronics being stored in described floating boom flows into described drain electrode.
9. the method for operating of nonvolatile memory as claimed in claim 8, is characterized in that, the span of described the first voltage is 3V～10V.
10. the method for operating of nonvolatile memory as claimed in claim 8, is characterized in that, the span of described second voltage is-2V～-10V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410097572.6A CN103871465A (en) | 2014-03-17 | 2014-03-17 | Nonvolatile memory and operating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410097572.6A CN103871465A (en) | 2014-03-17 | 2014-03-17 | Nonvolatile memory and operating method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103871465A true CN103871465A (en) | 2014-06-18 |
Family
ID=50909912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410097572.6A Pending CN103871465A (en) | 2014-03-17 | 2014-03-17 | Nonvolatile memory and operating method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103871465A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108777581A (en) * | 2018-08-02 | 2018-11-09 | 北京知存科技有限公司 | A kind of D/A conversion circuit, control method, storage device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6556068B2 (en) * | 1998-02-26 | 2003-04-29 | Micron Technology, Inc. | Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits |
| CN101276228A (en) * | 2007-03-28 | 2008-10-01 | 株式会社瑞萨科技 | Semiconductor device generating voltage for temperature compensation |
| CN100490157C (en) * | 2001-11-02 | 2009-05-20 | 桑迪士克股份有限公司 | Non-volatile memory for reading data with temperature-compensated function |
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
| US20090175079A1 (en) * | 2006-06-07 | 2009-07-09 | Lee Wang | Structures and methods to store information representable by a multiple-bit binary word in electrically erasable, programmable read-only memory (eeprom) |
| CN101740120A (en) * | 2009-11-10 | 2010-06-16 | 上海宏力半导体制造有限公司 | Programming method for shared-word line split-gate type flash memory |
| CN101752385A (en) * | 2008-12-03 | 2010-06-23 | 超捷公司 | Non-volatile memory cell with buried select gate and method for producing the same |
| JP2010176258A (en) * | 2009-01-28 | 2010-08-12 | Hitachi Ulsi Systems Co Ltd | Voltage generation circuit |
| CN101853704A (en) * | 2010-05-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Erasing method of split-gate flash memory of shared word line |
| CN101986389A (en) * | 2010-10-12 | 2011-03-16 | 上海宏力半导体制造有限公司 | Flash memory unit, flash memory device and programming method thereof |
-
2014
- 2014-03-17 CN CN201410097572.6A patent/CN103871465A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6556068B2 (en) * | 1998-02-26 | 2003-04-29 | Micron Technology, Inc. | Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits |
| CN100490157C (en) * | 2001-11-02 | 2009-05-20 | 桑迪士克股份有限公司 | Non-volatile memory for reading data with temperature-compensated function |
| US20090175079A1 (en) * | 2006-06-07 | 2009-07-09 | Lee Wang | Structures and methods to store information representable by a multiple-bit binary word in electrically erasable, programmable read-only memory (eeprom) |
| CN101276228A (en) * | 2007-03-28 | 2008-10-01 | 株式会社瑞萨科技 | Semiconductor device generating voltage for temperature compensation |
| CN101752385A (en) * | 2008-12-03 | 2010-06-23 | 超捷公司 | Non-volatile memory cell with buried select gate and method for producing the same |
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
| JP2010176258A (en) * | 2009-01-28 | 2010-08-12 | Hitachi Ulsi Systems Co Ltd | Voltage generation circuit |
| CN101740120A (en) * | 2009-11-10 | 2010-06-16 | 上海宏力半导体制造有限公司 | Programming method for shared-word line split-gate type flash memory |
| CN101853704A (en) * | 2010-05-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Erasing method of split-gate flash memory of shared word line |
| CN101986389A (en) * | 2010-10-12 | 2011-03-16 | 上海宏力半导体制造有限公司 | Flash memory unit, flash memory device and programming method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108777581A (en) * | 2018-08-02 | 2018-11-09 | 北京知存科技有限公司 | A kind of D/A conversion circuit, control method, storage device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10381086B2 (en) | Multiple blocks per string in 3D NAND memory | |
| US7663932B2 (en) | Nonvolatile semiconductor memory device | |
| US9053807B2 (en) | Non-volatile semiconductor memory device | |
| CN101441892B (en) | Method of operating a flash memory device | |
| US20150348621A1 (en) | Nonvolatile semiconductor memory device and read method thereof | |
| US8995188B2 (en) | Sharing support circuitry in a memory | |
| US20140043906A1 (en) | Semiconductor memory devices | |
| US20160019971A1 (en) | Nonvolatile semiconductor memory device and method of controlling the same | |
| CN107204203B (en) | Memory array and reading, programming and erasing operation method thereof | |
| JP2008090997A (en) | Flash memory element and programming method thereof | |
| CN103700399A (en) | Flash memory and corresponding programming method, reading method and erasing method | |
| CN105006247A (en) | High voltage switch circuit and nonvolatile memory including the same | |
| JP6874269B2 (en) | Leakage current reduction in 3D NAND memory | |
| US20120243328A1 (en) | Nonvolatile semiconductor memory device and data erase method of the same | |
| US20140355346A1 (en) | Nonvolatile memory device | |
| CN104183274A (en) | Storage unit and storage array erasing method | |
| CN103839586A (en) | Method for regulating erasing voltage of nonvolatile memory | |
| CN103871465A (en) | Nonvolatile memory and operating method thereof | |
| US9349481B2 (en) | Semiconductor memory device and method of operating the same | |
| US8867277B2 (en) | Nonvolatile semiconductor memory device | |
| CN107799146B (en) | Memory array and reading, programming and erasing operation method thereof | |
| CN103839587A (en) | Electric erasable programmable read-only memory and operating method | |
| US9153326B2 (en) | Nonvolatile semiconductor memory device and method of controlling same | |
| US8300469B2 (en) | Cost saving electrically-erasable-programmable read-only memory (EEPROM) array | |
| CN108346448A (en) | Flash memories and its control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140618 |