CN103823447B - The communication method of the upper and lower computer of semiconductor devices and communication system - Google Patents
The communication method of the upper and lower computer of semiconductor devices and communication system Download PDFInfo
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- CN103823447B CN103823447B CN201410076579.XA CN201410076579A CN103823447B CN 103823447 B CN103823447 B CN 103823447B CN 201410076579 A CN201410076579 A CN 201410076579A CN 103823447 B CN103823447 B CN 103823447B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The present invention discloses the communication system of semiconductor devices upper and lower computer, and wherein said lower computer comprises the command reception register for receiving upper computer instruction; For receive from described command reception register instruction with drive semiconductor devices topworks perform corresponding actions action executing register; For configuring the zone bit configuration module of working order zone bit, wherein working order zone bit represents the working order of described topworks; And for reading and receive register by the instruction of reception write or the control module not writing action executing register according to described working order zone bit steering order. Present invention also offers a kind of communication method, it is possible to improve the safety and reliability of equipment.
Description
Technical field
The present invention relates to the communications field, in particular to the communication method between the upper and lower computer of a kind of semiconductor devices.
Background technology
Current most of domestic semiconductor devices adopts the control framework of " host computer PC+lower computer ". Wherein the interactive communication of upper computer and lower computer is that steering order is passed on to lower computer by the method writing value to lower computer storer by upper computer, by the action of lower computer Direct driver topworks. The status feedback signal such as sensor are then gather by lower computer and be stored into corresponding registers, regularly obtain by reading these registers by upper computer.
But, adopt the shortcoming of this kind of communication method to be: first, upper computer needs to take ample resources and regularly reads the feedback signal in register; Secondly, regular reading machine system causes feedback information acquisition delayed; In addition, action instruction is written to lower computer register by upper computer, and lower computer directly drives topworks's action to there is potential safety hazard by the value of this register, reduces the safety and reliability of equipment.
The method therefore, it is necessary to the upper and lower computer proposing a kind of reliability that can save upper computer memory source, the raising response speed of topworks with sensor feedback and raising equipment communicates.
Summary of the invention
The main purpose of the present invention aims to provide the communication system of a kind of semiconductor devices upper and lower computer and the method for communicating, to improve above-mentioned defect.
For reaching above-mentioned purpose, the present invention provides the communication system of a kind of semiconductor devices upper and lower computer, comprises upper computer and lower computer, wherein, described upper computer writes instruction to described lower computer, and described lower computer sends the state feedback information of the topworks of semiconductor devices to described upper computer. Described lower computer comprises command reception register, for receiving the instruction that described upper computer writes; Action executing register, for receive from described command reception register instruction with drive described semiconductor devices topworks perform corresponding actions; Zone bit configuration module, for configuring working order zone bit, described working order zone bit represents the working order of described topworks; And control module, for reading and control, according to described working order zone bit, instruction write that described command reception register received or do not write described action executing register.
Preferably, when the described working order zone bit that described control module reads is the first zone bit, it controls described command reception register and the instruction of reception writes described action executing register, described first zone bit is changed to the 2nd zone bit simultaneously; When the described working order zone bit that described control module reads is described 2nd zone bit, it controls described command reception register and the instruction received is reset; Wherein said first zone bit represents that the working order of described topworks is for idle, and described 2nd zone bit represents that the working order of described topworks is in work.
Preferably, when the action of described topworks completes, described 2nd zone bit is changed to described first zone bit by described control module, is reset by described action executing register simultaneously.
Preferably, described lower computer also comprises interim status register and feedback states register, the state feedback information that wherein said interim status register gathers for upgrading described lower computer; When described control module judges that described feedback states register is different with the state feedback information in interim status register, give described feedback states register by the state feedback information that described interim status register upgrades; The state feedback information that described feedback states register is endowed is sent to described upper computer.
Preferably, during described lower computer initialize, described feedback states register is reset by described control module.
Preferably, the data frame head character of described state feedback information is for defining the type of this state feedback information, and described state feedback information is resolved by described upper computer according to described data frame head character.
Present invention also offers the communicate method of a kind of semiconductor devices upper computer with lower computer, comprise and write described instruction by described upper computer to the command reception register of described lower computer; And determine whether the instruction that described command reception register module receives is write described action executing register according to described working order zone bit.
Preferably, when described working order zone bit is the first zone bit, the instruction that described command reception register receives is write described action executing register, described first zone bit is changed to the 2nd zone bit simultaneously; When described working order zone bit is the 2nd zone bit, the instruction received by described command reception register resets; Wherein said first zone bit represents that the working order of described topworks is for idle, and described 2nd zone bit represents that the working order of described topworks is in work.
Preferably, when the action of described topworks completes, described 2nd zone bit is changed to described first zone bit, described action executing register is reset simultaneously.
Preferably, described communication method also comprises the state feedback information that described lower computer gathers is updated to described interim status register; Judge that whether described feedback states register is identical with the state feedback information in interim status register; If not identical, then the state feedback information that described interim status register upgrades is given described feedback states register send to described upper computer.
Preferably, before the state feedback information that described lower computer gathers is updated to described interim status register, also comprise lower computer described in initialize and by described feedback states register reset step.
Preferably, described state feedback information is resolved by the data frame head character of the state feedback information that described upper computer receives according to it, the type of wherein said data frame head this state feedback information of character definition.
The communication system of semiconductor devices upper and lower computer proposed by the invention and method, it is possible to effectively avoid topworks's instruction that performs an action chaotic and cause equipment and personal injury, it is to increase the safety and reliability of equipment; In addition the memory source of upper computer can also effectively be saved, the process of the status feedback signal such as sensor is also efficient more in time.
Accompanying drawing explanation
Fig. 1 is the functional diagram of the communication system of the semiconductor devices upper and lower computer of one embodiment of the invention;
Fig. 2 is the schema of upper computer to lower computer transmission instruction of semiconductor devices of the present invention;
Fig. 3 is the functional diagram of the communication system of the semiconductor devices upper and lower computer of another embodiment of the present invention;
Fig. 4 is the schema of lower computer to upper computer transmission state feedback information of semiconductor devices of the present invention.
Embodiment
For making the content of the present invention clearly understandable, below in conjunction with Figure of description, the content of the present invention is described further. Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Fig. 1 is the functional diagram of the communication system of semiconductor devices upper and lower computer of the present invention. The communication system of semiconductor devices upper and lower computer comprises upper computer 10 and lower computer 20, and instruction is sent to lower computer 20 by upper computer 10, drives the topworks 30 of semiconductor devices to perform corresponding actions by lower computer 20. Wherein, lower computer 20 comprises command reception register (D1) 21, action executing register (D2) 22, control module 23 and zone bit configuration module 24. Wherein, the instruction that command reception register 21 writes for receiving upper computer 10; Action executing register 22 is connected with command reception register 21, and for receiving the instruction from command reception register 21, to drive, the topworks 30 of semiconductor devices performs corresponding actions; The working order zone bit X of the working order that zone bit configuration module 24 represents topworks for configuring, and there is corresponding relation in the value of working order zone bit X and action executing register 22, as in the present embodiment when the working order of topworks 30 is idle, working order zone bit X=Free, the value in action executing register 22 is 0; When the working order of topworks 30 is in work, then working order zone bit X=Busy, the value in action executing register 22 is not 0; Control module 23 is connected with command reception register 21 with zone bit configuration module 24, for read work state flag bit X, and receive whether register 21 writes action executing register 22 to pass on to topworks 30 by the instruction of reception according to working order zone bit X steering order.
Fig. 2 be semiconductor devices upper computer to lower computer send instruction schema, below with reference to Fig. 1 with Fig. 2, the method for communicating of the semiconductor devices upper and lower computer of first embodiment of the invention is described.
First, after instruction code is written to the command reception register D1 of lower computer by upper computer, control module 23 read work state flag bit X, if working order zone bit X=Free, then illustrate that topworks 30 is in the free time, control module 23 steering order receives register D1 and instruction code is written to topworks action register D2, topworks's action register 22 can drive topworks 30 to carry out action corresponding to this instruction, and the working order zone bit X in zone bit configuration module 24 is changed to X=Busy by control module 23 simultaneously. Until after the action executing of topworks 30 terminates, the value in topworks action register D2 is reset by control module 23, working order zone bit X is recovered as X=Free simultaneously. Carry out the write of instruction again of upper computer afterwards again.
On the other hand, if working order zone bit X=Busy, illustrate that now topworks is still performing an action, then the value in upper computer command reception register D1 is reset by control module, again writes instruction by upper computer, carries out the judgement of working order zone bit. Until after action executing terminates by topworks 30, working order zone bit just is recovered to be reset by action executing register D2 for X=Free by control module 23 simultaneously. Hereafter the instruction that command reception register D1 receives can write action executing register D2, drives topworks 30 to carry out next step action.
As known from the above, sent the method for instruction to lower computer by above-mentioned upper computer, by command reception register and action executing register are separated, when topworks is still when carrying out action executing, the instruction that upper computer sends can not be sent to action executing register, therefore the equipment that can effectively avoid topworks to perform chaotic action instruction and to cause and personal injury, it is to increase the safety and reliability of equipment.
In another better embodiment of the present invention, lower computer also initiatively can send the state feedback information such as sensor to upper computer. Fig. 3 and Fig. 4 is that the communication system functional diagram of the present embodiment and lower computer send the schema of state feedback information to upper computer.
As shown in Figure 3, lower computer also comprises feedback states register (D3) 25 and interim status register (D4) 26 (command reception register D1, action executing register D2 and zone bit configuration module etc. in Fig. 1 do not illustrate). The state feedback information that wherein interim status register 26 gathers for upgrading lower computer; Control module is connected with feedback states register 25 with interim status register 26, and it judges that the state feedback information in two registers is as, time different, the state feedback information upgraded by interim status register 26 gives feedback states register 25. The state feedback information that feedback states register 25 is endowed is sent to upper computer.
Specifically, as shown in Figure 4, lower computer utilizes the communication instruction carried initiatively to send state feedback information to upper computer, the method that its " initiatively " sends is as follows: first reset by feedback states register D3 when lower computer initialize, and the state feedback information collected is updated in interim status register D4. Then judge that whether the value in feedback states register D3 and interim status register D4 is equal, if the value in D3 and D4 is inequal, then the value in interim status register D4 is assigned to feedback states register D3, performs once " initiatively " transmission by feedback states register D3 simultaneously and state feedback information is sent to upper computer. It is then processed by upper computer by event trigger mechanism. If the value in D3 and D4 is equal, then description status feedback information does not change, then lower computer continues to be updated to the state feedback information collected interim status register D4, and if judging that whether the value in D3 and D4 is equal. Have above known, by this state feedback information sending method, when state feedback information changes, the state feedback information of change is initiatively sent to upper computer by lower computer, can effectively save the memory source of upper computer, the process of the status feedback signal such as sensor is also efficient more in time. Further, in order to distinguish dissimilar state feedback information, the first character of state feedback information data frame joint is defined as " head character ", the type of this state feedback information that its value is corresponding, thus upper computer can resolve this state feedback information according to the difference of the value of data frame head character according to different types. Pass through the method, it is possible to improve upper computer further to the response speed of feedback signal and processing efficiency.
In sum, the communication system of the upper and lower computer of the semiconductor devices of the present invention and the method for communicating, by the command reception register of lower computer and action executing register are separated, working order according to topworks determines whether to be passed on to topworks by upper computer instruction, can effectively avoid topworks's instruction to perform chaotic and cause equipment and personal injury, also thus can improve the safety and reliability of equipment.
Although the present invention discloses as above with better embodiment; right described many embodiments are only illustrated for convenience of explanation; and be not used to limit the present invention; the technician of this area can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection domain that the present invention advocates should to be as the criterion described in claim book.
Claims (12)
1. a communication system for semiconductor devices upper computer and lower computer, comprises upper computer and lower computer, it is characterised in that, described lower computer comprises:
Command reception register, for receiving the instruction that described upper computer writes;
Action executing register, for receive from described command reception register instruction with drive described semiconductor devices topworks perform corresponding actions;
Zone bit configuration module, for configuring working order zone bit, described working order zone bit represents the working order of described topworks; And
Control module, for reading and control, according to described working order zone bit, instruction write that described command reception register received or do not write described action executing register.
2. communication system according to claim 1, it is characterised in that,
When the described working order zone bit that described control module reads is the first zone bit, it controls described command reception register and the instruction of reception writes described action executing register, described first zone bit is changed to the 2nd zone bit simultaneously;
When the described working order zone bit that described control module reads is described 2nd zone bit, it controls described command reception register and the instruction received is reset; Wherein said first zone bit represents that the working order of described topworks is for idle, and described 2nd zone bit represents that the working order of described topworks is in work.
3. communication system according to claim 2, it is characterised in that, when the action of described topworks completes, described 2nd zone bit is changed to described first zone bit by described control module, is reset by described action executing register simultaneously.
4. communication system according to claim 1, it is characterised in that, described lower computer also comprises interim status register and feedback states register, the state feedback information that wherein said interim status register gathers for upgrading described lower computer; When described control module judges that described feedback states register is different with the state feedback information in interim status register, give described feedback states register by the state feedback information that described interim status register upgrades; The state feedback information that described feedback states register is endowed is sent to described upper computer.
5. communication system according to claim 4, it is characterised in that, during described lower computer initialize, described feedback states register is reset by described control module.
6. communication system according to claim 4, it is characterised in that, the data frame head character of described state feedback information is for defining the type of this state feedback information, and described state feedback information is resolved by described upper computer according to described data frame head character.
7. semiconductor devices upper computer according to claim 1 carries out the method that communicates with the communication system of lower computer, comprising:
Described instruction is write to the command reception register of described lower computer by described upper computer; And
Determine whether the instruction that described command reception register module receives is write described action executing register according to described working order zone bit.
8. method according to claim 7, it is characterised in that,
When described working order zone bit is the first zone bit, the instruction that described command reception register receives is write described action executing register, described first zone bit is changed to the 2nd zone bit simultaneously;
When described working order zone bit is the 2nd zone bit, the instruction received by described command reception register resets; Wherein said first zone bit represents that the working order of described topworks is for idle, and described 2nd zone bit represents that the working order of described topworks is in work.
9. method according to claim 8, it is characterised in that, when the action of described topworks completes, described 2nd zone bit is changed to described first zone bit, described action executing register is reset simultaneously.
10. the method that a semiconductor devices upper computer according to claim 4 carries out communicating with the communication system of lower computer, it is characterised in that, comprising:
The state feedback information that described lower computer gathers is updated to described interim status register;
Judge that whether described feedback states register is identical with the state feedback information in interim status register;
If not identical, then the state feedback information that described interim status register upgrades is given described feedback states register send to described upper computer.
11. methods according to claim 10, it is characterised in that, before the state feedback information that described lower computer gathers is updated to described interim status register, also comprise lower computer described in initialize and by described feedback states register reset step.
12. methods according to claim 10, it is characterized in that, described state feedback information is resolved by the data frame head character of the state feedback information that described upper computer receives according to it, the type of wherein said data frame head this state feedback information of character definition.
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| CN108287805A (en) * | 2018-01-12 | 2018-07-17 | 厦门大学 | A kind of communication means and the application of universal the next microcontroller and host computer |
| CN108845537A (en) * | 2018-06-08 | 2018-11-20 | 山东超越数控电子股份有限公司 | The communication means of CPU and digital logic module in PLC system based on SOC FPGA |
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Address after: 100015 No. 1 East Jiuxianqiao Road, Beijing, Chaoyang District Patentee after: North China Science and technology group Limited by Share Ltd. Address before: 100016 Jiuxianqiao East Road, Beijing, No. 1, No. Patentee before: BEIJING SEVENSTAR ELECTRONIC Co.,Ltd. |
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Effective date of registration: 20180117 Address after: 100176 No. 8, Wenchang Avenue, Daxing District economic and Technological Development Zone, Beijing Patentee after: BEIJING NAURA MICROELECTRONICS EQUIPMENT Co.,Ltd. Address before: 100015 No. 1 East Jiuxianqiao Road, Beijing, Chaoyang District Patentee before: North China Science and technology group Limited by Share Ltd. |