CN103823447A - Communication method and communication system of upper and lower computers of semiconductor equipment - Google Patents
Communication method and communication system of upper and lower computers of semiconductor equipment Download PDFInfo
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- CN103823447A CN103823447A CN201410076579.XA CN201410076579A CN103823447A CN 103823447 A CN103823447 A CN 103823447A CN 201410076579 A CN201410076579 A CN 201410076579A CN 103823447 A CN103823447 A CN 103823447A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a communication system of upper and lower computers of semiconductor equipment. The lower computer comprises an instruction receiving register, an action execution register, a flag bit configuration module and a control module, wherein the instruction receiving register is used for receiving an instruction of the upper computer; the action execution register is used for receiving an instruction from the instruction receiving register so as to drive an execution mechanism of the semiconductor equipment to execute a corresponding action; the flag bit configuration module is used for configuring an operating state flag bit, wherein the operating state flag bit refers to an operating state of the execution mechanism; the control module is used for reading the operating state flag bit and controlling the instruction receiving register to write or not write the received instruction into the action execution register according to the operating state flag bit. The invention also provides a communication method, so that the safety and reliability of the equipment can be improved.
Description
Technical field
The present invention relates to the communications field, particularly the communication means between a kind of upper and lower computer of semiconductor equipment.
Background technology
At present most of domestic semiconductor equipment adopts the control framework of " host computer PC+slave computer ".Wherein the interactive communication of host computer and slave computer is to the method for the slave computer storer value of writing, steering order to be conveyed to slave computer by host computer, directly drives topworks's action by slave computer.Sensor feedback of status signal is to gather and store into corresponding registers by slave computer, is regularly obtained by reading these registers by host computer.
But, adopt the shortcoming of this communication means to be: first, host computer need to take ample resources and regularly read the feedback signal in register; Secondly, regularly reading machine system causes feedback information to obtain hysteresis; In addition, action command is written to slave computer register by host computer, and slave computer directly drives topworks's action to have potential safety hazard by the value of this register, has reduced the safety and reliability of equipment.
Therefore, be necessary to propose a kind of upper and lower computer communication means that can save host computer memory source, improve the response speed of topworks and sensor feedback and the reliability of raising equipment.
Summary of the invention
Fundamental purpose of the present invention aims to provide a kind of communication system and communication means of semiconductor equipment upper and lower computer, to improve above-mentioned defect.
For reaching above-mentioned purpose, the invention provides a kind of communication system of semiconductor equipment upper and lower computer, comprise host computer and slave computer, wherein, described host computer writes instruction to described slave computer, and described slave computer sends the state feedback information of the topworks of semiconductor equipment to described host computer.Described slave computer comprises command reception register, the instruction writing for receiving described host computer; Action executing register, carries out corresponding actions for receiving from the instruction of described command reception register with the topworks that drives described semiconductor equipment; Zone bit configuration module, for configuration effort state flag bit, described duty zone bit represents the duty of described topworks; And control module, for reading and the instruction of its reception being write or do not write described action executing register according to command reception register described in the control of described duty zone bit.
Preferably, when the described duty zone bit reading when described control module is the first zone bit, it is controlled described command reception register the instruction of reception is write to described action executing register, described the first zone bit is changed to the second zone bit simultaneously; When the described duty zone bit reading when described control module is described the second zone bit, it controls described command reception register by the instruction zero clearing receiving; Wherein said the first zone bit represents that the duty of described topworks is for idle, and described the second zone bit represents that the duty of described topworks is in work.
Preferably, in the time that the action of described topworks completes, described the second zone bit is changed to described the first zone bit by described control module, simultaneously by the zero clearing of described action executing register.
Preferably, described slave computer also comprises interim status register and feedback states register, and wherein said interim status register is for upgrading the state feedback information that described slave computer gathers; Described control module judges that when described feedback states register is different with state feedback information in interim status register, the state feedback information that described interim status register is upgraded is given described feedback states register; The state feedback information that described feedback states register is endowed is sent to described host computer.
Preferably, when described slave computer initialization, described control module is by the zero clearing of described feedback states register.
Preferably, the data frame head character of described state feedback information is for defining the type of this state feedback information, and described host computer is resolved described state feedback information according to described data frame head character.
The present invention also provides the communication means of a kind of semiconductor equipment host computer and slave computer, comprises by described host computer and writes described instruction to the command reception register of described slave computer; And determine that according to described duty zone bit the instruction whether described command reception register module being received writes described action executing register.
Preferably, in the time that described duty zone bit is the first zone bit, the instruction that described command reception register is received writes described action executing register, described the first zone bit is changed to the second zone bit simultaneously; In the time that described duty zone bit is the second zone bit, the instruction zero clearing that described command reception register is received; Wherein said the first zone bit represents that the duty of described topworks is for idle, and described the second zone bit represents that the duty of described topworks is in work.
Preferably, in the time that the action of described topworks completes, described the second zone bit is changed to described the first zone bit, simultaneously by the zero clearing of described action executing register.
Preferably, described communication means also comprises that the state feedback information that described slave computer is gathered is updated to described interim status register; Judge that whether the state feedback information in described feedback states register and interim status register is identical; If not identical, the state feedback information of described interim status register being upgraded is given described feedback states register and is sent to described host computer.
Preferably, before the state feedback information that described slave computer is gathered is updated to described interim status register, also comprise described in initialization slave computer and by the step of described feedback states register zero clearing.
Preferably, described host computer is resolved described state feedback information according to the data frame head character of the state feedback information of its reception, the type of wherein said this state feedback information of data frame head character definition.
Communication system and the method for semiconductor equipment upper and lower computer proposed by the invention, can effectively avoid topworks to perform an action instruction confusion and cause equipment and personal injury, improves the safety and reliability of equipment; In addition also can effectively save the memory source of host computer, also efficient more in time to the processing of sensor feedback of status signal.
Accompanying drawing explanation
Fig. 1 is the calcspar of the communication system of the semiconductor equipment upper and lower computer of one embodiment of the invention;
Fig. 2 is the host computer of semiconductor equipment of the present invention sends process flow diagram from instruction to slave computer;
Fig. 3 is the calcspar of the communication system of the semiconductor equipment upper and lower computer of another embodiment of the present invention;
Fig. 4 is the slave computer of semiconductor equipment of the present invention sends process flow diagram from state feedback information to host computer.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Fig. 1 is the calcspar of the communication system of semiconductor equipment upper and lower computer of the present invention.The communication system of semiconductor equipment upper and lower computer comprises host computer 10 and slave computer 20, and instruction is sent to slave computer 20 by host computer 10, drives the topworks 30 of semiconductor equipment to carry out corresponding actions by slave computer 20.Wherein, slave computer 20 comprises command reception register (D1) 21, action executing register (D2) 22, control module 23 and zone bit configuration module 24.Wherein, the instruction that command reception register 21 writes for receiving host computer 10; Action executing register 22 and instruction receiving registers 21 are connected, and carry out corresponding actions for receiving from the instruction of command reception register 21 with the topworks 30 that drives semiconductor equipment; Zone bit configuration module 24 is for configuring the duty zone bit X of the duty that represents topworks, and there is corresponding relation in the value of duty zone bit X and action executing register 22, while being idle as the duty when topworks 30 in the present embodiment, duty zone bit X=Free, the value in action executing register 22 is 0; When the duty of topworks 30 is in work, duty zone bit X=Busy, the value in action executing register 22 is not 0; Control module 23 is connected with command reception register 21 with zone bit configuration module 24, for read work state flag bit X, and whether the instruction write activity of reception is carried out to register 22 to convey to topworks 30 according to duty zone bit X steering order receiving register 21.
Fig. 2 is the host computer of semiconductor equipment sends process flow diagram from instruction to slave computer, and below with reference to Fig. 1 and Fig. 2, the communication means of the semiconductor equipment upper and lower computer to first embodiment of the invention describes.
First, host computer is written to instruction code after the command reception register D1 of slave computer, control module 23 read work state flag bit X, if duty zone bit X=Free, illustrate that topworks 30 is in the free time, instruction code is written to the action register D2 of topworks by control module 23 steering order receiving register D1, topworks's action register 22 can drive topworks 30 to carry out action corresponding to this instruction, and the duty zone bit X in zone bit configuration module 24 is changed to X=Busy by control module 23 simultaneously.Until after the action executing of topworks 30 finishes, the value zero clearing that control module 23 is moved topworks in register D2, reverts to X=Free by duty zone bit X simultaneously.The instruction again of carrying out again afterwards host computer writes.
On the other hand, if duty zone bit X=Busy illustrates that now topworks is still performing an action, control module, by the value zero clearing in host computer command reception register D1, is again write instruction, is carried out the judgement of duty zone bit by host computer.Until after topworks 30 finishes action executing, control module 23 just reverts to X=Free by duty zone bit, simultaneously by action executing register D2 zero clearing.After this instruction that command reception register D1 receives can be carried out register D2 by write activity, drives topworks 30 to carry out next step action.
As known from the above, send the method for instruction to slave computer by above-mentioned host computer, by command reception register and action executing register are separated, when topworks is still in the time carrying out action executing, the instruction that host computer can not sent sends to action executing register, therefore equipment and the personal injury that can effectively avoid topworks to carry out chaotic action command and to cause, the safety and reliability of raising equipment.
In another preferred embodiment of the present invention, slave computer also can initiatively send sensor state feedback information to host computer.Fig. 3 and Fig. 4 are the communication system calcspar of the present embodiment and slave computer send process flow diagram from state feedback information to host computer.
As shown in Figure 3, in slave computer, also comprise that command reception register D1, action executing register D2 and zone bit configuration module etc. in feedback states register (D3) 25 and interim status register (D4) 26(Fig. 1 are also not shown).The state feedback information that wherein interim status register 26 gathers for upgrading slave computer; Control module is connected with feedback states register 25 with interim status register 26, and when it judges two state feedback information in register for difference, the state feedback information that interim status register 25 is upgraded is given feedback states register 26.The state feedback information that feedback states register 25 is endowed is sent to host computer.
Specifically, as shown in Figure 4, the communication instruction that slave computer utilization carries initiatively sends state feedback information to host computer, the method that its " initiatively " sends is as follows: first in the time of slave computer initialization by feedback states register D3 zero clearing, and the state feedback information collecting is updated in interim status register D4.Then judge whether the value in feedback states register D3 and interim status register D4 equates, if the value in D3 and D4 is unequal, the value in interim status register D4 is assigned to feedback states register D3, carries out once " initiatively " transmission by feedback states register D3 simultaneously state feedback information is sent to host computer.Host computer is processed it by event trigger mechanism.If D3 equates with the value in D4, description status feedback information does not change, and slave computer continues the state feedback information collecting to be updated to interim status register D4, and if judgement D3 whether equate with the value in D4.Have above known, by this state feedback information sending method, in the time that state feedback information changes, slave computer is initiatively sent to host computer by the state feedback information of variation, can effectively save the memory source of host computer, also efficient more in time to the processing of sensor feedback of status signal.Further, in order to distinguish dissimilar state feedback information, first byte of state feedback information Frame is defined as to " character ", the type of this state feedback information that its value is corresponding, host computer can be resolved this state feedback information according to different types according to the difference of the value of data frame head character thus.By the method, can further improve response speed and the treatment effeciency of host computer to feedback signal.
In sum, the communication system of the upper and lower computer of semiconductor equipment of the present invention and communication means, by the command reception register of slave computer and action executing register are separated, determine whether host computer instruction will be conveyed to topworks according to the duty of topworks, can effectively avoid topworks's instruction to carry out chaotic and cause equipment and personal injury, also can improve thus the safety and reliability of equipment.
Although the present invention discloses as above with preferred embodiment; so described many embodiment only give an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection domain that the present invention advocates should be as the criterion with described in claims.
Claims (12)
1. a communication system for semiconductor equipment host computer and slave computer, comprises host computer and slave computer, it is characterized in that, described slave computer comprises:
Command reception register, the instruction writing for receiving described host computer;
Action executing register, carries out corresponding actions for receiving from the instruction of described command reception register with the topworks that drives described semiconductor equipment;
Zone bit configuration module, for configuration effort state flag bit, described duty zone bit represents the duty of described topworks; And
Control module, for reading and the instruction of its reception being write or do not write described action executing register according to command reception register described in the control of described duty zone bit.
2. communication system according to claim 1, is characterized in that,
When the described duty zone bit reading when described control module is the first zone bit, it is controlled described command reception register the instruction of reception is write to described action executing register, described the first zone bit is changed to the second zone bit simultaneously;
When the described duty zone bit reading when described control module is described the second zone bit, it controls described command reception register by the instruction zero clearing receiving; Wherein said the first zone bit represents that the duty of described topworks is for idle, and described the second zone bit represents that the duty of described topworks is in work.
3. communication system according to claim 2, is characterized in that, in the time that the action of described topworks completes, described the second zone bit is changed to described the first zone bit by described control module, simultaneously by the zero clearing of described action executing register.
4. communication system according to claim 1, is characterized in that, described slave computer also comprises interim status register and feedback states register, and wherein said interim status register is for upgrading the state feedback information that described slave computer gathers; Described control module judges that when described feedback states register is different with state feedback information in interim status register, the state feedback information that described interim status register is upgraded is given described feedback states register; The state feedback information that described feedback states register is endowed is sent to described host computer.
5. communication system according to claim 4, is characterized in that, when described slave computer initialization, described control module is by the zero clearing of described feedback states register.
6. communication system according to claim 4, is characterized in that, the data frame head character of described state feedback information is for defining the type of this state feedback information, and described host computer is resolved described state feedback information according to described data frame head character.
7. the communication means that the communication system of semiconductor equipment host computer according to claim 1 and slave computer is carried out, comprising:
Write described instruction by described host computer to the command reception register of described slave computer; And
Determine that according to described duty zone bit the instruction whether described command reception register module being received writes described action executing register.
8. communication means according to claim 7, is characterized in that,
In the time that described duty zone bit is the first zone bit, the instruction that described command reception register is received writes described action executing register, described the first zone bit is changed to the second zone bit simultaneously;
In the time that described duty zone bit is the second zone bit, the instruction zero clearing that described command reception register is received; Wherein said the first zone bit represents that the duty of described topworks is for idle, and described the second zone bit represents that the duty of described topworks is in work.
9. communication means according to claim 8, is characterized in that, in the time that the action of described topworks completes, described the second zone bit is changed to described the first zone bit, simultaneously by the zero clearing of described action executing register.
10. the communication means that the communication system of semiconductor equipment host computer according to claim 4 and slave computer is carried out, is characterized in that, comprising:
The state feedback information that described slave computer is gathered is updated to described interim status register;
Judge that whether the state feedback information in described feedback states register and interim status register is identical;
If not identical, the state feedback information of described interim status register being upgraded is given described feedback states register and is sent to described host computer.
11. communication meanss according to claim 10, it is characterized in that, before the state feedback information that described slave computer is gathered is updated to described interim status register, also comprise described in initialization slave computer and by the step of described feedback states register zero clearing.
12. communication meanss according to claim 10, it is characterized in that, described host computer is resolved described state feedback information according to the data frame head character of the state feedback information of its reception, the type of wherein said this state feedback information of data frame head character definition.
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| CN110231798A (en) * | 2019-05-21 | 2019-09-13 | 上海航天设备制造总厂有限公司 | The communication alternate acknowledge mechanism of human-computer interaction interface and programmable logic controller (PLC) |
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| CN110231798A (en) * | 2019-05-21 | 2019-09-13 | 上海航天设备制造总厂有限公司 | The communication alternate acknowledge mechanism of human-computer interaction interface and programmable logic controller (PLC) |
| CN112637248A (en) * | 2021-03-09 | 2021-04-09 | 厚普清洁能源股份有限公司 | Ship-end and shore-end equipment communication processing method for LNG filling wharf boat |
| CN113419464A (en) * | 2021-07-13 | 2021-09-21 | 上海迪璞电子科技股份有限公司 | Open type automobile offline detection test board scheduling control system, method and device |
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