CN103811357A - Ultra-thin wafer level package manufacturing method - Google Patents
Ultra-thin wafer level package manufacturing method Download PDFInfo
- Publication number
- CN103811357A CN103811357A CN201410033740.5A CN201410033740A CN103811357A CN 103811357 A CN103811357 A CN 103811357A CN 201410033740 A CN201410033740 A CN 201410033740A CN 103811357 A CN103811357 A CN 103811357A
- Authority
- CN
- China
- Prior art keywords
- disk
- wafer
- wafer level
- super
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Abstract
The invention provides an ultra-thin wafer level package manufacturing method which includes the steps: providing a wafer; forming conductive bumps on the surfaces of chips far away from the wafer; pasting a protective film on one surface of the wafer with the formed conductive bumps; downwards placing the surface of the wafer with the formed conductive bumps on a slide holder, and selectively and annularly thinning the other surface of the wafer without the chips to form an annular structure with a thick periphery and a thin middle; turning over the selectively and annularly thinned wafer and placing the wafer on the slide holder; ripping out the protective film formed on the wafer; testing the wafer without the protective film and then cutting the wafer. A plurality of chips are distributed on one surface of the wafer in an arrayed manner. By the ultra-thin wafer level package manufacturing method, a single chip of the semiconductor device wafer package with the same function is thinner and thinner, and the wafer is only slightly warped after the back of the wafer is thinned.
Description
Technical field
The present invention relates to a kind of method for packaging semiconductor, relate in particular to a kind of super-thin wafer level packaging manufacture method.
Background technology
In recent years, semiconductor device is under the common promotion of the lifting of cost He Qian road wafer manufacturing process, realize the more and more less target of monomer chip size of the semiconductor device of said function, can cause like this semiconductor device heat radiation to require more and more higher, also need semiconductor device more and more thinner, wafer level packaging technique wafer reduction process originally cannot meet the requirement of thin type and high heat radiation simultaneously.
Existing wafer level packaging process chart as shown in Figure 1, by existing wafer level packaging Wafer Thinning technique, after the attenuate of disk back, there will be the situation of overall warpage, be illustrated in figure 3 the sectional view after the attenuate of disk back, 301 is chip, 305 is the salient point generating on chip, and 306 is the diaphragm of coating chip and salient point, the disk after the attenuate that 302a is semiconductor device; The sectional view that is illustrated in figure 4 warpage after the attenuate of disk back, carries out after reduction process at disk back, removes the diaphragm 306 of above-mentioned coating chip and salient point, and disk there will be the situation of warpage.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to the basic comprehension about some aspect of the present invention is provided.Should be appreciated that this general introduction is not about exhaustive general introduction of the present invention.It is not that intention is determined key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only that the form of simplifying provides some concept, using this as the preorder in greater detail of discussing after a while.
The invention provides a kind of super-thin wafer level packaging manufacture method, comprising:
S201: disk is provided, and the one side array distribution of described disk has multiple chips;
S202: form conductive salient point away from the surface of described disk at described chip;
S203: the one side that is formed with conductive salient point at disk is pasted layer protecting film;
S204: disk is formed with to one of conductive salient point and faces down, be placed on slide holder, do not form the one side selectivity ring-type attenuate of described chip at disk, form the circulus of the thick intermediate thin of periphery;
S205: by the disk upset after selectivity ring-type attenuate, be placed on slide holder;
S206: tear the diaphragm being formed on disk off;
S207: the disk of removing diaphragm is tested, cut after test.
A kind of super-thin wafer level packaging manufacture method provided by the invention, has realized the more and more thinner target of monomer chip thickness of the semiconductor device disk encapsulation of said function, and has realized the target of only having small warpage after the attenuate of disk back.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is existing wafer level packaging process chart;
Fig. 2 is sectional view after disk back side entirety attenuate in existing technique;
Fig. 3 is the sectional view of warpage after disk entirety attenuate in existing technique;
Fig. 4 is the ultra-thin wafer level packaging manufacture method of the present invention flow chart;
Fig. 5 to Fig. 7 encapsulates schematic diagram before Wafer Thinning in the embodiment of the present invention;
Fig. 8 is sectional view after disk back side selectivity ring-type attenuate in the embodiment of the present invention;
Fig. 9 is sectional view after ring-type attenuate disk is sent on slide holder in the embodiment of the present invention;
Figure 10 is that in the embodiment of the present invention, ring-type attenuate disk is sent on slide holder sectional view after dyestripping;
Figure 11 is the rear schematic diagram of ring-type attenuate disk cutting in the embodiment of the present invention.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.The element of describing in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with element and feature shown in one or more other accompanying drawing or execution mode.It should be noted that for purposes of clarity, in accompanying drawing and explanation, omitted expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and processing.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not paying creative work, belongs to the scope of protection of the invention.
The invention provides a kind of super-thin wafer level packaging manufacture method, be illustrated in figure 1 the ultra-thin wafer level packaging manufacture method of the present invention flow chart, comprise step:
S201: disk is provided, and the one side array distribution of described disk has multiple chips;
Before disk encapsulation, disk substrate first will be provided, as shown in Figure 5, provide disk 202, described disk upper surface has chip 201, and described chip 201 is array distribution in disk 202 one sides.
Preferably, be formed with electrode and passivation layer at described chip away from the surface of described disk, described conductive salient point is electrically connected with described electrode, and described passivation layer is positioned at described electrode top, and described conductive salient point exposes described passivation layer surface at least partly.Described electrode is formed at chip surface, and described electrode can be also pad, and electrode (as pad) is the fuction output terminal of chip, and finally realizes the conduction transition of electrical functionality by the salient point of follow-up formation.
Optionally; described passivation layer adopts the mixture preparation of following a kind of material or multiple material: silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene; shown in the material of passivation layer comprise dielectric material or their mixtures such as silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene, for the protection of the circuit in chip 201.
It should be noted that, the pad of described chip and passivation layer can be initial pad and the initial passivation of chip, and can be also needs according to circuit layout-design the transition pad, the passivation layer that form; The mode that forms transition pad, passivation layer is mainly to adopt Wiring technique technology again, connect up again initial pad, passivation layer are reprinted on transition pad, passivation layer by one or more layers, form transition pad if pass through again Wiring technique, the conductive salient point being formed on chip is connected with last one deck electrode, and described conductive salient point exposes last one deck passivation layer surface at least partly.The described technology of Wiring technique is again existing maturation process, is well known to those skilled in the art, and does not repeat them here.
S202: form conductive salient point away from the surface of described disk at described chip;
As shown in Figure 6, and then on described chip, form conductive salient point 203, optional, the material of described conductive salient point 203 is for having high conduction and dystectic metal material, as copper etc.Conductive salient point can be copper post.Forming described conductive salient point is the transmission in order to realize electrical functionality, and described conductive salient point can be formed at above-mentioned electrode or bond pad surface, or form metal wiring layer again at electrode or bond pad surface, described conductive salient point is formed to metal again on wiring layer, act on identical with function, be all the transmission in order to realize electrical functionality, the concrete steps of these methods for those skilled in the art of the present technique know, do not repeat them here.
S203: the one side that is formed with conductive salient point at disk is pasted layer protecting film;
After having formed conductive salient point 203, the one side that is formed with conductive salient point 203 at disk 202 is pasted layer protecting film 204, as shown in Figure 7; described diaphragm 204 coated with conductive salient points; conductive salient point is covered completely, for conductive salient point being protected in following step, be not worn.
Optionally, the material of described diaphragm 204 is epoxy resin, or is PI glue; above-mentioned material coated with conductive salient point, plays the effect of protection, and forms described diaphragm by modes such as printing, spin coatings; these have been well-known to those skilled in the art, do not repeat them here.
S204: disk is formed with to one of conductive salient point and faces down, be placed on slide holder, do not form the one side selectivity ring-type attenuate of described chip at disk, form the circulus of the thick intermediate thin of periphery;
Then disk 202 is formed with to one of salient point 203 and coated with protective film 203 and faces down, be placed on slide holder 303, the one side that disk is not formed to salient point is that selectivity ring-type attenuate is carried out at the back side of disk.
Optionally, described selectivity ring-type thining method is: utilize spherical gear to carry out ring-type polishing, by disk mid portion attenuate, retain disk peripheral part, form described circulus, the wafer architecture after polishing as shown in Figure 8.
Existing Wafer Thinning method is disk back all to be removed until reach the thickness needing, this method is after Wafer Thinning, tear off after the diaphragm on salient point, disk there will be the situation of warpage, as shown in Figs. 3-4, and it is more severe that disk more approaches edge warping degree, in order to reduce the warpage degree of the disk after attenuate, the present invention gets off the most serious Edge preserving of warpage degree, form a circulus, it is thicker that the disk at edge retains, even if can there is buckling deformation, the thickness at edge is also enough to make warpage to become very little, with respect to existing technique, warpage has obtained very large improvement.
S205: by the disk upset after selectivity ring-type attenuate, be placed on slide holder;
After the polishing attenuate of disk is finished, overturn, be placed on slide holder 303, as shown in Figure 9, the disk after attenuate is circulus, and just clamping is placed on slide holder 303.On described slide holder 303, have micro-groove 302b, described micro-groove is used for corresponding one by one with the groove on disk, and in the step of ensuing scribing for standard is done in its scribing.
Optionally, on disk after described ring-type attenuate, by being set, scribe line cuts disk, described scribe line is arranged at the disk surfaces between different chips, and described scribe line is corresponding one by one with the micro-groove on slide holder 303, the described scribe line of foundation in the time that disk is carried out to scribing.
In described slide holder 303, also have vacuum adapter and vacuum passage, extract the air in described vacuum passage, can will be placed on disk on slide holder and be firmly adsorbed on the surface of described slide holder, so implementing in Wafer Thinning, disk is attracted on slide holder, do not have any movement or crooked etc., after Wafer Thinning, its upset is adsorbed on slide holder, has also beaten basis for following step, the situation that there will not be disk to touch.
S206: tear the diaphragm being formed on disk off;
Implementation step S206 subsequently; diaphragm on disk is torn off, and as shown in figure 10, diaphragm 204 is the salient point on chip and chip to be protected when polishing attenuate at the disk back side; after end, also need to be torn off, proceed following step.
S207: the disk of removing diaphragm is tested, cut after test.
Subsequently as shown in figure 11, the disk of removing diaphragm is tested to the electrical property of the each salient point on test chip; After test, cut apart, described in cut apart along scribe line and carry out, the chip on disk is separated, form monomer bump chip.
Ultrathin wafer level packaging manufacture method provided by the invention also comprises step after S207: draw and separate rear tape package from slide holder.Draw each monomer bump chip from slide holder, each monomer bump chip is separated, carry out subsequently tape package.
The super-thin wafer level packaging manufacture method that the present invention proposes, by selectivity attenuate is carried out in disk back, after attenuate, form circulus, in the more and more thinner target of the monomer chip thickness of semiconductor device disk encapsulation of having realized said function, adopt selectivity ring-type attenuate, realize the target of only having small warpage after the attenuate of disk back, had very large improvement with respect to existing disk back thinning technique.
In the embodiment such as apparatus and method of the present invention, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decomposition and/or reconfigure and should be considered as equivalents of the present invention.Simultaneously, in the above in the description of the specific embodiment of the invention, describe and/or the feature that illustrates can be used in same or similar mode in one or more other execution mode for a kind of execution mode, combined with the feature in other execution mode, or substitute the feature in other execution mode.
Should emphasize, term " comprises/comprises " existence that refers to feature, key element, step or assembly while use herein, but does not get rid of the existence of one or more further feature, key element, step or assembly or add.
Finally it should be noted that: although described above the present invention and advantage thereof in detail, be to be understood that in the case of not exceeding the spirit and scope of the present invention that limited by appended claim and can carry out various changes, alternative and conversion.And scope of the present invention is not limited only to the specific embodiment of the described process of specification, equipment, means, method and step.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use carry out with the essentially identical function of corresponding embodiment described herein or obtain process, equipment, means, method or step result essentially identical with it, that existing and will be developed future according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (10)
1. a super-thin wafer level packaging manufacture method, is characterized in that, comprising:
S201: disk is provided, and the one side array distribution of described disk has multiple chips;
S202: form conductive salient point away from the surface of described disk at described chip;
S203: the one side that is formed with conductive salient point at disk is pasted layer protecting film;
S204: disk is formed with to one of conductive salient point and faces down, be placed on slide holder, do not form the one side selectivity ring-type attenuate of described chip at disk, form the circulus of the thick intermediate thin of periphery;
S205: by the disk upset after selectivity ring-type attenuate, be placed on slide holder;
S206: tear the diaphragm being formed on disk off;
S207: the disk of removing diaphragm is tested, cut after test.
2. super-thin wafer level packaging manufacture method according to claim 1, it is characterized in that, before described step S202, also comprise: be formed with electrode and passivation layer at described chip away from the surface of described disk, described conductive salient point is electrically connected with described electrode, described passivation layer is positioned at described electrode top, and described conductive salient point exposes described passivation layer surface at least partly.
3. super-thin wafer level packaging manufacture method according to claim 1, is characterized in that, described passivation layer adopts the mixture preparation of following a kind of material or multiple material: silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene.
4. super-thin wafer level packaging manufacture method according to claim 1, is characterized in that, the conductive salient point described in step S202 is copper post.
5. super-thin wafer level packaging manufacture method according to claim 1, is characterized in that, the coated described conductive salient point of diaphragm described in step S203.
6. super-thin wafer level packaging manufacture method according to claim 1, is characterized in that, the diaphragm material described in step S203 is epoxy resin.
7. super-thin wafer level packaging manufacture method according to claim 1, it is characterized in that, the selectivity ring-type thining method described in step S204 is: utilize spherical gear to carry out ring-type polishing, by disk mid portion attenuate, retain disk peripheral part, form described circulus.
8. super-thin wafer level packaging manufacture method according to claim 1, is characterized in that, in step S205, cuts disk by the scribe line arranging on disk.
9. super-thin wafer level packaging manufacture method according to claim 5, is characterized in that, described scribe line is corresponding one by one with the micro-groove on slide holder.
10. super-thin wafer level packaging manufacture method according to claim 1, is characterized in that, also comprises step after described super-thin wafer level packaging manufacture method S207: draw and separate rear tape package from slide holder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410033740.5A CN103811357A (en) | 2014-01-24 | 2014-01-24 | Ultra-thin wafer level package manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410033740.5A CN103811357A (en) | 2014-01-24 | 2014-01-24 | Ultra-thin wafer level package manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103811357A true CN103811357A (en) | 2014-05-21 |
Family
ID=50707952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410033740.5A Pending CN103811357A (en) | 2014-01-24 | 2014-01-24 | Ultra-thin wafer level package manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103811357A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105666333A (en) * | 2016-01-15 | 2016-06-15 | 应达利电子股份有限公司 | Method for manufacturing thin ceramic cap body |
| CN109358281A (en) * | 2018-10-11 | 2019-02-19 | 颜建芳 | Burning chip test equipment and its test or burning program method for chip |
| CN109712926A (en) * | 2017-10-25 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6024631A (en) * | 1996-11-26 | 2000-02-15 | Micron Technology, Inc. | Method and apparatus to hold integrated circuit chips onto a chuck and to simultaneously remove multiple integrated circuit chips from a cutting chuck |
| US20060275949A1 (en) * | 2002-03-06 | 2006-12-07 | Farnworth Warren M | Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors |
| JP2007103739A (en) * | 2005-10-05 | 2007-04-19 | Toshiba Corp | Semiconductor device manufacturing method |
| CN101625972A (en) * | 2008-07-11 | 2010-01-13 | 半导体元件工业有限责任公司 | Method of thinning a semiconductor wafer |
| CN101625994A (en) * | 2008-07-09 | 2010-01-13 | 力成科技股份有限公司 | Large-sized wafer cutting method and device |
| CN102315168A (en) * | 2010-07-09 | 2012-01-11 | 瑞鼎科技股份有限公司 | Method for cutting integrated circuit wafer |
| CN102509707A (en) * | 2011-12-19 | 2012-06-20 | 如皋市大昌电子有限公司 | Process of carrying out passivation protection on rectification chip by use of polyimide |
| CN102543781A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Optimizing process of wafer-level packaging |
| US20130130443A1 (en) * | 2011-11-22 | 2013-05-23 | Jun Lu | Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process |
| CN103489820A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for isolating device |
-
2014
- 2014-01-24 CN CN201410033740.5A patent/CN103811357A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6024631A (en) * | 1996-11-26 | 2000-02-15 | Micron Technology, Inc. | Method and apparatus to hold integrated circuit chips onto a chuck and to simultaneously remove multiple integrated circuit chips from a cutting chuck |
| US20060275949A1 (en) * | 2002-03-06 | 2006-12-07 | Farnworth Warren M | Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors |
| JP2007103739A (en) * | 2005-10-05 | 2007-04-19 | Toshiba Corp | Semiconductor device manufacturing method |
| CN101625994A (en) * | 2008-07-09 | 2010-01-13 | 力成科技股份有限公司 | Large-sized wafer cutting method and device |
| CN101625972A (en) * | 2008-07-11 | 2010-01-13 | 半导体元件工业有限责任公司 | Method of thinning a semiconductor wafer |
| CN102315168A (en) * | 2010-07-09 | 2012-01-11 | 瑞鼎科技股份有限公司 | Method for cutting integrated circuit wafer |
| US20130130443A1 (en) * | 2011-11-22 | 2013-05-23 | Jun Lu | Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process |
| CN102509707A (en) * | 2011-12-19 | 2012-06-20 | 如皋市大昌电子有限公司 | Process of carrying out passivation protection on rectification chip by use of polyimide |
| CN102543781A (en) * | 2012-01-17 | 2012-07-04 | 南通富士通微电子股份有限公司 | Optimizing process of wafer-level packaging |
| CN103489820A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for isolating device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105666333A (en) * | 2016-01-15 | 2016-06-15 | 应达利电子股份有限公司 | Method for manufacturing thin ceramic cap body |
| CN105666333B (en) * | 2016-01-15 | 2018-06-19 | 应达利电子股份有限公司 | A kind of preparation method of thin ceramic cover |
| CN109712926A (en) * | 2017-10-25 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN109358281A (en) * | 2018-10-11 | 2019-02-19 | 颜建芳 | Burning chip test equipment and its test or burning program method for chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102163559B (en) | Manufacturing method of stack device and device chip process method | |
| US9716080B1 (en) | Thin fan-out multi-chip stacked package structure and manufacturing method thereof | |
| KR20040092435A (en) | Semiconductor device and manufacturing method thereof | |
| CN103400807B (en) | The wafer level packaging structure of image sensor and method for packing | |
| JP6393036B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20080076207A1 (en) | Manufacturing method of semiconductor device | |
| CN109390326A (en) | Semiconductor device and its manufacturing method | |
| US11069652B2 (en) | Method of manufacturing semiconductor structure | |
| US9070672B2 (en) | Semiconductor device packaging structure and packaging method | |
| CN106415817A (en) | Dicing method for wafer-level packaging and semiconductor chip with dicing structure adapted for wafer-level packaging | |
| US8652939B2 (en) | Method and apparatus for die assembly | |
| CN105632911A (en) | Wafer level package method for reducing edge stress | |
| CN103811357A (en) | Ultra-thin wafer level package manufacturing method | |
| CN103420322B (en) | Wafer encapsulation body and forming method thereof | |
| TW201428904A (en) | Semiconductor package and fabrication method thereof | |
| JP4528758B2 (en) | Transfer tape and semiconductor device manufacturing method using the transfer tape | |
| CN103811536A (en) | Wafer thinning structure for wafer level packaging technology | |
| TW201611212A (en) | Electronic monomer and method of fabricating the same | |
| JP2004343088A (en) | Semiconductor device and its manufacturing method | |
| CN103247639A (en) | Wafer level packaging method and structure of image sensor | |
| CN203733801U (en) | Wafer thinning structure | |
| CN107611097A (en) | Wafer stage chip encapsulating structure and preparation method thereof | |
| TWI575676B (en) | Electronic package structure and method of manufacture | |
| JP2005191485A (en) | Semiconductor device | |
| CN114628250A (en) | Wafer scribing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| COR | Change of bibliographic data | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140521 |