CN103811021A - Method and device for waveform analysis - Google Patents
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- CN103811021A CN103811021A CN201410054919.9A CN201410054919A CN103811021A CN 103811021 A CN103811021 A CN 103811021A CN 201410054919 A CN201410054919 A CN 201410054919A CN 103811021 A CN103811021 A CN 103811021A
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Abstract
The invention provides a method and a device for waveform analysis. The method includes that sinusoidal waveforms are received and sampled to obtain square waveforms, and the square waveforms sequentially include waveforms of test data and waveforms of valid data; a pulse width Mi between an i<th> rising edge and a (i+1)<th> rising edge in the waveforms of the test data is obtained, and a pulse width Ni between an i<th> falling edge and a (i+1)<th> falling edge in the waveforms of the test data is obtained; a cycle T0 of logic 0 and a cycle T1 of logic 1 are obtained by the pulse width Mi and the pulse width Ni; whether the pulse width Mi and the pulse width Ni are between the cycle T0 and the cycle T1 or not is determined; if the pulse width Mi is between the cycle T0 and the cycle T1, bits represented by the waveforms of the valid data are analyzed in sequence according to a pulse width between two adjacent falling edges in the square waveforms; if the pulse width Ni is between the cycle T0 and the cycle T1, bits represented by the waveforms of the valid data are analyzed in sequence according to a pulse width between two adjacent rising edges.
Description
Technical field
The present invention relates to electronic technology field, relate in particular to a kind of waveform display method and device of resolving.
Background technology
Intelligent cipher key equipment is the safety equipment with signature function and/or dynamic password systematic function.In the time that the mobile terminals such as intelligent cipher key equipment and mobile phone, panel computer communicate by audio interface, after mobile terminal output waveform, intelligent cipher key equipment can be sampled to the waveform receiving, and parses the bit that waveform is corresponding.
And in prior art, do not provide a kind of scheme of resolving waveform corresponding to sound signal.
Summary of the invention
The invention provides a kind of method and apparatus of resolving waveform, fundamental purpose is to provide the parsing scheme to waveform when by audio interface transmitted waveform.
A kind of method of resolving waveform, comprise: receive sine waveform, described sine waveform is sampled, obtain square-wave waveform, wherein said square-wave waveform comprises the waveform of test data and the waveform of valid data successively, the waveform of wherein said test data comprises the waveform of the individual continuous logical zero of a consulting in advance and b continuous logical one, and wherein a and b are the integer that is more than or equal to 3, and wherein the cycle T 0 of logical zero and the cycle T 1 of logical one are unequal; Obtain the pulse width Mi between i rising edge and i+1 rising edge in the waveform of described test data, and pulse width Ni between i negative edge and i+1 negative edge, i is the positive integer that is less than or equal to the summation of a and b; According to the bit-order of logical zero and logical one in the waveform of the described test data of obtaining in advance, utilize pulse width Mi and pulse width Ni to obtain the cycle T 0 of logical zero and the cycle T 1 of logical one; Judge that pulse width Mi and pulse width Ni are whether between cycle T 0 and cycle T 1; If pulse width Mi, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent negative edges, obtains each pulse width of the waveform of valid data successively; If pulse width Ni, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent rising edges, obtains each pulse width of the waveform of valid data successively; After the each pulse width of waveform that obtains valid data, according to each pulse width of the waveform of the cycle T 1 of the cycle T 0 of logical zero and logical one and valid data, the bit that the waveform of parsing valid data represents.
Wherein, according to the bit-order of logical zero and logical one in the waveform of the described test data of obtaining in advance, utilize pulse width Mi and pulse width Ni to obtain the cycle T 0 of logical zero and the cycle T 1 of logical one, comprise: obtain multiple pulse widths corresponding to logical zero in the waveform of test data, the multiple pulse widths corresponding to the logical zero getting are averaged, and obtain cycle T 0; And, obtain multiple pulse widths corresponding to logical one in the waveform of test data, the multiple pulse widths corresponding to the logical one getting are averaged, and obtain cycle T 1.
A method of resolving waveform, comprising: steps A, reception sine waveform, described sine waveform is sampled, and obtain square-wave waveform; Step B, obtain the pulse width Mi between i rising edge and i+1 rising edge in described square-wave waveform, and pulse width Ni between i negative edge and i+1 negative edge, i is positive integer; Step C, judge that pulse width Mi and pulse width Ni are whether between the cycle T 0 of the logical zero obtaining in advance and the cycle T 1 of the logical one that obtains in advance, wherein cycle T 0 and cycle T 1 are unequal; If step D pulse width Mi, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Ni, obtain the bit that described square-wave waveform represents; If pulse width Ni, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Mi, obtain the bit that described square-wave waveform represents; If step e pulse width Mi and pulse width Ni be not all between cycle T 0 and cycle T 1, the value of upgrading i is i+1, execution step B.
A kind of device of resolving waveform, comprise: processing module, be used for receiving sine waveform, described sine waveform is sampled, obtain square-wave waveform, wherein said square-wave waveform comprises the waveform of test data and the waveform of valid data successively, and the waveform of wherein said test data comprises the waveform of the individual continuous logical zero of a consulting in advance and b continuous logical one, wherein a and b are the integer that is more than or equal to 3, and wherein the cycle T 0 of logical zero and the cycle T 1 of logical one are unequal; The first acquisition module, for obtaining the pulse width Mi between i rising edge of waveform and i+1 the rising edge of described test data, and pulse width Ni between i negative edge and i+1 negative edge, i is the positive integer that is less than or equal to the summation of a and b; The second acquisition module, for the waveform logical zero according to the described test data of obtaining in advance and the bit-order of logical one, utilizes pulse width Mi and pulse width Ni to obtain the cycle T 0 of logical zero and the cycle T 1 of logical one; Judge module, be used for judging whether the 3rd acquisition module between cycle T 0 and cycle T 1 of pulse width Mi and pulse width Ni, if be used for pulse width Mi between cycle T 0 and cycle T 1,, according to the pulse width between two adjacent negative edges, obtain successively each pulse width of the waveform of valid data; If pulse width Ni, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent rising edges, obtains each pulse width of the waveform of valid data successively; Parsing module, for after the each pulse width of waveform that obtains valid data, according to each pulse width of the waveform of the cycle T 1 of the cycle T 0 of logical zero and logical one and valid data, the bit that the waveform of parsing valid data represents.
Wherein, described the second acquisition module, for obtaining multiple pulse widths corresponding to waveform logical zero of test data, the multiple pulse widths corresponding to the logical zero getting are averaged, and obtain cycle T 0; And, obtain multiple pulse widths corresponding to logical one in the waveform of test data, the multiple pulse widths corresponding to the logical one getting are averaged, and obtain cycle T 1.
A device of resolving waveform, comprising: processing module, for receiving sine waveform, described sine waveform is sampled, and obtain square-wave waveform; Acquisition module, for obtaining the pulse width Mi between i rising edge of described square-wave waveform and i+1 rising edge, and pulse width Ni between i negative edge and i+1 negative edge, i is positive integer; Judge module, for judging that pulse width Mi and pulse width Ni are whether between the cycle T 0 of the logical zero obtaining in advance and the cycle T 1 of the logical one that obtains in advance, wherein cycle T 0 and cycle T 1 are unequal; Parsing module, if for pulse width Mi between cycle T 0 and cycle T 1, resolve described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Ni, obtain the bit that described square-wave waveform represents; If pulse width Ni, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Mi, obtain the bit that described square-wave waveform represents; Update module, if for pulse width Mi and pulse width Ni all not between cycle T 0 and cycle T 1, the value of upgrading i is i+1, triggers the operation of acquisition module.
Embodiment of the method provided by the invention, is coming presentation logic 0 and at 1 o'clock by the waveform of transmission different cycles, the cycle of obtaining in different ways test waveform, determine that the waveform that the waveform of valid data is used divides benchmark, and improve the accuracy of wave analysis.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is the schematic flow sheet that the invention provides a kind of embodiment of the method for resolving waveform;
Fig. 2 is the schematic flow sheet that the invention provides another kind of embodiment of the method for resolving waveform;
Fig. 3 is the structural representation that the invention provides a kind of device embodiment that resolves waveform;
Fig. 4 is the structural representation that the invention provides the another kind of device embodiment that resolves waveform.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on embodiments of the invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to protection scope of the present invention.
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in further detail.
Fig. 1 is the schematic flow sheet that the invention provides a kind of embodiment of the method for resolving waveform.Shown in Fig. 1, embodiment of the method comprises:
Step 101, reception sine waveform, described sine waveform is sampled, obtain square-wave waveform, wherein said square-wave waveform comprises the waveform of test data and the waveform of valid data successively, the waveform of wherein said test data comprises the waveform of the individual continuous logical zero of a consulting in advance and b continuous logical one, wherein a and b are the integer that is more than or equal to 3, and wherein the cycle T 0 of logical zero and the cycle T 1 of logical one are unequal;
Wherein, intelligent cipher key equipment is to the sine wave being sent by mobile terminal receiving, according to local sample frequency, described sinusoidal wave sampling is obtained to square-wave waveform, the data of wherein carrying in square wave comprise test data and valid data, wherein test data is for determining the division benchmark in square-wave waveform cycle, and valid data are the data of the actual needs of mobile terminal transmission; The logical zero wherein carrying in square wave and logical one were distinguished by the unequal cycle;
In addition, in the waveform of test data, the number of logical zero and logical one is all greater than 3, to reduce the deviation that in waveform transmitting procedure, wave form varies is brought.
Wherein, the detection of rising edge and negative edge can change to detect by level, the clock that its pulse width can be used according to waveform is determined, can calculate in this step two groups of cycles that logical bits is corresponding, be respectively the periodic sequence (being pulse width Mi) calculating according to rising edge, the periodic sequence calculating according to negative edge (being pulse width Ni).
Wherein, obtain multiple pulse widths corresponding to logical zero in the waveform of test data, the multiple pulse widths corresponding to the logical zero getting are averaged, and obtain cycle T 0; And, obtain multiple pulse widths corresponding to logical one in the waveform of test data, the multiple pulse widths corresponding to the logical one getting are averaged, and obtain cycle T 1;
It should be noted that, take the cycle T 0 of computational logic 0 as example, can only calculate with multiple pulse width Mi corresponding to logical zero, also can only calculate with multiple pulse width Ni corresponding to logical zero, certainly, can also calculate with multiple pulse width Mi corresponding to logical zero and multiple pulse width Ni; In like manner, T1 also can adopt aforesaid way.In addition, for saltus step place of logical zero and logical one, the value of pulse width Mi or pulse width Ni may be the half period of logical zero and the half period sum of logical one, this value both can for calculate T0 also can for calculate T1.
In the time calculating T0 or T1, can use multiple pulse width Mi and multiple pulse width Ni, to reduce the error of computation of Period.
If step 105 pulse width Mi, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent negative edges, obtains each pulse width of the waveform of valid data successively; If pulse width Ni, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent rising edges, obtains each pulse width of the waveform of valid data successively;
That is to say, if Mi is between T0 and T1, represent that the periodic sequence calculating according to rising edge can have problems at logical zero and logical one saltus step place (being the above-mentioned half period of logical zero and the half period sum of logical one), obtains each pulse width of the waveform of valid data successively according to the pulse width between two adjacent negative edges; If Ni between T0 and T1, represents that the periodic sequence calculating according to negative edge can have problems at logical zero and logical one saltus step place, obtains each pulse width of the waveform of valid data successively according to the pulse width between two adjacent rising edges.
Wherein, if pulse width Mi and pulse width Ni all not between cycle T 0 and cycle T 1, the value of upgrading i is i+1, continues execution step 104.
Embodiment of the method provided by the invention, is coming presentation logic 0 and at 1 o'clock by the waveform of transmission different cycles, the cycle of obtaining in different ways test waveform, determine that the waveform that the waveform of valid data is used divides benchmark, and improve the accuracy of wave analysis.
Fig. 2 is the schematic flow sheet that the invention provides another kind of embodiment of the method for resolving waveform.Shown in Fig. 2, embodiment of the method comprises:
Wherein, intelligent cipher key equipment, to the sine wave being sent by mobile terminal receiving, according to local sample frequency, obtains square-wave waveform to described sinusoidal wave sampling.In square-wave waveform, at least comprise the waveform of valid data.
Wherein, the detection of rising edge and negative edge can change to detect by level, the clock that its pulse width can be used according to waveform is determined, two groups of cycles that logical bits is corresponding in can calculating in this step, be respectively the periodic sequence calculating according to rising edge, the periodic sequence calculating according to negative edge.
If step 204 pulse width Mi, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Ni, obtain the bit that described square-wave waveform represents; If pulse width Ni, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Mi, obtain the bit that described square-wave waveform represents;
If step 205 pulse width Mi and pulse width Ni be not all between cycle T 0 and cycle T 1, the value of upgrading i is i+1, execution step 202.
Embodiment of the method provided by the invention, coming presentation logic 0 and at 1 o'clock by the waveform of transmission different cycles, obtain in different ways the cycle of square-wave waveform, determine the waveform division benchmark that the waveform of valid data is wherein used, the accuracy that improves wave analysis.
Averaging by multiple pulse widths of the waveform to test data from intelligent cipher key equipment in embodiment mono-, to obtain cycle of logical zero and logical one different, in the present embodiment, get in advance the cycle (can be the cycle T 0 of logical zero and the cycle T 1 of logical one that mobile terminal and intelligent cipher key equipment are consulted in advance) of logical zero and logical one, therefore without the waveform of transmitting test data, and by the comparison to the cycle in the waveform of valid data, can determine the benchmark of dividing waveform, realize simple.
Fig. 3 is the structural representation of a kind of device embodiment that resolves waveform provided by the invention.Embodiment illustrated in fig. 3 comprising:
The first acquisition module 302, be connected to processing module 301, for obtaining the pulse width Mi between i rising edge of waveform and i+1 the rising edge of described test data, and pulse width Ni between i negative edge and i+1 negative edge, i is the positive integer that is less than or equal to the summation of a and b;
The second acquisition module 303, is connected to the first acquisition module 302, for the waveform logical zero according to the described test data of obtaining in advance and the bit-order of logical one, utilizes pulse width Mi and pulse width Ni to obtain the cycle T 0 of logical zero and the cycle T 1 of logical one;
The 3rd acquisition module 305, is connected to judge module 304, if for pulse width Mi between cycle T 0 and cycle T 1, according to the pulse width between two adjacent negative edges, obtain successively each pulse width of the waveform of valid data; If pulse width Ni, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent rising edges, obtains each pulse width of the waveform of valid data successively;
Device embodiment provided by the invention, is coming presentation logic 0 and at 1 o'clock by the waveform of transmission different cycles, the cycle of obtaining in different ways test waveform, determine that the waveform that the waveform of valid data is used divides benchmark, and improve the accuracy of wave analysis.In addition, in the waveform of test data, the number of logical zero and logical one is all greater than 3, to reduce the deviation that in waveform transmitting procedure, wave form varies is brought; In the time calculating T0 or T1, can use multiple pulse width Mi and multiple pulse width Ni, to reduce the error of computation of Period.
Fig. 4 is the structural representation of the another kind of device embodiment that resolves waveform provided by the invention.Embodiment illustrated in fig. 4 comprising:
Device embodiment provided by the invention, coming presentation logic 0 and at 1 o'clock by the waveform of transmission different cycles, obtain in different ways the cycle of square-wave waveform, determine the waveform division benchmark that the waveform of valid data is wherein used, the accuracy that improves wave analysis.In the present embodiment, get in advance the cycle of logical zero and logical one, therefore without the waveform of transmitting test data, and by the comparison to the cycle in the waveform of valid data, can determine the benchmark of dividing waveform, realize simple.
Any process of otherwise describing in process flow diagram or at this or method are described and can be understood to, represent to comprise that one or more is for realizing module, fragment or the part of code of executable instruction of step of specific logical function or process, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can be not according to order shown or that discuss, comprise according to related function by the mode of basic while or by contrary order, carry out function, this should be understood by embodiments of the invention person of ordinary skill in the field.
Should be appreciated that each several part of the present invention can realize with hardware, software, firmware or their combination.In the above-described embodiment, multiple steps or method can realize with being stored in software or the firmware carried out in storer and by suitable instruction execution system.For example, if realized with hardware, the same in another embodiment, can realize by any one in following technology well known in the art or their combination: there is the discrete logic for data-signal being realized to the logic gates of logic function, there is the special IC of suitable combinational logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) etc.
Those skilled in the art are appreciated that realizing all or part of step that above-described embodiment method carries is can carry out the hardware that instruction is relevant by program to complete, described program can be stored in a kind of computer-readable recording medium, this program, in the time carrying out, comprises step of embodiment of the method one or a combination set of.
In addition, the each functional unit in each embodiment of the present invention can be integrated in a processing module, can be also that the independent physics of unit exists, and also can be integrated in a module two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.If described integrated module realizes and during as production marketing independently or use, also can be stored in a computer read/write memory medium using the form of software function module.
The above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
In the description of this instructions, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment within the scope of the invention in the situation that not departing from principle of the present invention and aim, modification, replacement and modification.Scope of the present invention is by claims and be equal to and limit.
Claims (6)
1. a method of resolving waveform, is characterized in that, comprising:
Receive sine waveform, described sine waveform is sampled, obtain square-wave waveform, wherein said square-wave waveform comprises the waveform of test data and the waveform of valid data successively, the waveform of wherein said test data comprises the waveform of the individual continuous logical zero of a consulting in advance and b continuous logical one, wherein a and b are the integer that is more than or equal to 3, and wherein the cycle T 0 of logical zero and the cycle T 1 of logical one are unequal;
Obtain the pulse width Mi between i rising edge and i+1 rising edge in the waveform of described test data, and pulse width Ni between i negative edge and i+1 negative edge, i is the positive integer that is less than or equal to the summation of a and b;
According to the bit-order of logical zero and logical one in the waveform of the described test data of obtaining in advance, utilize pulse width Mi and pulse width Ni to obtain the cycle T 0 of logical zero and the cycle T 1 of logical one;
Judge that pulse width Mi and pulse width Ni are whether between cycle T 0 and cycle T 1;
If pulse width Mi, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent negative edges, obtains each pulse width of the waveform of valid data successively; If pulse width Ni, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent rising edges, obtains each pulse width of the waveform of valid data successively;
After the each pulse width of waveform that obtains valid data, according to each pulse width of the waveform of the cycle T 1 of the cycle T 0 of logical zero and logical one and valid data, the bit that the waveform of parsing valid data represents.
2. method according to claim 1, is characterized in that, according to the bit-order of logical zero and logical one in the waveform of the described test data of obtaining in advance, utilizes pulse width Mi and pulse width Ni to obtain the cycle T 0 of logical zero and the cycle T 1 of logical one, comprising:
Obtain multiple pulse widths corresponding to logical zero in the waveform of test data, the multiple pulse widths corresponding to the logical zero getting are averaged, and obtain cycle T 0; And,
Obtain multiple pulse widths corresponding to logical one in the waveform of test data, the multiple pulse widths corresponding to the logical one getting are averaged, and obtain cycle T 1.
3. a method of resolving waveform, is characterized in that, comprising:
Steps A, reception sine waveform, sample to described sine waveform, obtains square-wave waveform;
Step B, obtain the pulse width Mi between i rising edge and i+1 rising edge in described square-wave waveform, and pulse width Ni between i negative edge and i+1 negative edge, i is positive integer;
Step C, judge that pulse width Mi and pulse width Ni are whether between the cycle T 0 of the logical zero obtaining in advance and the cycle T 1 of the logical one that obtains in advance, wherein cycle T 0 and cycle T 1 are unequal;
If step D pulse width Mi, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Ni, obtain the bit that described square-wave waveform represents; If pulse width Ni, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Mi, obtain the bit that described square-wave waveform represents;
If step e pulse width Mi and pulse width Ni be not all between cycle T 0 and cycle T 1, the value of upgrading i is i+1, execution step B.
4. a device of resolving waveform, is characterized in that, comprising:
Processing module, be used for receiving sine waveform, described sine waveform is sampled, obtain square-wave waveform, wherein said square-wave waveform comprises the waveform of test data and the waveform of valid data successively, the waveform of wherein said test data comprises the waveform of the individual continuous logical zero of a consulting in advance and b continuous logical one, and wherein a and b are the integer that is more than or equal to 3, and wherein the cycle T 0 of logical zero and the cycle T 1 of logical one are unequal;
The first acquisition module, for obtaining the pulse width Mi between i rising edge of waveform and i+1 the rising edge of described test data, and pulse width Ni between i negative edge and i+1 negative edge, i is the positive integer that is less than or equal to the summation of a and b;
The second acquisition module, for the waveform logical zero according to the described test data of obtaining in advance and the bit-order of logical one, utilizes pulse width Mi and pulse width Ni to obtain the cycle T 0 of logical zero and the cycle T 1 of logical one;
Judge module, for judging that pulse width Mi and pulse width Ni are whether between cycle T 0 and cycle T 1;
The 3rd acquisition module, if for pulse width Mi between cycle T 0 and cycle T 1, according to the pulse width between two adjacent negative edges, obtain successively each pulse width of the waveform of valid data; If pulse width Ni, between cycle T 0 and cycle T 1, according to the pulse width between two adjacent rising edges, obtains each pulse width of the waveform of valid data successively;
Parsing module, for after the each pulse width of waveform that obtains valid data, according to each pulse width of the waveform of the cycle T 1 of the cycle T 0 of logical zero and logical one and valid data, the bit that the waveform of parsing valid data represents.
5. device according to claim 4, is characterized in that:
Described the second acquisition module, for obtaining multiple pulse widths corresponding to waveform logical zero of test data, the multiple pulse widths corresponding to the logical zero getting are averaged, and obtain cycle T 0; And, obtain multiple pulse widths corresponding to logical one in the waveform of test data, the multiple pulse widths corresponding to the logical one getting are averaged, and obtain cycle T 1.
6. a device of resolving waveform, is characterized in that, comprising:
Processing module, for receiving sine waveform, samples to described sine waveform, obtains square-wave waveform;
Acquisition module, for obtaining the pulse width Mi between i rising edge of described square-wave waveform and i+1 rising edge, and pulse width Ni between i negative edge and i+1 negative edge, i is positive integer;
Judge module, for judging that pulse width Mi and pulse width Ni are whether between the cycle T 0 of the logical zero obtaining in advance and the cycle T 1 of the logical one that obtains in advance, wherein cycle T 0 and cycle T 1 are unequal;
Parsing module, if for pulse width Mi between cycle T 0 and cycle T 1, resolve described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Ni, obtain the bit that described square-wave waveform represents; If pulse width Ni, between cycle T 0 and cycle T 1, resolves described square-wave waveform according to the cycle T 1 of the cycle T 0 of logical zero and logical one and pulse width Mi, obtain the bit that described square-wave waveform represents;
Update module, if for pulse width Mi and pulse width Ni all not between cycle T 0 and cycle T 1, the value of upgrading i is i+1, triggers the operation of acquisition module.
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| CN106789517A (en) * | 2017-01-08 | 2017-05-31 | 易晓云 | CAN data link and its by turn loss arbitration method |
| CN106911334A (en) * | 2017-02-28 | 2017-06-30 | 四川赛科安全技术有限公司 | A kind of fire-fighting industrial bus coding method |
| CN111467643A (en) * | 2020-03-20 | 2020-07-31 | 肖赫 | Sleep aiding method and device, computer equipment and storage medium |
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| CN103811021B (en) | 2016-12-07 |
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