CN103788736A - Composition for insulating layer and method for preparing insulating layer on through silicon via of silicon wafer - Google Patents
Composition for insulating layer and method for preparing insulating layer on through silicon via of silicon wafer Download PDFInfo
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- CN103788736A CN103788736A CN201410017166.4A CN201410017166A CN103788736A CN 103788736 A CN103788736 A CN 103788736A CN 201410017166 A CN201410017166 A CN 201410017166A CN 103788736 A CN103788736 A CN 103788736A
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Abstract
The invention relates to a composition for an insulating layer and a method for preparing the insulating layer on a through silicon via of a silicon wafer. The composition for the insulating layer comprises the following components in parts by mass: 100 parts of diluting agent, 2 to 10 parts of phenolic resin, 0.3 to 1.0 part of thickening agent, 5 to 15 parts of cross-linking agent and 1 to 5 parts of white carbon black. The composition for the insulating layer is prepared from the diluting agent, the phenolic resin, the thickening agent, the cross-linking agent and the white carbon black at a proper ratio, and has proper viscosity, so that good film forming property is ensured, the three-dimensional forming of the composition for the insulating layer is facilitated, and the insulating layer prepared in the through silicon via is high in conformality; moreover, the insulating layer prepared from the composition for the insulating layer in the through silicon via is proven by experiments to be low in dielectric constant and moisture absorption.
Description
Technical field
The present invention relates to Electronic Packaging insulation layer technical field, particularly relate to a kind of composition for insulating layer and on the silicon through hole of Silicon Wafer, prepare the method for insulation layer.
Background technology
In recent years, the three-dimensional packaging technology of unicircuit is considered to meet Moore's Law and even realizes the optimal path that surmounts Moore's Law.Therefore, the industrialization of silicon through hole (TSV) technology in three-dimension packaging and complete processing procedure just seems particularly important.At present, silicon through hole processing procedure below depth-to-width ratio 5:1 has possessed the possibility of volume production, and the silicon through hole interconnection technique of especially lower depth-to-width ratio is at CMOS(Complementary Metal-Oxide Semiconductor) the field of image sensors application that succeeds.Wherein, silicon through hole interconnection technique comprises the important process such as via etch, through hole insulation, seed layer deposition, electroplated lead layer, consent, but through hole insulation is considered to basic and the most crucial processing step.Insulation layer in traditional integrated circuit technology is generally by chemical gaseous phase depositing process (CVD) preparation, the silicon dioxide layer forming by this method has higher specific inductivity (being generally greater than 4.0), makes the delay of the mutual attach signal transmission that stray capacitance causes comparatively serious.In addition, the silicon dioxide layer forming by CVD and the bonding force of silicon base are poor, easily cause that product yield reduces, and increases cost; Meanwhile, expensive for the vacuum coating film equipment of vapour deposition, greatly limit the scale of mass production of this technology.
Therefore, exploitation is used for the composition for insulating layer of the low-k of silicon through hole insulation making, and realizes the stereo shaping of this composition for insulating layer by suitable complete processing, prepares the insulation layer that specific inductivity is low and have great importance on Silicon Wafer.
Summary of the invention
Based on this, be necessary to provide a kind of composition for insulating layer of good film-forming property, with on the silicon through hole at Silicon Wafer, prepare that specific inductivity is low, conformality is good insulation layer.
Further, provide a kind of method of preparing insulation layer on the silicon through hole of Silicon Wafer.
A kind of composition for insulating layer, by mass parts, comprises
Thinner: 100 parts;
Resol: 2 parts～10 parts;
Tackifier: 0.3 part～1.0 parts;
Linking agent: 5 parts～15 parts; And
White Carbon black: 1 part～5 parts.
In an embodiment, described thinner is selected from least one in methacrylic acid hydroxyl butyl ester, dimethyl allene dimethyl phthalate, n-Butyl lactate, propylene glycol monomethyl ether, propandiol butyl ether and methyl lactate therein.
In an embodiment, described resol is selected from least one in linear phenolic resin, linear o-cresol formaldehyde resin, linear meta-cresol urea formaldehyde, linear p-cresol urea formaldehyde and linear para-tert-butyl phenolic resin therein.
In an embodiment, described resol weight-average molecular weight is 800～2000 therein.
In an embodiment, described tackifier are selected from least one in silane coupling agent KH-560, silane resin acceptor kh-550 and silane coupling A DP therein.
In an embodiment, described linking agent is selected from least one in butylated amino resin, methyl-etherified aminoresin and mixed etherified amino resins therein.
In an embodiment, described White Carbon black is that particle diameter is the spherical white carbon black of 10 nanometer～150 nanometers therein.
In an embodiment, the viscosity of described composition for insulating layer is not higher than 20mPa*s therein.
A method of preparing insulation layer on the silicon through hole of Silicon Wafer, comprises the steps:
The Silicon Wafer that contains silicon through hole is provided, adopts spraying coating process on described Silicon Wafer, to spray above-mentioned composition for insulating layer, form the presoma of insulation layer at the bottom of the surface of described Silicon Wafer and the hole wall of described silicon through hole and hole; And
The presoma of described insulation layer is toasted, then the presoma of the described insulation layer after baking is carried out to heat treated the presoma of described insulation layer is solidified, on the described Silicon Wafer that contains silicon through hole, form insulation layer.
In an embodiment, described employing spraying coating process sprays in the operation of above-mentioned composition for insulating layer on described Silicon Wafer therein, and the temperature of described Silicon Wafer is maintained to 70 ℃～110 ℃.
In an embodiment, the temperature of described baking is 90 ℃～120 ℃ therein, and the time of baking is 3 minutes～7 minutes.
In an embodiment, the described presoma to the described insulation layer after baking carries out heat treated is specially the curing operation of presoma of described insulation layer: the presoma of the described insulation layer after baking is kept keeping keeping 0.5 hour～1 hour at 0.5 hour～1 hour and 180 ℃ at 0.5 hour～1 hour, 150 ℃ successively at 120 ℃ therein.
In an embodiment, at the bottom of the hole of described silicon through hole, diameter is 30 microns～70 microns therein, and hole depth is 90 microns～200 microns, and depth-to-width ratio is less than or equal to 5:1, and the angle at the bottom of hole wall and hole is 90 °～130 °.
The above-mentioned composition for insulating layer that thinner, resol, tackifier, linking agent and white carbon black obtain by suitable proportioning has suitable viscosity, thereby there is good film-forming properties, be conducive to the stereo shaping of composition for insulating layer, in the silicon through hole of Silicon Wafer, prepare the insulation layer that conformality is good.And, the experiment proved that, adopt the specific inductivity of the insulation layer that above-mentioned composition for insulating layer prepared on Silicon Wafer lower, and rate of moisture absorption is lower.
Accompanying drawing explanation
Fig. 1 is the schema of preparing the method for insulation layer on the silicon through hole of Silicon Wafer of an embodiment;
Fig. 2 is the SEM figure in the cross section of preparing the sample that insulation layer obtains on the silicon through hole of Silicon Wafer of embodiment 1;
Fig. 3 is the SEM figure in the cross section of preparing the sample that insulation layer obtains on the silicon through hole of Silicon Wafer of embodiment 2.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.A lot of details are set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar improvement without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public concrete enforcement.
The composition for insulating layer of one embodiment, by mass parts, comprising:
1 part～5 parts of 100 parts of thinners, 2 parts～10 parts, resol, 0.3 part～1.0 parts of tackifier, 5 parts～15 parts of linking agents and white carbon blacks.
This composition for insulating layer is for the preparation of the insulation layer on the Silicon Wafer of unicircuit.
Thinner is selected from least one in methacrylic acid hydroxyl butyl ester, dimethyl allene dimethyl phthalate, n-Butyl lactate, propylene glycol monomethyl ether, propandiol butyl ether and methyl lactate.
Resol has good insulating property, and has a large amount of polar groups, is convenient to improve the adhesive property of insulation layer to silicon wafer, avoids insulation layer come off and cause the reduction of the yield of electronic product from silicon wafer.
Preferably, resol is selected from least one in linear phenolic resin, linear o-cresol formaldehyde resin, linear meta-cresol urea formaldehyde, linear p-cresol urea formaldehyde and linear para-tert-butyl phenolic resin.
Linear phenolic resin, linear o-cresol formaldehyde resin, linear meta-cresol urea formaldehyde, linear p-cresol urea formaldehyde and linear para-tert-butyl phenolic resin all can be dissolved in above-mentioned thinner at normal temperatures, without heating dissolution, the energy consumption that makes to prepare insulation layer is lower.
Weight-average molecular weight is less than the cured article poor heat resistance of 800 resol, and the cured article fragility that weight-average molecular weight is greater than 2000 resol is large, thereby is difficult to guarantee the stability of the insulation layer of being prepared by this composition for insulating layer.Therefore, it is 800～2000 resol that resol is preferably weight-average molecular weight, makes the stability of insulation layer better, is conducive to improve the yield of electron device.
Tackifier are selected from least one in silane coupling agent KH-560, silane resin acceptor kh-550 and silane coupling A DP.
At least one in silane coupling agent KH-560, silane resin acceptor kh-550 and the silane coupling A DP of 0.3 part～1.0 parts can improve the adhesive property at the bottom of hole wall and the hole of the surface of insulation layer to Silicon Wafer, silicon through hole.
Linking agent is selected from least one in butylated amino resin, methyl-etherified aminoresin and mixed etherified amino resins.The effect of linking agent is to make each component be cross-linked into stable network structure, to obtain the insulation layer that thermotolerance is higher and dielectric properties are excellent.
White Carbon black has strengthening action, for reducing the thermal expansivity of insulation layer, improves the yield of integral device.White carbon black preferable particle size is the spherical white carbon black of 10 nanometer～150 nanometers, and the reinforcing effect of the white carbon black of this particle diameter is better, uses less amount can obtain reinforcing effect preferably, reduces raw materials cost.
By being carried out to rational proportion, thinner, resol, tackifier, linking agent and white carbon black obtain above-mentioned composition for insulating layer.This composition for insulating layer there is suitable viscosity, thereby there is good film-forming properties, can be for convenience of forming insulation layer at the bottom of the hole wall of the surface at Silicon Wafer, silicon through hole and hole.
Preferably, adopt suitable proportioning to make the viscosity of above-mentioned composition for insulating layer not higher than 20mPa*s, make the film-forming properties of this composition for insulating layer better, be conducive to the stereo shaping of this composition for insulating layer, can meet the requirement of spraying coating process, can adopt spraying coating process to form insulation layer, thereby can realize high shape-preserving coating following to depth-to-width ratio 5:1, difform silicon through hole.
Our experiments show that, the specific inductivity of the insulation layer of being prepared by this composition for insulating layer is lower, is conducive to avoid the delay of the mutual attach signal transmission that stray capacitance causes.
Our experiments show that, the water absorbability of the insulation layer of being prepared by this composition for insulating layer is lower, makes the stability of this insulation layer better.
Preferably, composition for insulating layer, by mass parts, comprising:
3 parts of 100 parts of thinners, 10 parts, resol, 0.3 part of tackifier, 9 parts of linking agents and white carbon blacks.
While preparing above-mentioned composition for insulating layer, thinner, resol, tackifier, linking agent and white carbon black are mixed at normal temperatures by said ratio, and stir.Preparation method is simple, dissolves without heat, and energy consumption is low, and preparation cost is low.
Refer to Fig. 1, the method for preparing insulation layer on the silicon through hole of Silicon Wafer of an embodiment, comprises the steps S110 and step S120.
Step S110: the Silicon Wafer that contains silicon through hole is provided, adopts spraying coating process to spray above-mentioned composition for insulating layer on Silicon Wafer, form the presoma of insulation layer at the bottom of the surface of Silicon Wafer and the hole wall of silicon through hole and hole.
Silicon Wafer is the Silicon Wafer that contains silicon through hole.Silicon through hole can be three-dimensional perpendicular duct or three-dimensional tilt duct.At the bottom of the hole of the silicon through hole of the Silicon Wafer that contains silicon through hole, diameter is 30 microns～70 microns, and hole depth is 90 microns～200 microns, and depth-to-width ratio is less than or equal to 5:1, and the angle at the bottom of hole wall and hole is 90 °～130 °.
Before spraying, also comprise Silicon Wafer is cleaned and dry operation, with pollutents such as the dusts on removing at the bottom of the hole wall of the surface of Silicon Wafer and different shapes, different form ratios and hole.Preferably, using plasma or ultrasonic cleaning Silicon Wafer, with the pollutent on fully removing at the bottom of hole wall and hole, obtain the wafer in the free of contamination TSV of containing duct.
Adopt spraying coating process on cleaning, dry Silicon Wafer, to spray above-mentioned composition for insulating layer, be formed with uniform composition for insulating layer rete on making at the bottom of the hole wall of surface, silicon through hole of Silicon Wafer and hole.
Preferably, in spraying process, the temperature of Silicon Wafer maintains 70 ℃～110 ℃, and the thinner in composition for insulating layer is volatilized fast, forms fast the composition for insulating layer rete of high conformal.
Spraying coating process has the features such as level of automation is high, efficiency is high, homogeneity is good, cost is low.Especially in the Silicon Wafer insulation layer preparation technology who contains low depth-to-width ratio TSV duct, adopt the insulation layer of spraying preparation also to possess high conformality feature, for follow-up silicon perforation processing procedure is had laid a good foundation.
Step S120: the presoma of insulation layer is toasted, then the presoma of the insulation layer after baking is carried out to heat treated the presoma of insulation layer is solidified, form insulation layer on the Silicon Wafer that contains silicon through hole.
The presoma of insulation layer is carried out heat treated make insulation layer presoma solidify before, first the presoma of insulation layer is toasted, be conducive to improve the high conformality of insulation layer.
Preferably, the temperature of baking is 90 ℃～120 ℃, and the time of baking is 3 minutes～7 minutes.
Presoma to the insulation layer after baking carries out heat treated, be heated to 120 ℃ by room temperature, at 120 ℃, keep 0.5 hour～1 hour, be heated to 150 ℃ by 120 ℃, at 150 ℃, keep 0.5 hour～1 hour, be heated to 180 ℃ by 150 ℃, at 180 ℃, be incubated 0.5 hour～1 hour, then be cooled to room temperature by 180 ℃, the presoma of insulation layer is solidified, at the bottom of the hole wall of the surface of Silicon Wafer, silicon through hole and hole, form insulation layer.
The temperature rise rate of heating is preferably 4 ℃, and the speed of cooling is preferably 4 ℃.Adopt above-mentioned curing that the presoma of insulation layer is solidified, the height of the insulation layer of formation guarantor property is good.Comprise heating-up time and temperature fall time, be 3 hours～7 hours set time.
Because above-mentioned composition for insulating layer comprises properly mixed thinner, resol, tackifier, linking agent and white carbon black, the character of this composition for insulating layer itself makes the solidification value of presoma of this insulation layer lower, only up to 180 ℃, be conducive to reduce the energy consumption of silicon perforation processing procedure.
Adopt spraying coating process and above-mentioned program curing to prepare insulation layer, can control preferably the thickness of insulation layer, make the conformality of insulation layer better.
The above-mentioned method of preparing insulation layer on the silicon through hole of Silicon Wafer is simple to operate, reproducible, have the advantages that high guarantor property applies, the specific inductivity of prepared insulation layer is lower at the bottom of the hole wall of the surface of Silicon Wafer, silicon through hole and hole, rate of moisture absorption is lower, good stability, lays a good foundation for subsequent technique, is conducive to improve the yield of the three-dimensional integrated device of semi-conductor.
Further set forth by specific embodiment below.
Embodiment 1
Prepare composition for insulating layer and prepare insulation layer on the silicon through hole of Silicon Wafer
1, prepare composition for insulating layer
By mass parts, the spherical white carbon black that the linear o-cresol formaldehyde resin that is 800 by 20 parts of propylene glycol monomethyl ethers, 80 parts of ethyl lactates, 9 parts of weight-average molecular weight, 0.5 part of silylation coupling agent KH-550,8 parts of butylated amino resins and 2 parts of particle diameters are 40 nanometers is uniformly mixed and obtains composition for insulating layer.
2, on the silicon through hole of Silicon Wafer, prepare insulation layer
(1) provide the Silicon Wafer that contains silicon through hole, this silicon through hole is three-dimensional perpendicular hole, and at the bottom of hole, diameter is 65 microns, 130 microns of hole depths (depth-to-width ratio 2:1); This Silicon Wafer that contains silicon through hole is cleaned and is dried with plasma body;
(2) this cleaning, the dry Silicon Wafer that contains silicon through hole are heated to 70 ℃, and maintain 70 ℃, adopt spraying coating process that the above-mentioned composition for insulating layer being prepared into is sprayed on this Silicon Wafer that contains silicon through hole, on making at the bottom of the hole wall of surface, silicon through hole of Silicon Wafer and hole, be formed with uniform composition for insulating layer rete, on Silicon Wafer, form the presoma of insulation layer;
(3) sample step (2) being obtained toasts after 7 minutes and carries out heat treated at 90 ℃, being operating as of heat treated heated the sample after baking, and at 120 ℃, 150 ℃ and 180 ℃, be cured successively, at three temperature, keep 0.5 hour respectively, be cooled to after room temperature in 180 ℃, on Silicon Wafer, form insulation layer, at the bottom of the surface of insulation layer covering Silicon Wafer, the hole wall and hole in three-dimensional perpendicular hole.Wherein, the temperature rise rate of heating is 4 ℃/min, and rate of temperature fall is 4 ℃/min.
The SEM figure in the cross section of preparing the sample that insulation layer obtains on the silicon through hole of Silicon Wafer of the present embodiment 1 is shown in Fig. 2.As seen from Figure 2, the conformality of insulation layer is better.
Embodiment 2
Prepare composition for insulating layer and prepare insulation layer on the silicon through hole of Silicon Wafer
1, prepare composition for insulating layer
By mass parts, the spherical white carbon black that the linear para-tert-butyl phenolic resin that is 1000 by 40 parts of propylene glycol monomethyl ethers, 60 parts of ethyl lactates, 10 parts of weight-average molecular weight, 0.4 part of silylation coupling agent KH-550,11 parts of butylated amino resins and 3 parts of particle diameters are 40 nanometers is uniformly mixed and obtains composition for insulating layer.
2, on the silicon through hole of Silicon Wafer, prepare insulation layer
(1) provide the Silicon Wafer that contains silicon through hole, the silicon through hole of this Silicon Wafer is three-dimensional perpendicular hole, and at the bottom of hole, diameter is 33 microns, 100 microns of hole depths (depth-to-width ratio 3:1); This Silicon Wafer that contains silicon through hole is cleaned and is dried with plasma body;
(2) this cleaning, the dry Silicon Wafer that contains silicon through hole are heated to 80 ℃, and maintain 80 ℃, adopt spraying coating process that the above-mentioned composition for insulating layer being prepared into is sprayed on this Silicon Wafer that contains silicon through hole, on making at the bottom of the hole wall of surface, silicon through hole of Silicon Wafer and hole, be formed with uniform composition for insulating layer rete, on Silicon Wafer, form the presoma of insulation layer;
(3) sample step (2) being obtained toasts after 3 minutes and carries out heat treated at 120 ℃, being operating as of heat treated heated the sample after baking, and at 120 ℃, 150 ℃ and 180 ℃, be cured successively, at 120 ℃, keep 1 hour, at 150 ℃, keep 0.5 hour, at 180 ℃, keep 0.5 hour, be cooled to after room temperature in 180 ℃, on Silicon Wafer, form insulation layer, at the bottom of the surface of insulation layer covering Silicon Wafer, the hole wall and hole in three-dimensional perpendicular hole.Wherein, the temperature rise rate of heating is 4 ℃/min, and rate of temperature fall is 4 ℃/min.
Embodiment 3
Prepare composition for insulating layer and prepare insulation layer on the silicon through hole of Silicon Wafer
1, prepare composition for insulating layer
By mass parts, the spherical white carbon black that the linearity that is 1200 by 50 parts of propylene glycol monomethyl ethers, 50 parts of ethyl lactates, 10 parts of weight-average molecular weight is 30 nanometers to sylvan urea formaldehyde, 0.3 part of silylation coupling agent ADP, 9 parts of methyl-etherified aminoresin and 3 parts of particle diameters is uniformly mixed and obtains composition for insulating layer.
2, on the silicon through hole of Silicon Wafer, prepare insulation layer
(1) provide the Silicon Wafer that contains silicon through hole, the silicon through hole of this Silicon Wafer is three-dimensional tilt hole, and at the bottom of hole, diameter is 70 microns, 90 microns of hole depths (angle forming at the bottom of hole wall and hole is 100 °); This Silicon Wafer that contains silicon through hole is cleaned and is dried with plasma body;
(2) this cleaning, the dry Silicon Wafer that contains silicon through hole are heated to 100 ℃, and maintain 100 ℃, adopt spraying coating process that the above-mentioned composition for insulating layer being prepared into is sprayed on this Silicon Wafer that contains silicon through hole, on making at the bottom of the hole wall of surface, silicon through hole of Silicon Wafer and hole, be formed with uniform composition for insulating layer rete, on Silicon Wafer, form the presoma of insulation layer;
(3) sample step (2) being obtained toasts after 5 minutes and carries out heat treated at 105 ℃, being operating as of heat treated heated the sample after baking, and at 120 ℃, 150 ℃ and 180 ℃, be cured successively, at 120 ℃, keep 0.5 hour, at 150 ℃, keep 1 hour, at 180 ℃, keep 0.5 hour, be cooled to after room temperature in 180 ℃, on Silicon Wafer, form insulation layer, at the bottom of the surface of insulation layer covering Silicon Wafer, the hole wall and hole in three-dimensional tilt hole.Wherein, the temperature rise rate of heating is 4 ℃/min, and rate of temperature fall is 4 ℃/min.
The SEM figure in the cross section of preparing the sample that insulation layer obtains on the silicon through hole of Silicon Wafer of the present embodiment 3 is shown in Fig. 3.As seen from Figure 3, the conformality of insulation layer is better.
Embodiment 4
Prepare composition for insulating layer and prepare insulation layer on the silicon through hole of Silicon Wafer
1, prepare composition for insulating layer
By mass parts, the spherical white carbon black that the linearity that is 1500 by 60 parts of propylene glycol monomethyl ethers, 40 parts of ethyl lactates, 8 parts of weight-average molecular weight is 30 nanometers to sylvan urea formaldehyde, 0.5 part of silylation coupling agent KH-560,12 parts of methyl-etherified aminoresin and 5 parts of particle diameters is uniformly mixed and obtains composition for insulating layer.
2, on the silicon through hole of Silicon Wafer, prepare insulation layer
(1) provide the Silicon Wafer that contains silicon through hole, the silicon through hole of this Silicon Wafer is three-dimensional perpendicular hole, and at the bottom of hole, diameter is 30 microns, 150 microns of hole depths (depth-to-width ratio 5:1); This Silicon Wafer that contains silicon through hole is cleaned and is dried with plasma body;
(2) this cleaning, the dry Silicon Wafer that contains silicon through hole are heated to 70 ℃, and maintain 70 ℃, adopt spraying coating process that the above-mentioned composition for insulating layer being prepared into is sprayed on this Silicon Wafer that contains silicon through hole, on making at the bottom of the hole wall of surface, silicon through hole of Silicon Wafer and hole, be formed with uniform composition for insulating layer rete, on Silicon Wafer, form the presoma of insulation layer;
(3) sample step (2) being obtained toasts after 4 minutes and carries out heat treated at 110 ℃, being operating as of heat treated heated the sample after baking, and at 120 ℃, 150 ℃ and 180 ℃, be cured successively, at 120 ℃, keep 1 hour, at 150 ℃, keep 1 hour, at 180 ℃, keep 1 hour, be cooled to after room temperature in 180 ℃, on Silicon Wafer, form insulation layer, at the bottom of the surface of insulation layer covering Silicon Wafer, the hole wall and hole in three-dimensional perpendicular hole.Wherein, the temperature rise rate of heating is 4 ℃/min, and rate of temperature fall is 4 ℃/min.
Embodiment 5
Prepare composition for insulating layer and prepare insulation layer on the silicon through hole of Silicon Wafer
1, prepare composition for insulating layer
By mass parts, the spherical white carbon black that linear meta-cresol urea formaldehyde that the linear phenolic resin that is 2000 by 100 parts of methacrylic acid hydroxyl butyl esters, 1 part of weight-average molecular weight and 1 part of weight-average molecular weight are 2000,0.3 part of silylation coupling agent KH-560,5 parts of mixed etherified amino resins and 1 part of particle diameter are 80 nanometers is uniformly mixed and obtains composition for insulating layer.
2, on the silicon through hole of Silicon Wafer, prepare insulation layer
(1) provide the Silicon Wafer that contains silicon through hole, the silicon through hole of this Silicon Wafer is three-dimensional tilt hole, and at the bottom of hole, diameter is 50 microns, 80 microns of hole depths (angle forming at the bottom of hole wall and hole is 120 °); This Silicon Wafer that contains silicon through hole is cleaned and is dried by ultrasonic wave;
(2) this cleaning, the dry Silicon Wafer that contains silicon through hole are heated to 110 ℃, and maintain 110 ℃, adopt spraying coating process that the above-mentioned composition for insulating layer being prepared into is sprayed on this Silicon Wafer that contains silicon through hole, on making at the bottom of the hole wall of surface, silicon through hole of Silicon Wafer and hole, be formed with uniform composition for insulating layer rete, on Silicon Wafer, form the presoma of insulation layer;
(3) sample step (2) being obtained toasts after 6 minutes and carries out heat treated at 95 ℃, being operating as of heat treated heated the sample after baking, and at 120 ℃, 150 ℃ and 180 ℃, be cured successively, at 120 ℃, keep 0.8 hour, at 150 ℃, keep 1 hour, at 180 ℃, keep 0.9 hour, be cooled to after room temperature in 180 ℃, on Silicon Wafer, form insulation layer, at the bottom of the surface of insulation layer covering Silicon Wafer, the hole wall and hole in three-dimensional tilt hole.Wherein, the temperature rise rate of heating is 4 ℃/min, and rate of temperature fall is 4 ℃/min.
Embodiment 6
Prepare composition for insulating layer and prepare insulation layer on the silicon through hole of Silicon Wafer
1, prepare composition for insulating layer
By mass parts, the spherical white carbon black that the linear phenolic resin that is 1200 by 30 parts of dimethyl allene dimethyl phthalates, 70 parts of propandiol butyl ethers, 5 parts of weight-average molecular weight, 0.6 part of silylation coupling agent KH-560,0.4 part of silylation coupling agent ADP, 15 parts of mixed etherified amino resins and 4 parts of particle diameters are 10 nanometers is uniformly mixed and obtains composition for insulating layer.
2, on the silicon through hole of Silicon Wafer, prepare insulation layer
(1) provide the Silicon Wafer that contains silicon through hole, the silicon through hole of this Silicon Wafer is three-dimensional perpendicular hole, and at the bottom of hole, diameter is 30 microns, 120 microns of hole depths (depth-to-width ratio 4:1); This Silicon Wafer that contains silicon through hole is cleaned and is dried with plasma body;
(2) this cleaning, the dry Silicon Wafer that contains silicon through hole are heated to 80 ℃, and maintain 80 ℃, adopt spraying coating process that the above-mentioned composition for insulating layer being prepared into is sprayed on this Silicon Wafer that contains silicon through hole, make to be formed with uniform composition for insulating layer rete on the hole wall of surface, silicon through hole of Silicon Wafer and bottom, on Silicon Wafer, form the presoma of insulation layer;
(3) sample step (2) being obtained toasts after 3.5 minutes and carries out heat treated at 115 ℃, being operating as of heat treated heated the sample after baking, and at 120 ℃, 150 ℃ and 180 ℃, be cured successively, at 120 ℃, keep 1 hour, at 150 ℃, keep 0.5 hour, at 180 ℃, keep 0.5 hour, be cooled to after room temperature in 180 ℃, on Silicon Wafer, form insulation layer, at the bottom of the surface of insulation layer covering Silicon Wafer, the hole wall and hole in three-dimensional perpendicular hole.Wherein, the temperature rise rate of heating is 4 ℃/min, and rate of temperature fall is 4 ℃/min.
Embodiment 7
Prepare composition for insulating layer and prepare insulation layer on the silicon through hole of Silicon Wafer
1, prepare composition for insulating layer
By mass parts, the spherical white carbon black that the linear meta-cresol urea formaldehyde that is 1800 by 100 parts of propandiol butyl ethers, 3 parts of weight-average molecular weight, 0.8 part of silylation coupling agent ADP, 7 parts of butylated amino resins and 5 parts of particle diameters are 150 nanometers is uniformly mixed and obtains composition for insulating layer.
2, on the silicon through hole of Silicon Wafer, prepare insulation layer
(1) provide the Silicon Wafer that contains silicon through hole, the silicon through hole of this Silicon Wafer is three-dimensional perpendicular hole, and aperture is 60 microns, 120 microns of hole depths (depth-to-width ratio 2:1); This Silicon Wafer that contains silicon through hole is cleaned and is dried with plasma body;
(2) this cleaning, the dry Silicon Wafer that contains silicon through hole are heated to 95 ℃, and maintain 95 ℃, adopt spraying coating process that the above-mentioned composition for insulating layer being prepared into is sprayed on this Silicon Wafer that contains silicon through hole, on making at the bottom of the hole wall of surface, silicon through hole of Silicon Wafer and hole, be formed with uniform composition for insulating layer rete, on Silicon Wafer, form the presoma of insulation layer;
(3) sample step (2) being obtained toasts after 7 minutes and carries out heat treated at 90 ℃, being operating as of heat treated heated the sample after baking, and at 120 ℃, 150 ℃ and 180 ℃, be cured successively, at 120 ℃, keep 1 hour, at 150 ℃, keep 0.8 hour, at 180 ℃, keep 0.8 hour, be cooled to after room temperature in 180 ℃, on Silicon Wafer, form insulation layer, at the bottom of the surface of insulation layer covering Silicon Wafer, the hole wall and hole in three-dimensional perpendicular hole.Wherein, the temperature rise rate of heating is 4 ℃/min, and rate of temperature fall is 4 ℃/min.
The component of the composition for insulating layer of embodiment 1～embodiment 7 sees the following form 1
The component of the composition for insulating layer of table 1 embodiment 1～embodiment 7
Specific inductivity and the rate of moisture absorption of the viscosity of the composition for insulating layer of embodiment 1～embodiment 7, film forming complexity, insulation layer see the following form 2.
Specific inductivity and the rate of moisture absorption of table 2 viscosity, film forming complexity, insulation layer
| Embodiment | Viscosity (mPa*s) | Film forming complexity | Rate of moisture absorption | Specific inductivity |
| Embodiment 1 | 5.42 | Easily | 1.65 | 3.54 |
| Embodiment 2 | 9.21 | Easily | 1.45 | 3.70 |
| Embodiment 3 | 7.23 | Easily | 1.56 | 3.48 |
| Embodiment 4 | 8.09 | Easily | 1.78 | 3.89 |
| Embodiment 5 | 2.74 | Easily | 1.25 | 3.36 |
| Embodiment 6 | 4.25 | Easily | 1.89 | 3.95 |
| Embodiment 7 | 5.34 | Easily | 1.56 | 3.67 |
As seen from Table 2, the composition for insulating layer film forming of embodiment 1～embodiment 7 is comparatively easy, the technique that forms the insulation layer at the bottom of hole wall and the hole that covers silicon wafer surface, silicon through hole on the Silicon Wafer that is containing silicon through hole through spraying coating process by polymer composition is comparatively simple, and the conformality of this insulation layer is good, specific inductivity and rate of moisture absorption lower.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (13)
1. a composition for insulating layer, is characterized in that, by mass parts, comprises
Thinner: 100 parts;
Resol: 2 parts～10 parts;
Tackifier: 0.3 part～1.0 parts;
Linking agent: 5 parts～15 parts; And
White Carbon black: 1 part～5 parts.
2. composition for insulating layer according to claim 1, is characterized in that, described thinner is selected from least one in methacrylic acid hydroxyl butyl ester, dimethyl allene dimethyl phthalate, n-Butyl lactate, propylene glycol monomethyl ether, propandiol butyl ether and methyl lactate.
3. composition for insulating layer according to claim 1, it is characterized in that, described resol is selected from least one in linear phenolic resin, linear o-cresol formaldehyde resin, linear meta-cresol urea formaldehyde, linear p-cresol urea formaldehyde and linear para-tert-butyl phenolic resin.
4. composition for insulating layer according to claim 1, is characterized in that, described resol weight-average molecular weight is 800～2000.
5. composition for insulating layer according to claim 1, is characterized in that, described tackifier are selected from least one in silane coupling agent KH-560, silane resin acceptor kh-550 and silane coupling A DP.
6. composition for insulating layer according to claim 1, is characterized in that, described linking agent is selected from least one in butylated amino resin, methyl-etherified aminoresin and mixed etherified amino resins.
7. composition for insulating layer according to claim 1, is characterized in that, described White Carbon black is that particle diameter is the spherical white carbon black of 10 nanometer～150 nanometers.
8. composition for insulating layer according to claim 1, is characterized in that, the viscosity of described composition for insulating layer is not higher than 20mPa*s.
9. a method of preparing insulation layer on the silicon through hole of Silicon Wafer, comprises the steps:
The Silicon Wafer that contains silicon through hole is provided, adopt spraying coating process on described Silicon Wafer, spray the composition for insulating layer as described in claim 1～8 any one, form the presoma of insulation layer at the bottom of the hole wall of the surperficial and described silicon through hole of described Silicon Wafer and hole; And
The presoma of described insulation layer is toasted, then the presoma of the described insulation layer after baking is carried out to heat treated the presoma of described insulation layer is solidified, on the described Silicon Wafer that contains silicon through hole, form insulation layer.
10. the method for preparing insulation layer on the silicon through hole of Silicon Wafer according to claim 9, it is characterized in that, described employing spraying coating process sprays in the operation of the composition for insulating layer as described in claim 1～8 any one on described Silicon Wafer, and the temperature of described Silicon Wafer is maintained to 70 ℃～110 ℃.
11. methods of preparing insulation layer on the silicon through hole of Silicon Wafer according to claim 9, is characterized in that, the temperature of described baking is 90 ℃～120 ℃, and the time of baking is 3 minutes～7 minutes.
12. methods of preparing insulation layer on the silicon through hole of Silicon Wafer according to claim 9, it is characterized in that, the described presoma to the described insulation layer after baking carries out heat treated is specially the curing operation of presoma of described insulation layer: the presoma of the described insulation layer after baking is kept keeping keeping 0.5 hour～1 hour at 0.5 hour～1 hour and 180 ℃ at 0.5 hour～1 hour, 150 ℃ successively at 120 ℃.
13. methods of preparing insulation layer on the silicon through hole of Silicon Wafer according to claim 9, it is characterized in that, at the bottom of the hole of described silicon through hole, diameter is 30 microns～70 microns, and hole depth is 90 microns～200 microns, depth-to-width ratio is less than or equal to 5:1, and the angle at the bottom of hole wall and hole is 90 °～130 °.
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