CN103782393A - 肖特基二极管 - Google Patents
肖特基二极管 Download PDFInfo
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- CN103782393A CN103782393A CN201280044080.XA CN201280044080A CN103782393A CN 103782393 A CN103782393 A CN 103782393A CN 201280044080 A CN201280044080 A CN 201280044080A CN 103782393 A CN103782393 A CN 103782393A
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Abstract
本发明总体上涉及一种肖特基二极管,所述肖特基二极管具有衬底、在所述衬底上所提供的漂移层和在所述漂移层的有源区域上所提供的肖特基层。选择用于所述肖特基层的金属以及用于所述漂移层的半导体材料,用以在所述漂移层和所述肖特基层之间提供低位垒高度肖特基结。
Description
对相关申请的交叉引用
本申请与同此同时提交的题为“EDGE TERMINATION STRUCTURE EMPLOYING RECESSES FOR EDGE TERMINATION ELEMENTS”的美国实用专利申请号 相关;并且与同此同时提交的题为“SCHOTTKY DIODE EMPLOYING RECESSES FOR ELEMENTS OF JUNCTION BARRIER ARRAY”的美国实用专利申请号 相关,其公开通过引用整体被结合于此。
技术领域
本公开涉及半导体器件。
背景技术
肖特基二极管利用金属半导体结,其提供肖特基位垒并且在金属层和掺杂半导体层之间被产生。对于具有N型半导体层的肖特基二极管,金属层充当阳极,并且N型半导体层充当阴极。通常,肖特基二极管通过容易地在正向偏置方向上传递电流和在反向偏置方向上阻断电流而像传统p-n二极管一样起作用。在金属半导体结处所提供的肖特基位垒提供优于p-n二极管的两个独特优点。首先,所述肖特基位垒与较低位垒高度相关联,所述较低位垒高度与较低正向电压降相互关联。因而,需要较小的正向电压来导通器件以及允许电流在正向偏置方向上流动。其次,所述肖特基位垒通常具有比可比的p-n二极管更小的电容。所述更低电容转化成比p-n二极管更高的开关速度。肖特基二极管是多数载流子器件并且不显出导致开关损耗的少数载流子行为。
不幸地,肖特基二极管传统上已遭受相对低的反向偏置额定电压和高反向偏置漏电流。近年来,北卡罗莱纳州的达勒姆的Cree公司已经引入一系列由碳化硅衬底和外延层所形成的肖特基二极管。这些器件已经并且继续通过增大反向偏置额定电压、降低反向偏置漏电流和增大正向偏置电流操纵来提升现有技术。然而,仍然有进一步改进肖特基器件性能以及减少这些器件的成本的需要。
发明内容
本公开总体上涉及肖特基二极管,其具有衬底、在所述衬底上所提供的漂移层和在所述漂移层的有源区域上所提供的肖特基层。用于肖特基层的金属和用于漂移层的半导体材料被选择以在漂移层和肖特基层之间提供低位垒高度肖特基结。
在一个实施例中,肖特基层由钽(Ta)形成并且漂移层由碳化硅形成。因而,所述肖特基结的位垒高度可以小于0.9电子伏特。其它材料适合于形成肖特基层和漂移层。
在另一个实施例中,漂移层具有与有源区域相关联的第一表面并且提供边缘终端区域。所述边缘终端区域与所述有源区域基本上横向相邻,并且在某些实施例中可以完全或基本上包围所述有源区域。所述漂移层掺杂有第一导电类型的掺杂材料,并且所述边缘终端区域可以包括从所述第一表面延伸到所述漂移层中的边缘终端凹进。可以在所述边缘终端凹进的底表面中形成诸如几个同心保护环的边缘终端结构。可以在所述边缘终端凹进的底部处的漂浮层中形成掺杂阱。
在另一个实施例中,由于包括漂移层和肖特基层的上部外延结构在衬底的顶表面上形成,所以所述衬底是相对厚的。在形成所有或至少一部分上部外延结构之后,衬底的底部部分被去除以有效地使所述衬底“变薄”。因而,所得到的肖特基二极管具有变薄的衬底,其中在所述变薄的衬底的底部上可以形成阴极接触。在所述肖特基层之上形成阳极接触。
还在其它实施例中,在正好在肖特基层下方的漂移区域中可以提供结位垒阵列并且在所有或一部分有源区域附近的漂移层中可以提供台面保护环。所述结位垒阵列、保护环和台面保护环的元件通常是漂移层中的掺杂区域。为了增大这些掺杂区域的深度,在其中将形成所述结位垒阵列、保护环和台面保护环的元件的漂移层的表面中可以形成单独凹进。一旦在漂移层中形成了凹进,在所述凹进附近和底部处的这些区域被掺杂以形成所述结位垒阵列、保护环和台面保护环的相应元件。
在阅读与附图相关联的以下详细描述之后,本领域技术人员将意识到本公开的范围和领会其附加方面。
附图说明
被结合在本说明书中并且形成本说明书的一部分的附图示出了本公开的几个方面,并且与描述一起用来解释本公开的原理。
图1是根据本公开的一个实施例的肖特基二极管的截面图。
图2是根据本公开的一个实施例的没有肖特基层和阳极接触的肖特基二极管的顶视图。
图3是根据本公开的第二实施例的没有肖特基层和阳极接触的肖特基二极管的顶视图。
图4是根据本公开的第三实施例的没有肖特基层和阳极接触的肖特基二极管的顶视图。
图5是根据本公开的第四实施例的没有肖特基层和阳极接触的肖特基二极管的顶视图。
图6是根据本公开的一个实施例的具有均匀JB阵列的肖特基二极管的部分截面图。
图7是根据本公开的另一个实施例的具有非均匀JB阵列的肖特基二极管的部分截面图。
图8是根据本公开的一个实施例的对于JB元件、保护环和台面保护环中的每一个而在漂移层中采用凹进的肖特基二级管的部分截面图。
图9是根据本公开的另一个实施例的对于JB元件、保护环和台面保护环中的每一个而在漂移层中采用凹进的肖特基二级管的部分截面图。
图10至25说明用于制造根据在图1中所说明的实施例的肖特基二极管的选择处理步骤。
具体实施方式
以下所阐明的实施例表示使得本领域技术人员能够实施本公开的必要信息并且说明实施本公开的最佳方式。在阅读根据附图的以下描述时,本领域技术人员将理解本公开的概念并且将认识到没有在此处特别提出的这些概念的应用。应当被理解的是,这些概念和应用落在本公开和所附权利要求的范围内。
将被理解的是,当诸如层、区域或衬底的元件被称作在另一个元件“上”或延伸“到”另一个元件上时,其可以是直接在所述另一个元件上或直接延伸到所述另一个元件上或也可以存在中间元件。相比之下,当元件被称作“直接在”另一个元件上或“直接延伸到”另一个元件上时,不存在中间元件。也将被理解的是,当元件被称作被“连接”或“耦合”到另一个元件时,其可以被直接连接或耦合到所述另一个元件或可以存在中间元件。相比之下,当元件被称作被“直接连接”或“直接耦合”到另一个元件时,不存在中间元件。
在此处可以使用诸如“以下”或“以上”或“上部”或“下部”或“水平”或“垂直”的相对术语,用以描述如在图中所说明的一个元件、层或区域与另一个元件、层或区域的关系。将被理解的是,这些术语和以上所讨论的那些术语意图包括除在图中所描绘的定向之外的不同器件定向。
最初,与图1相关联地提供示范性肖特基二极管10的总体结构的概观。接着所述结构概观的是肖特基二极管10的各种结构和功能方面的细节以及用于制造图1的肖特基二极管10的示范性过程。特别地,此处所描述的实施例将各种半导体层或其中的元件参考为掺杂有N型或P型掺杂材料。掺杂有N型或P型材料指示所述层或元件分别具有N型或P型导电率。N型材料具有带负电荷的电子的多数平衡浓度,并且P型材料具有带正电荷的空穴的多数平衡浓度。用于各种层或元件的掺杂浓度可以被定义为是轻、正常或重掺杂。这些术语是相对术语,其意图将用于一个层或元件的掺杂浓度与另一个层或元件联系起来。
此外,以下描述集中于在肖特基二极管中所使用的N型衬底和漂移层;然而,此处所提供的概念同等地适用于具有P型衬底和漂移层的肖特基二极管。因而,用于所公开的实施例中的每个层或元件的掺杂电荷可以被反转以产生具有P型衬底和漂移层的肖特基二极管。此外,可以使用任何可用技术而由一个或多个外延层形成此处所描述的任何层,并且在此处所描述的那些层之间可以增加未被描述的附加层,而不一定偏离本公开的概念。
如所说明的,肖特基二极管10被形成在衬底12上并且具有居于边缘终端区域16内的有源区域14,所述边缘终端区域16可以但不需要完全或基本上包围所述有源区域14。沿着衬底12的底面,阴极接触18被形成并且可以在有源区域14和边缘终端区域16这两者下方延伸。在衬底12和阴极接触18之间可以提供阴极欧姆层12,用以促进在其之间的低阻抗耦合。漂移层22沿衬底12的顶面延伸。所述漂移层22、阴极接触18和阴极欧姆层20可以沿所述有源区域14和所述边缘终端区域16这两者延伸。
在有源区域14中,肖特基层24居于漂移层22的顶表面之上,并且阳极接触26居于肖特基层24之上。如所描绘的,可以在肖特基层24和阳极接触26之间提供位垒层28,用以防止来自肖特基层24和阳极接触26中之一的材料扩散到另一个中。特别地,有源区域14基本上对应于其中肖特基二极管10的肖特基层24居于漂移层22之上的区域。只为了说明的目的,假定衬底12和漂移层22是碳化硅(SiC)。此外在以下讨论用于这些和其它层的其它材料。
在所说明的实施例中,衬底12被重掺杂并且漂移层22被相对轻掺杂有N型材料。可以基本上均匀地掺杂或以梯度方式掺杂漂移层22。例如,漂移层22的掺杂浓度可以从在衬底12近旁是相对较重掺杂过渡到在邻近肖特基层24的漂移层22的顶表面近旁是较轻掺杂。此外在以下提供掺杂细节。
在肖特基层24之下,沿漂移层22的顶表面提供多个结位垒(JB)元件30。在具有P型材料的漂移层22中的掺杂选择区域形成这些JB元件30。因而,每个JB元件30从漂移层22的顶表面延伸到漂移层22中。JB元件30一起形成JB阵列。JB元件30可以采取各种形状,如在图2至5中所说明的。如在图2中所说明的,每个JB元件30是单一、长的细长条,其基本上延伸跨越有源区域14,其中JB阵列是多个平行JB元件30。在图3中,每个JB元件30是短的细长划线(dash),其中所述JB阵列具有多个划线的平行行划线,所述多个划线被线性对准以延伸跨越所述有源区域14。在图4中,JB元件30包括多个细长条(30')和多个岛(30")。如此外在以下所描述的,所述细长条和岛可以具有基本上相同或基本上不同的掺杂浓度。在图5中,JB元件30包括较小圆形岛的阵列,其中利用较小圆形岛的阵列将多个较大矩形岛均匀地分散开。在阅读此处所提供的公开之后,本领域技术人员将意识到JB元件30和由其所形成的最终JB阵列的其它形状和配置。
继续参考与图2至5相关联的图1,边缘终端区域16包括在漂移层22的顶表面中所形成的并且基本上包围有源区域14的凹槽。该凹槽被称作边缘终端凹进32。所述边缘终端凹进32的存在提供台面,所述台面由漂移层22中的边缘终端凹进32包围。在选择的实施例中,在边缘终端凹进32的表面和台面的底表面之间的距离在大约0.2微米和0.5微米之间并且可能是大约0.3微米。
在居于边缘终端凹进32的底表面下方的一部分漂移层22中形成至少一个凹阱34。通过利用P型材料来轻掺杂居于边缘终端凹进32的底表面下方的一部分漂移层22而形成所述凹阱34。因而,所述凹阱34是在漂移层22内的轻掺杂P型区域。沿着边缘终端凹进32的底表面和在凹阱34内,形成多个同心保护环36。通过利用P型掺杂材料来重掺杂凹阱34的对应部分而形成所述保护环36。在选择的实施例中,所述保护环彼此间隔开并且从边缘终端凹进32的底表面延伸到凹阱34中。
除了居于边缘终端凹进32中的保护环36之外,可以在由边缘终端凹进32所形成的台面的外部外围周围提供台面保护环38。通过利用P型材料来重掺杂所述台面的顶表面的外部部分而形成所述台面保护环38,使得所述台面保护环38在有源区域14的外围附近形成并且延伸到所述台面中。虽然在图2至5中被说明为基本上是矩形,所述边缘终端凹进32、保护环36和台面保护环38可以是任何形状的并且将通常对应于有源区域14的外围的形状,其在所说明的实施例中是矩形。这三个元件中的每一个可以在有源区域14附近提供连续或间断(即虚线、点线等等)的环路。
在第一实施例中,图6提供一部分有源区域14的放大视图并且被用于帮助识别在肖特基二极管10的操作期间起作用的各种p-n结。对于该实施例,假定JB元件是细长条(如在图2中所说明的)。在存在JB元件30的情况下,在有源区域14附近有至少两种类型的结。第一个被称作肖特基结J1,并且是在肖特基层24和不具有JB元件30的漂移层22的顶表面的那些部分之间的任何金属半导体(m-s)结。换句话说,肖特基结J1是在肖特基层24和在两个相邻JB元件30之间或JB元件30和台面保护环38(未示出)之间的漂移层的顶表面的那些部分之间的结。第二个被称作JB结J2,并且是在JB元件30和漂移层22之间的任何p-n结。
当肖特基二极管10被正向偏置时,在JB结J2导通之前,肖特基结J1导通。在低正向电压处,肖特基二极管10中的电流输送由在肖特基结J1两端所注入的多数载流子(电子)支配。因而,肖特基二极管10像传统肖特基二极管一样起作用。在该配置中,有很少的或没有少数载流子注入,并且因而没有少数电荷。结果,肖特基二极管10能够在正常操作电压处有快速开关速度。
当肖特基二极管10被反向偏置时,形成相邻JB结J2的耗尽区域扩展,用以阻断通过肖特基二极管10的反向电流。结果,所扩展的耗尽区域发挥作用,用以既保护肖特基结J1,又限制肖特基二极管10中的反向漏电流。在JB元件30的情况下,肖特基二极管10像PIN二极管一样工作。
在另一个实施例中,图7提供一部分有源区域14的放大视图并且被用于帮助识别在肖特基二极管10的操作期间起作用的各种p-n结。对于该实施例,假定有两种类型的JB元件30:成条的较低掺杂JB元件30 '和岛状的较高掺杂JB元件30"(如在图4中所说明的)。再次,肖特基结J1是在肖特基层24和在两个相邻JB元件30之间或JB元件30和台面保护环38(未示出)之间的漂移层的顶表面的那些部分之间的任何金属半导体结。初级JB结J2是在条JB元件30'和漂移层22之间的任何p-n结。次级JB结J3是在岛JB元件30"和漂移层22之间的任何p-n结。在该实施例中,假定条JB元件30'以相同于或低于岛JB元件30"的浓度掺杂有P型材料。
肖特基二极管10的有源区域14的由较低掺杂JB元件30'和较高掺杂JB元件30"所占据的表面积与有源区域14的总的表面积的比率可以影响肖特基二极管10的反向漏电流和正向电压降这两者。例如,如果相对于有源区域14的总面积增大由较低和较高掺杂JB元件30'、30"所占据的面积,则反向漏电流可以被减小,但是肖特基二极管10的正向电压降可能增大。因而,对有源区域14的由较低和较高掺杂JB元件30'和30"所占据的表面积的比率的选择可以带来在反向漏电流和正向电压降之间的权衡。在一些实施例中,有源区域14的由较低和较高掺杂JB元件30'、30"所占据的表面积与有源区域14的总的表面积的比率可以在大约2%和40%之间。
当肖特基二极管10被正向偏置超过第一阈值时,肖特基结J1在初级JB结J2和次级JB结J3之前导通,并且所述肖特基二极管10在低正向偏置电压处显出传统肖特基二极管行为。在低正向偏置电压处,肖特基二极管10的操作由在肖特基结J1两端的多数载流子注入所支配。由于在正常操作条件下不存在少数载流子注入,肖特基二极管10可以具有非常快的开关能力,其通常是肖特基二极管的特性。
如所指示的,对于肖特基结J1的导通电压低于对于初级和次级JB结J2、J3的导通电压。所述较低和较高掺杂JB元件30'、30"可以被设计使得如果正向偏置电压继续增大超过第二阈值,则次级JB结J3将开始传导。如果正向偏置电压增大超过第二阈值,诸如在通过肖特基二极管10的电流浪涌的情况下,则次级JB结J3将开始传导。一旦次级JB结J3开始传导,则肖特基二极管10的操作由在次级结J3两端的少数载流子注入和复合所支配。在这种情况下,肖特基二极管10的导通电阻可以减小,其对于给定电流水平又可以减小由肖特基二极管10所耗散的功率量,并且可以帮助防止热逸散。
在反向偏置条件下,由初级和次级JB结J2和J3所形成的耗尽区域可以扩展以阻断通过肖特基二极管10的反向电流,因而保护肖特基结J1并且限制在肖特基二极管10中的反向漏电流。再次,当被反向偏置时,肖特基二极管10可以基本上像PIN二极管一样发挥作用。
特别地,根据本发明的一些实施例的肖特基二极管10的电压阻断能力由较低掺杂的JB元件30'的厚度和掺杂所确定。当足够大的反向电压被施加到肖特基二极管10时,较低掺杂JB元件30'中的耗尽区域将穿通到与漂移层22相关联的耗尽区域。结果,大的反向电流被准许流经肖特基二极管10。由于较低掺杂JB元件30'跨有源区域14而被分布,该反向击穿可以被均匀地分布和控制,使得其不损坏肖特基二极管10。本质上,肖特基二极管10的击穿被定位于较低掺杂的JB元件30'的穿通,所述穿通导致跨有源区域14而被均匀分布的击穿电流。结果,肖特基二极管10的击穿特性可以被控制,使得大的反向电流可以在不损坏或破坏肖特基二极管10的情况下被耗散。在一些实施例中,较低掺杂JB元件30'的掺杂可以被选择,使得穿通电压稍小于另外可以由肖特基二极管10的边缘终端所支持的最大反向电压。
在图1中所示出的边缘终端区域16的设计进一步增强肖特基二极管10的正向和反向电流和电压特性这两者。特别地,尤其当反向电压增大时,电场倾向于在肖特基层24的外围附近构建。当电场增大时,反向漏电流增大,反向击穿电压减小,并且当超过击穿电压时控制雪崩电流的能力被减小。这些特性中的每一个与提供具有低反向漏电流、高反向击穿电压和被控制的雪崩电流的肖特基二极管10的需要背道而驰。
幸运地,在肖特基层24或有源区域14周围提供保护环36通常倾向于减小电场在肖特基层24外围附近的积聚(buildup)。在选择的实施例中,诸如在图1中所示出的,在居于边缘终端凹进32的底部处的掺杂凹阱34中提供保护环36已经被证明比仅仅在漂移层22的顶表面中和在提供JB元件30的相同平面中提供保护环36多得多地减小这些电场的积聚。使用台面保护环38甚至提供另外的场抑制(field suppression)。虽然没有特别说明,台面保护环38可以包裹于在漂移层22中所形成的台面的边缘之上并且延伸到边缘终端凹进32中。在这样的实施例中,所述台面保护环38可以或可以不与另一个保护环36组合,其通常彼此间隔开。
因此,边缘终端区域16和JB元件30的设计在确定肖特基二极管10的正向和反向电流和电压特性中起重要作用。如以下进一步详细描述的,使用离子注入来形成JB元件30、保护环36、台面保护环38和凹阱34,其中适当掺杂材料的离子被注入到漂移层22的暴露顶表面中。申请人已经发现,使用更深的掺杂区域来形成所述JB元件30、保护环36、台面保护环38和甚至凹阱34已经被证明在肖特基层24附近提供极好的电场抑制以及甚至进一步被改进的电流和电压特性。不幸地,当漂移层22由有点抵抗离子注入的材料、诸如SiC形成时,产生以相对均匀和经控制的方式被掺杂的相对深的掺杂区域是有挑战性的。
参考图8,根据可替换实施例说明了肖特基二极管10的漂移层22和肖特基层24。如所说明的,在被蚀刻到漂移层22的顶表面中的对应凹进附近的漂移层22中形成JB元件30、保护环36和台面保护环38中的每个。在有源区域14中,多个JB元件凹进40和台面保护环38被蚀刻到漂移层22中。在边缘终端区域16中,边缘终端凹进32被蚀刻在漂移层22中,并且然后,保护环凹进42在边缘终端凹进32的底表面中被蚀刻到漂移层22中。如果期望,可以通过选择性掺杂边缘终端凹进32来形成凹阱34。一旦形成JB元件凹进40、保护环凹进42、台面保护环凹进44和边缘终端凹进32,沿所述凹进的侧以及在所述凹进底部处的区域被选择性地掺杂以形成杯或沟状的JB元件30、保护环36和台面保护环38。通过将凹进蚀刻到漂移层22中,可以往漂移层22中更深地形成相应的JB元件30、保护环36和台面保护环38。如所注意到的,这对于SiC器件是特别有益的。各种JB元件凹进40、保护环凹进42和台面保护环凹进44的深度和宽度可以是相同或不同的。当描述特定凹进的宽度时,所述宽度指的是具有宽度、长度和深度的凹进的较窄横向尺寸。在一个实施例中,任何凹进的深度至少是0.1微米,并且任何凹进的宽度至少是0.5微米。在另一个实施例中,凹进的深度至少是1.0微米,并且任何凹进的宽度至少是3.0微米。
参考图9,提供采用JB元件凹进40、保护环凹进42和台面保护环凹进44的另一个实施例。然而,在该实施例中,没有边缘终端凹进32、台面保护环凹进44或台面保护环38。代替地,在与JB元件凹进40相同的平面上形成保护环凹进42,并且沿这些凹进的侧和在这些凹进的底部处形成JB元件30和保护环36。在图7和8的实施例的任一个中,凹阱34是可选的。
虽然以上实施例针对的是肖特基二极管10,边缘终端区域16的所有预期结构和设计,包括凹阱34、保护环36和保护环凹进42的结构和设计,同等地可适用于在有源区域外围附近遭受不利场效应的其它半导体器件。可以受益于边缘终端区域16的预期结构和设计的示范性器件包括所有类型的场效应晶体管(FET)、绝缘栅双极晶体管(IGBT)和栅关断晶闸管(GTO)。
影响肖特基二极管10的正向和反向电流和电压特性这两者的另一个特性是与肖特基结(图6和7)相关联的位垒高度,所述肖特基结J1再次是在金属肖特基层24和半导体漂移层22之间的金属半导体结。当诸如肖特基层24的金属层与诸如漂移层22的半导体层极邻近时,在所述两个层之间产生本地(native)势垒。与肖特基结J1相关联的位垒高度对应于本地势垒。不存在外部电压的施加的情况下,该本地势垒防止大多数电荷载流子(电子或空穴)从一层移动到另一层。当施加外部电压时,从半导体层的角度,本地势垒将有效地增大或减小。特别地,当施加外部电压时,从金属层的角度,势垒将不改变。
当具有N型漂移层22的肖特基二极管10被正向偏置时,在肖特基层24处施加正电压有效地减小本地势垒并且使电子从半导体流动跨越金属半导体结。本地势垒的大小并且因而位垒高度对克服本地势垒并且使电子从半导体层向金属层流动所需要的电压量产生影响。事实上,当肖特基二极管被正向偏置时,势垒被减小。当肖特基二极管10被反向偏置时,势垒被大大增大并且发挥作用以阻断电子流动。
被用以形成肖特基层24的材料很大程度地决定与肖特基结J1相关联的位垒高度。在许多应用中,优选低位垒高度。较低位垒高度允许下述之一。首先,具有较小有源区域14的较低位垒高度器件可以被开发以具有与具有较大有源区域14和较高位垒高度的器件相同的正向导通和操作额定电流和电压。换句话说,具有较小有源区域14的较低位垒高度器件在给定电流处可以与具有较高位垒高度和较大有源区域14的器件支持相同的正向电压。可替换地,当这两个器件具有相同尺寸的有源区域14时,当操纵与较高位垒高度器件相同或相似的电流时,较低位垒高度器件可以具有较低正向导通和操作电压。较低位垒高度也降低器件的正向偏置导通电阻,其帮助使得器件更高效并且生成较少热,所述热对于器件可能是破坏性的。与采用SiC漂移层22的肖特基应用中的低位垒高度相关联的示范性金属(包括合金)包括但不限于钽(Ta)、钛(Ti)、铬(Cr)和铝(Al),其中钽与该组的最低位垒高度相关联。所述金属被定义为低位垒高度电缆金属。虽然位垒高度是用于肖特基层24的材料、用于漂移层22的材料、并且可能是漂移层22中的掺杂程度的函数,利用某些实施例可以实现的示范性位垒高度小于1.2电子伏特(eV)、小于1.1eV、小于1.0eV、小于0.9eV并且小于大约0.8eV。
现在转到图10-24,提供了用于制造诸如在图1中所说明的一个之类的肖特基二极管10的示范性过程。在该示例中,假定JB元件30是细长条,如在图2中所说明的。贯穿所述过程的描述,概述了示范性材料、掺杂类型、掺杂水平、结构尺寸和所选择的替换方案。这些方面仅仅是说明性的,并且此处所公开的概念和随后的权利要求不被限制于这些方面。
如在图10中所示出的,过程通过提供N掺杂、单晶、4H SiC衬底12而开始。衬底12可以具有各种晶体多型,诸如2H、4H、6H、3C等等。所述衬底也可以由诸如氮化镓(GaN)、砷化镓(GaAs)、硅(Si)、锗(Ge)、SiGe等等的其它材料系统形成。N掺杂、SiC衬底12的电阻率在一个实施例中在大约10毫欧-厘米和30毫欧-厘米之间。初始衬底12可以具有在大约200微米和500微米之间的厚度。
漂移层22可以生长在衬底12上并且被原位掺杂,其中漂移层22在其生长时被掺杂有N型掺杂材料,如在图11中所示出的。特别地,在形成漂移层22之前,可以在衬底12上形成一个或多个缓冲层(未示出)。所述缓冲层可以被用作成核层并且相对重掺杂有N型掺杂材料。所述缓冲层在某些实施例中可以从0.5微米变化至5微米。
漂移层22可以贯穿地被相对均匀地掺杂或可以贯穿其全部或一部分而采用梯度掺杂。对于均匀掺杂的漂移层22,掺杂浓度在一个实施例中可以在大约2×1015cm-3和1×1016cm-3之间。在梯度掺杂的情况下,掺杂浓度在衬底12近旁的漂移层22的底部处最高并且在肖特基层24近旁的漂移层22的顶部处最低。所述掺杂浓度通常以逐步或连续方式从在漂移层22的底部处或底部近旁的点至在漂移层22的顶部处或近旁的点减小。在采用梯度掺杂的一个实施例中,漂移层22的较低部分可以以大约1×1015cm-3的浓度被掺杂并且漂移层22的较高部分可以以大约5×1016cm-3的浓度被掺杂。在采用梯度掺杂的另一个实施例中,漂移层22的较低部分可以以大约5×1015cm-3的浓度被掺杂并且漂移层22的较高部分可以以大约1×1016cm-3的浓度被掺杂。
在选择的实施例中,取决于所期望的反向击穿电压,漂移层22可以在四微米和十微米之间。在一个实施例中,漂移层22是大约每100伏特的所期望的反向击穿电压一微米厚。例如,具有600伏特的反向击穿电压的肖特基二极管10可以有具有大约六微米的厚度的漂移层22。
一旦漂移层22被形成,顶表面被蚀刻以产生边缘终端凹进32,如在图12中所示出的。基于所期望的器件特性,边缘终端凹进32将在深度和宽度上变化。在具有600V的反向击穿电压和可以操控持续不变的50A正向电流的肖特基二极管10的一个实施例中,边缘终端凹进32具有在大约0.2微米和0.5微米之间的深度和在大约10和120之间的宽度,其将最终取决于在所述器件中采用了多少保护环36。
接下来,通过利用P型材料选择性注入居于边缘终端凹进32的底部处的漂移层22的一部分而形成凹阱34,如在图13中所示出的。例如,具有600伏特的反向击穿电压并且能够操控持续不变的50A正向电流的肖特基二极管10可以具有以在大约5×1016cm-3和2×1017cm-3之间的浓度被轻掺杂的凹阱34。凹阱34可以是在大约0.1微米和0.5微米深之间并且具有基本上对应于边缘终端凹进32的宽度的宽度。
一旦凹阱34被形成,通过利用P型材料来选择性地注入漂移层22的顶表面的对应部分(包括边缘终端凹进32的底表面)而形成JB元件30、台面保护环38和保护环36,如在图14中所示出的。JB元件30、台面保护环38和保护环36是相对重掺杂的并且可以使用相同离子注入过程而同时形成。在一个实施例中,具有600伏特的反向击穿电压和能够操控持续不变的50A正向电流的肖特基二极管10可以具有都以在大约5×1017cm-3和5×1019cm-3之间的浓度被掺杂的JB元件30、台面保护环38和保护环36。在其它实施例中,可以使用相同或不同的离子注入过程、以不同浓度来掺杂这些元件。例如,当JB元件30的JB阵列包括如在图4和5中所提供的不同形状或尺寸时,或在不同JB元件30具有不同深度的情况下。在相邻JB元件30之间、在台面保护环38和JB元件30之间和在相邻保护环36之间的深度和间隔可以基于所期望的器件特性而变化。例如,这些元件的深度可以从0.2微米变化到大于1.5微米,并且相应元件可以彼此间隔开大约一微米和四微米之间。
对于像那些在图8和9中所说明的、采用JB元件凹进或台面保护环凹进44或保护环凹进42的实施例,相应JB元件30、台面保护环38和保护环36更容易往漂移层22中更深地形成。对于由SiC所形成的漂移层22,相应凹进的深度可以在大约0.1微米和1.0微米之间并且具有在大约1.0微米和5.0微米之间的宽度。因而,JB元件30、台面保护环38和保护环36的总深度可以容易地延伸至如从漂移层22的顶表面所测量的、在0.5和1.5之间的深度。
如在图15中所说明的,在漂移层22的顶表面(包括边缘终端凹进32的底表面)之上形成热氧化物层46。对于SiC漂移层22,氧化物是二氧化硅(SiO2)。热氧化物层46可以充当钝化层,所述钝化层为漂移层22和其中所形成的各种元件的保护或性能给予帮助。接下来,如在图16中所示出的,与有源区域14相关联的热氧化物层46的部分被去除以形成其中将形成肖特基层24的肖特基凹进48。
一旦肖特基凹进48被形成,如在图17中所说明的,在由肖特基凹进48所暴露的漂移层22的部分之上形成肖特基层24。肖特基层24的厚度将基于所期望的器件特性和用于形成肖特基层24的金属而变化,并且将通常在大约100埃和4500埃之间。对于参考的600V器件,由钽(Ta)所形成的肖特基层24可以在大约200埃和1200埃之间;由钛(Ti)所形成的肖特基层24可以在大约500埃和2500埃之间;并且由铝(Al)所形成的肖特基层24可以在大约3500埃和4500埃之间。如以上所注意到的,特别是当连同SiC被使用以形成肖特基结时,钽(Ta)与非常低的位垒高度相关联。钽(Ta)相对于SiC也是非常稳定的。
取决于用于肖特基层24和将被形成的阳极接触26的金属,可以在肖特基层24上形成一个或多个位垒层28,如在图18中所示出的。所述位垒层28可以由钛钨合金(TiW)、钛镍合金(TiN)、钽(Ta)和任何其它合适材料形成并且在选择的实施例中可以在大约75埃和400埃厚之间。所述位垒层28帮助防止在用于形成肖特基层24和将被形成的阳极接触26的金属之间的扩散。特别地,在其中肖特基层24是钽(Ta)并且将被形成的阳极接触26由铝(Al)形成的某些实施例中不使用所述位垒层28。所述位垒层28通常在其中肖特基层是钛(Ti)并且将被形成的阳极接触26由铝(Al)形成的实施例中是有益的。
接下来,在肖特基层24或(如果存在)位垒层28上形成阳极接触26,如在图19中所示出的。阳极接触26通常相对厚、由金属形成,并且充当用于肖特基二极管10的阳极的接合焊盘。所述阳极接触26可以由铝(Al)、金(Au)、银(Ag)等等形成。
然后至少在阳极接触26和热氧化物层46的暴露表面上形成密封层50,如在图20中所说明的。所述密封层50可以是诸如氮化硅(SiN)的氮化物并且充当保形涂层以保护下面的层不受不利环境条件影响。为了进一步抵抗划痕或如同机械损坏的保护,可以在所述密封层50上提供聚酰亚胺层52,如在图21中所说明的。所述聚酰亚胺层52的中央部分被去除以在所述密封层50上提供阳极开口54。在该示例中,所述聚酰亚胺层52被用作蚀刻掩模,所述蚀刻掩模具有以阳极接触26为中心的阳极开口54。接下来,密封层50的由阳极开口54所暴露的部分被去除以暴露阳极接触26的顶表面,如在图22中所说明的。最终,接合线等等可以通过密封层50中的阳极开口54而被焊接或用别的方式连接到阳极接触26的顶表面。
在该点上,处理从肖特基二极管10的正面(顶部)转换到肖特基二极管10的背面(底部)。如在图23中所说明的,基本上通过经由磨削、蚀刻或相似的过程来去除衬底12的底部来使衬底12变薄。对于600V参考肖特基二极管10,衬底12在第一实施例中可以被变薄至在大约50微米和200微米之间的厚度,并且在第二实施例中在大约75微米和125微米之间。使衬底12变薄或另外采用薄衬底12减小在肖特基二极管10的阳极和阴极之间的总电和热阻并且允许器件操控更高的电流密度而没有过热。
最终,利用诸如镍(Ni)、硅化镍(NiSi)和铝化镍(NiAl)之类的欧姆金属而在被变薄的衬底12的底部上形成阴极欧姆层20,如在图24中所说明的。在采用聚酰亚胺层52的实施例中,所述阴极欧姆层20可以被激光退火,而不是以高温度烘烤整个器件以使所述欧姆金属退火。激光退火允许欧姆金属被充分加热以便退火,但是不将器件的其余部分加热至另外将会损坏或破坏聚酰亚胺层52的温度。一旦阴极欧姆层20被形成并且被退火,则在阴极欧姆层20上形成阴极接触18以提供用于肖特基二极管10的焊接或相似的接口,如在图25中所说明的。
利用此处所公开的概念,非常高性能的肖特基二极管10可以被设计用于需要各种操作参数的各种应用。与DC正向偏置电流相关联的电流密度在某些实施例中可以超过440安培/厘米,并且在其它实施例中可以超过500安培/厘米。此外,肖特基二极管10在各种实施例中可以被构造以具有大于0.275、0.3、0.325、0.35、0.375和0.4安培/皮克法拉(A/pF)的DC正向偏置电流密度与反向偏置阳极阴极电容的比率,其中当肖特基二极管被反向偏置到有源区域基本上被完全耗尽的点时,所述反向偏置阳极阴极电压被确定。
本领域技术人员将意识到对本公开的实施例的改进和修改。所有这样的改进和修改被认为是在此处所公开的概念和随后的权利要求的范围内。
Claims (39)
1.一种肖特基二极管,包括:
漂移层,其具有与有源区域和同所述有源区域基本上横向相邻的边缘终端区域相关联的第一表面,其中所述漂移层主要地掺杂有第一导电类型的掺杂材料,并且所述边缘终端区域具有从所述第一表面延伸到所述漂移层中的边缘终端凹进;
在所述第一表面的有源区域上的用以形成肖特基结的肖特基层,所述肖特基层由有低位垒高度能力的金属形成;
在边缘终端凹进的底表面中所形成的边缘终端结构。
2.根据权利要求1所述的肖特基二极管,其中所述肖特基结具有小于0.9电子伏特的位垒高度。
3.根据权利要求1所述的肖特基二极管,其中:
所述肖特基层的有低位垒高度能力的金属包括钽;并且
所述边缘终端凹进基本上在所述有源区域附近延伸;并且
所述边缘终端结构包括基本上在所述有源区域附近延伸的多个保护环。
4.根据权利要求3所述的肖特基二极管,其中所述有源区域在所述漂移层中的台面上被提供并且还包括基本上在所述肖特基层附近延伸的台面保护环,使得所述台面保护环居于肖特基层和所述多个保护环之间。
5.根据权利要求4所述的肖特基二极管,其中在所述边缘终端凹进的底表面下方的所述漂移层中形成凹阱,并且所述凹阱掺杂有第二导电类型的掺杂材料,所述第二导电类型与所述第一导电类型相反。
6.根据权利要求3所述的肖特基二极管,其中所述漂移层在被变薄的衬底上形成,所述被变薄的衬底是在形成所述漂移层之后被变薄的。
7.根据权利要求6所述的肖特基二极管,其中所述肖特基层的有低位垒高度能力的金属基本上由钽构成。
8.根据权利要求3所述的肖特基二极管,其中:
所述肖特基层的有低位垒高度能力的金属包括钽;并且
所述漂移层包括碳化硅。
9.根据权利要求8所述的肖特基二极管,其中所述肖特基层的有低位垒高度能力的金属基本上由钽构成。
10.根据权利要求1所述的肖特基二极管,其中所述肖特基层的有低位垒高度能力的金属包括钽。
11.根据权利要求1所述的肖特基二极管,其中所述肖特基层的有低位垒高度能力的金属包括由钛、铬和铝所构成的组中的至少一个。
12.根据权利要求1所述的肖特基二极管,其中所述肖特基层的有低位垒高度能力的金属基本上由钽构成。
13.根据权利要求1所述的肖特基二极管,其中所述边缘终端结构包括至少一个保护环。
14.根据权利要求1所述的肖特基二极管,其中所述边缘终端凹进基本上在所述有源区域附近延伸并且所述边缘终端结构包括基本上在所述有源区域附近延伸的多个保护环。
15.根据权利要求14所述的肖特基二极管,其中所述有源区域在所述漂移层中的台面上被提供并且还包括基本上在所述肖特基层附近延伸的台面保护环,使得所述台面保护环居于所述肖特基层和所述多个保护环之间。
16.根据权利要求15所述的肖特基二极管,其中在所述有源区域附近的所述漂移层的第一表面包括台面保护环凹进,使得所述台面保护环是延伸到在所述台面保护环凹进附近的所述漂移层中的掺杂区域,并且所述掺杂区域掺杂有第二导电类型的掺杂材料,所述第二导电类型与所述第一导电类型相反。
17.根据权利要求14所述的肖特基二极管,其中在所述边缘终端凹进的底表面下方的所述漂移层中形成凹阱,并且所述凹阱掺杂有第二导电类型的掺杂材料,所述第二导电类型与第一导电类型相反。
18.根据权利要求14所述的肖特基二极管,其中所述边缘终端凹进的底表面包括多个保护环凹进,使得所述多个保护环中的至少一些是延伸到在所述多个保护环凹进中对应的一个附近的所述漂移层中的掺杂区域,并且所述掺杂区域掺杂有第二导电类型的掺杂材料,所述第二导电类型与第一导电类型相反。
19.根据权利要求1所述的肖特基二极管,其中所述漂移层在被变薄的衬底上形成,并且在所述被变薄的衬底的底表面上形成阴极接触,所述被变薄的衬底是在形成所述漂移层之后被变薄的。
20.根据权利要求19所述的肖特基二极管,其中所述被变薄的衬底在大约50微米和200微米厚之间。
21.根据权利要求1所述的肖特基二极管,其中所述边缘终端凹进大于0.2微米深。
22.根据权利要求1所述的肖特基二极管,其中所述边缘终端凹进在大约0.2微米和0.5微米深之间。
23.根据权利要求1所述的肖特基二极管,还包括在肖特基结下方的所述漂移层中所形成的结位垒元件的阵列。
24.根据权利要求23所述的肖特基二极管,其中所述结位垒元件阵列的每个结位垒元件与所述结位垒元件阵列的其它元件基本上相同。
25.根据权利要求23所述的肖特基二极管,其中所述结位垒元件阵列的至少第一结位垒元件在尺寸或形状上与所述结位垒元件阵列的至少第二结位垒元件基本上不同。
26.根据权利要求23所述的肖特基二极管,其中在所述结位垒元件阵列中的至少某些结位垒元件是细长条。
27.根据权利要求23所述的肖特基二极管,其中在所述结位垒元件阵列中的至少某些结位垒元件基本上围绕着所述第一表面。
28.根据权利要求23所述的肖特基二极管,其中所述漂移层的第一表面在所述有源区域中包括多个结位垒元件凹进,使得所述结位垒元件阵列的至少某些结位垒元件是延伸到在所述多个结位垒元件凹进中对应多个的附近的所述漂移层中的掺杂区域,并且所述掺杂区域掺杂有第二导电类型的掺杂材料,所述第二导电类型与所述第一导电类型相反。
29.根据权利要求1所述的肖特基二极管,其中所述漂移层以梯度方式主要地掺杂有第一导电类型的掺杂材料,其中所述漂移层在所述漂移层的第一表面近旁具有较低掺杂浓度并且在其第二表面近旁具有有意更高的掺杂浓度,所述第二表面与所述第一表面基本上相对。
30.根据权利要求1所述的肖特基二极管,其中所述漂移层包括碳化硅。
31.根据权利要求1所述的肖特基二极管,其中所述肖特基二极管当被正向偏置时支持至少440安培/厘米的DC电流密度。
32.根据权利要求1所述的肖特基二极管,其中所述肖特基二极管当被正向偏置时支持至少500安培/厘米的DC电流密度。
33.根据权利要求1所述的肖特基二极管,其中DC正向偏置电流密度与反向偏置阳极阴极电容的比率至少是0.275安培/皮克法拉(A/pF),其中当所述肖特基二极管被反向偏置到所述有源区域基本上完全被耗尽的点时,所述反向偏置阳极阴极电压被确定。
34.根据权利要求1所述的肖特基二极管,其中DC正向偏置电流密度与反向偏置阳极阴极电容的比率至少是0.3安培/皮克法拉(A/pF),其中当所述肖特基二极管被反向偏置到所述有源区域基本上完全被耗尽的点时,所述反向偏置阳极阴极电压被确定。
35.根据权利要求1所述的肖特基二极管,其中DC正向偏置电流密度与反向偏置阳极阴极电容的比率至少是0.35安培/皮克法拉(A/pF),其中当所述肖特基二极管被反向偏置到所述有源区域基本上完全被耗尽的点时,所述反向偏置阳极阴极电压被确定。
36.一种肖特基二极管,包括:
漂移层,其具有与有源区域和同所述有源区域基本上横向相邻的边缘终端区域相关联的第一表面,其中所述漂移层包括碳化硅并且掺杂有第一导电类型的掺杂材料,并且所述边缘终端区域具有从所述第一表面延伸到所述漂移层中的边缘终端凹进;
在所述第一表面的有源区域上的用以形成肖特基结的肖特基层,所形成的肖特基层包括钽;
在所述边缘终端凹进的底表面中所形成的边缘终端结构;和
在所述肖特基结下方并且在所述漂移层中所形成的结位垒元件阵列。
37.根据权利要求36所述的肖特基二极管,其中所述漂移层在被变薄的碳化硅衬底上形成,并且在所述被变薄的碳化硅衬底的底表面上形成阴极接触,所述被变薄的碳化硅衬底是在形成所述漂移层之后被变薄的。
38.根据权利要求37所述的肖特基二极管,其中所述漂移层的第一表面在所述有源区域中包括多个结位垒元件凹进,使得所述结位垒元件阵列的至少某些结位垒元件是延伸到在所述多个结位垒元件凹进中对应多个的附近的所述漂移层中的掺杂区域,并且所述掺杂区域掺杂有第二导电类型的掺杂材料,所述第二导电类型与所述第一导电类型相反。
39.一种肖特基二极管,包括:
衬底;
在所述衬底上所形成的并且具有第一表面的漂移层,所述第一表面与有源区域以及同所述有源区域基本上横向相邻的边缘终端区域相关联,其中所述漂移层主要地掺杂有第一导电类型的掺杂材料;和
在所述第一表面的有源区域上的用以形成肖特基结的肖特基层,
其中所述肖特基层由有低位垒高度能力的金属形成,并且所述漂移层具有基本上在所述肖特基层附近延伸的台面保护环,并且所述衬底在形成所述漂移层之后被变薄。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105226102A (zh) * | 2014-06-25 | 2016-01-06 | 辛纳普蒂克斯显像装置合同会社 | 结势垒肖特基二极管及其制造方法 |
CN106067415A (zh) * | 2015-04-24 | 2016-11-02 | 富士电机株式会社 | 碳化硅半导体装置的制造方法 |
CN108140676A (zh) * | 2015-10-30 | 2018-06-08 | 三菱电机株式会社 | 碳化硅半导体器件 |
CN110534583A (zh) * | 2019-08-01 | 2019-12-03 | 山东天岳电子科技有限公司 | 一种肖特基二极管及其制备方法 |
CN110571281A (zh) * | 2019-08-01 | 2019-12-13 | 山东天岳电子科技有限公司 | 一种混合PiN结肖特基二极管及制造方法 |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9117739B2 (en) * | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
US8680587B2 (en) | 2011-09-11 | 2014-03-25 | Cree, Inc. | Schottky diode |
US8890293B2 (en) * | 2011-12-16 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Guard ring for through vias |
CA2872941C (en) * | 2012-05-17 | 2021-03-30 | General Electric Company | Semiconductor device with junction termination extension |
DE102013010187A1 (de) * | 2012-06-27 | 2014-01-02 | Fairchild Semiconductor Corp. | Schottky-Barriere-Vorrichtung mit lokal planarisierter Oberfläche und zugehöriges Halbleitererzeugnis |
US9991399B2 (en) * | 2012-10-04 | 2018-06-05 | Cree, Inc. | Passivation structure for semiconductor devices |
US8952481B2 (en) | 2012-11-20 | 2015-02-10 | Cree, Inc. | Super surge diodes |
US8866148B2 (en) * | 2012-12-20 | 2014-10-21 | Avogy, Inc. | Vertical GaN power device with breakdown voltage control |
KR20140089639A (ko) * | 2013-01-03 | 2014-07-16 | 삼성전자주식회사 | 가변 저항 메모리 장치 및 그 형성 방법 |
TW201438232A (zh) * | 2013-03-26 | 2014-10-01 | Anpec Electronics Corp | 半導體功率元件及其製作方法 |
JP2014236171A (ja) | 2013-06-05 | 2014-12-15 | ローム株式会社 | 半導体装置およびその製造方法 |
US9245944B2 (en) * | 2013-07-02 | 2016-01-26 | Infineon Technologies Ag | Silicon carbide device and a method for manufacturing a silicon carbide device |
US9768259B2 (en) * | 2013-07-26 | 2017-09-19 | Cree, Inc. | Controlled ion implantation into silicon carbide using channeling and devices fabricated using controlled ion implantation into silicon carbide using channeling |
JP2015032627A (ja) * | 2013-07-31 | 2015-02-16 | 株式会社東芝 | 半導体装置 |
DE102013111966B4 (de) | 2013-10-30 | 2017-11-02 | Infineon Technologies Ag | Feldeffekthalbleiterbauelement und Verfahren zu dessen Herstellung |
JP6222771B2 (ja) * | 2013-11-22 | 2017-11-01 | 国立研究開発法人産業技術総合研究所 | 炭化珪素半導体装置の製造方法 |
US20150255362A1 (en) * | 2014-03-07 | 2015-09-10 | Infineon Technologies Ag | Semiconductor Device with a Passivation Layer and Method for Producing Thereof |
JP6010773B2 (ja) * | 2014-03-10 | 2016-10-19 | パナソニックIpマネジメント株式会社 | 半導体素子及びその製造方法 |
EP2942805B1 (en) * | 2014-05-08 | 2017-11-01 | Nexperia B.V. | Semiconductor device and manufacturing method |
MY185098A (en) * | 2014-08-29 | 2021-04-30 | Mimos Berhad | A method for manufacturing a large schottky diode |
WO2016043247A1 (ja) | 2014-09-17 | 2016-03-24 | 富士電機株式会社 | 半導体装置 |
US9324827B1 (en) * | 2014-10-28 | 2016-04-26 | Globalfoundries Inc. | Non-planar schottky diode and method of fabrication |
US9583482B2 (en) | 2015-02-11 | 2017-02-28 | Monolith Semiconductor Inc. | High voltage semiconductor devices and methods of making the devices |
US10026805B2 (en) | 2015-03-27 | 2018-07-17 | Farichild Semiconductor Corporation | Avalanche-rugged silicon carbide (SiC) power device |
US9741873B2 (en) * | 2015-03-27 | 2017-08-22 | Fairchild Semiconductor Corporation | Avalanche-rugged silicon carbide (SiC) power Schottky rectifier |
US9368650B1 (en) * | 2015-07-16 | 2016-06-14 | Hestia Power Inc. | SiC junction barrier controlled schottky rectifier |
DE102015120668B4 (de) * | 2015-11-27 | 2022-08-11 | Infineon Technologies Ag | Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelementes |
WO2017135940A1 (en) * | 2016-02-03 | 2017-08-10 | Microsemi Corporation | Sic transient voltage suppressor |
JP6668847B2 (ja) * | 2016-03-15 | 2020-03-18 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
US9806112B1 (en) * | 2016-05-02 | 2017-10-31 | Huawei Technologies Co., Ltd. | Electrostatic discharge guard structure |
US9978751B2 (en) * | 2016-05-20 | 2018-05-22 | Mediatek Inc. | Semiconductor structure |
KR102430498B1 (ko) | 2016-06-28 | 2022-08-09 | 삼성전자주식회사 | 쇼트키 다이오드를 갖는 전자 소자 |
US10083952B2 (en) * | 2017-02-02 | 2018-09-25 | Globalfoundries Inc. | Diode-triggered schottky silicon-controlled rectifier for Fin-FET electrostatic discharge control |
US10510905B2 (en) * | 2017-07-06 | 2019-12-17 | Cree, Inc. | Power Schottky diodes having closely-spaced deep blocking junctions in a heavily-doped drift region |
SE541466C2 (en) * | 2017-09-15 | 2019-10-08 | Ascatron Ab | A concept for silicon carbide power devices |
EP3460856B1 (en) * | 2017-09-26 | 2020-12-02 | ams AG | Schottky barrier diode with improved schottky contact for high voltages |
WO2019097662A1 (ja) * | 2017-11-17 | 2019-05-23 | 新電元工業株式会社 | 電力変換回路 |
JP7132719B2 (ja) * | 2018-01-19 | 2022-09-07 | ローム株式会社 | 半導体装置 |
US10608122B2 (en) | 2018-03-13 | 2020-03-31 | Semicondutor Components Industries, Llc | Schottky device and method of manufacture |
JP6952631B2 (ja) * | 2018-03-20 | 2021-10-20 | 株式会社東芝 | 半導体装置 |
DE102019100130B4 (de) * | 2018-04-10 | 2021-11-04 | Infineon Technologies Ag | Ein halbleiterbauelement und ein verfahren zum bilden eines halbleiterbauelements |
US11342232B2 (en) * | 2018-06-22 | 2022-05-24 | Intel Corporation | Fabrication of Schottky barrier diode using lateral epitaxial overgrowth |
KR102038525B1 (ko) | 2018-09-27 | 2019-11-26 | 파워큐브세미(주) | Esd 방지 구조를 가진 실리콘카바이드 쇼트키 정션 배리어 다이오드 |
KR102156685B1 (ko) | 2018-11-27 | 2020-09-16 | 한양대학교 산학협력단 | 2단자 수직형 사이리스터 기반 1t 디램 |
CN109509794A (zh) * | 2018-12-08 | 2019-03-22 | 程德明 | N+区边缘圆弧形结构的p+-i-n+型功率二极管 |
KR102224497B1 (ko) | 2019-08-28 | 2021-03-08 | 연세대학교 산학협력단 | 이차원 반도체 물질을 이용한 수직형 쇼트키 다이오드 및 이의 제조방법 |
US11462648B2 (en) | 2019-12-05 | 2022-10-04 | Globalfoundries U.S. Inc. | Fin-based Schottky diode for integrated circuit (IC) products and methods of making such a Schottky diode |
JP7371484B2 (ja) * | 2019-12-18 | 2023-10-31 | Tdk株式会社 | ショットキーバリアダイオード |
KR102335550B1 (ko) * | 2020-05-06 | 2021-12-08 | 파워큐브세미 (주) | 멀티에피를 활용하여 러기드니스가 강화된 실리콘카바이드 정션 배리어 쇼트키 다이오드 |
CN113066870B (zh) * | 2021-03-25 | 2022-05-24 | 电子科技大学 | 一种具有终端结构的氧化镓基结势垒肖特基二极管 |
US11677023B2 (en) * | 2021-05-04 | 2023-06-13 | Infineon Technologies Austria Ag | Semiconductor device |
CN116230743B (zh) * | 2022-04-09 | 2024-02-23 | 重庆理工大学 | 一种氧化镓pn异质结二极管 |
CN116093165A (zh) * | 2023-04-10 | 2023-05-09 | 深圳市晶扬电子有限公司 | 一种紧凑的低电容型肖特基二极管 |
CN117747675A (zh) * | 2024-02-20 | 2024-03-22 | 北京怀柔实验室 | 肖特基二极管及其制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101385146A (zh) * | 2006-02-16 | 2009-03-11 | 财团法人电力中央研究所 | 肖特基结半导体元件及其制造方法 |
CN101467262A (zh) * | 2006-04-04 | 2009-06-24 | 半南实验室公司 | 结势垒肖特基整流器及其制造方法 |
CN101978502A (zh) * | 2008-03-17 | 2011-02-16 | 三菱电机株式会社 | 半导体器件 |
US20110207321A1 (en) * | 2010-02-19 | 2011-08-25 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device manufacturiing method |
US20110215338A1 (en) * | 2010-03-08 | 2011-09-08 | Qingchun Zhang | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
Family Cites Families (321)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3439189A (en) | 1965-12-28 | 1969-04-15 | Teletype Corp | Gated switching circuit comprising parallel combination of latching and shunt switches series-connected with input-output control means |
US3629011A (en) | 1967-09-11 | 1971-12-21 | Matsushita Electric Ind Co Ltd | Method for diffusing an impurity substance into silicon carbide |
US3924024A (en) | 1973-04-02 | 1975-12-02 | Ncr Co | Process for fabricating MNOS non-volatile memories |
FR2347780A1 (fr) | 1976-07-21 | 1977-11-04 | Bicosa Recherches | Perfectionnements apportes a un element bistable et circuit interrupteur comportant un tel element bistable |
US4242690A (en) | 1978-06-06 | 1980-12-30 | General Electric Company | High breakdown voltage semiconductor device |
US4466172A (en) | 1979-01-08 | 1984-08-21 | American Microsystems, Inc. | Method for fabricating MOS device with self-aligned contacts |
JPS59104165A (ja) | 1982-12-06 | 1984-06-15 | Mitsubishi Electric Corp | 電力用トランジスタ |
US4570328A (en) | 1983-03-07 | 1986-02-18 | Motorola, Inc. | Method of producing titanium nitride MOS device gate electrode |
US4469022A (en) | 1983-04-01 | 1984-09-04 | Permanent Label Corporation | Apparatus and method for decorating articles of non-circular cross-section |
US4641174A (en) | 1983-08-08 | 1987-02-03 | General Electric Company | Pinch rectifier |
US4581542A (en) | 1983-11-14 | 1986-04-08 | General Electric Company | Driver circuits for emitter switch gate turn-off SCR devices |
US4644637A (en) | 1983-12-30 | 1987-02-24 | General Electric Company | Method of making an insulated-gate semiconductor device with improved shorting region |
JPS60240158A (ja) | 1984-05-14 | 1985-11-29 | Mitsubishi Electric Corp | 半導体回路 |
DE3581348D1 (de) | 1984-09-28 | 1991-02-21 | Siemens Ag | Verfahren zum herstellen eines pn-uebergangs mit hoher durchbruchsspannung. |
JPS61191071A (ja) | 1985-02-20 | 1986-08-25 | Toshiba Corp | 伝導度変調型半導体装置及びその製造方法 |
JPS62136072A (ja) | 1985-12-10 | 1987-06-19 | Fuji Electric Co Ltd | シヨツトキ−バリアダイオ−ドの製造方法 |
JP2633536B2 (ja) | 1986-11-05 | 1997-07-23 | 株式会社東芝 | 接合型半導体基板の製造方法 |
US5041881A (en) | 1987-05-18 | 1991-08-20 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Whiskerless Schottky diode |
US4811065A (en) | 1987-06-11 | 1989-03-07 | Siliconix Incorporated | Power DMOS transistor with high speed body diode |
JPS6449273A (en) | 1987-08-19 | 1989-02-23 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
US4945394A (en) | 1987-10-26 | 1990-07-31 | North Carolina State University | Bipolar junction transistor on silicon carbide |
US4875083A (en) | 1987-10-26 | 1989-10-17 | North Carolina State University | Metal-insulator-semiconductor capacitor formed on silicon carbide |
US4866005A (en) | 1987-10-26 | 1989-09-12 | North Carolina State University | Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide |
US5011549A (en) | 1987-10-26 | 1991-04-30 | North Carolina State University | Homoepitaxial growth of Alpha-SiC thin films and semiconductor devices fabricated thereon |
JPH01117363A (ja) | 1987-10-30 | 1989-05-10 | Nec Corp | 縦型絶縁ゲート電界効果トランジスタ |
JPH02137368A (ja) | 1988-11-18 | 1990-05-25 | Toshiba Corp | 半導体整流装置 |
JP2667477B2 (ja) | 1988-12-02 | 1997-10-27 | 株式会社東芝 | ショットキーバリアダイオード |
JPH02275675A (ja) | 1988-12-29 | 1990-11-09 | Fuji Electric Co Ltd | Mos型半導体装置 |
CA2008176A1 (en) | 1989-01-25 | 1990-07-25 | John W. Palmour | Silicon carbide schottky diode and method of making same |
EP0389863B1 (de) | 1989-03-29 | 1996-12-18 | Siemens Aktiengesellschaft | Verfahren zur Herstellung eines planaren pn-Übergangs hoher Spannungsfestigkeit |
US5111253A (en) | 1989-05-09 | 1992-05-05 | General Electric Company | Multicellular FET having a Schottky diode merged therewith |
US4927772A (en) | 1989-05-30 | 1990-05-22 | General Electric Company | Method of making high breakdown voltage semiconductor device |
JPH0766971B2 (ja) | 1989-06-07 | 1995-07-19 | シャープ株式会社 | 炭化珪素半導体装置 |
US5028977A (en) | 1989-06-16 | 1991-07-02 | Massachusetts Institute Of Technology | Merged bipolar and insulated gate transistors |
JPH0334466A (ja) | 1989-06-30 | 1991-02-14 | Nippon Telegr & Teleph Corp <Ntt> | 縦形二重拡散mosfet |
JP2623850B2 (ja) | 1989-08-25 | 1997-06-25 | 富士電機株式会社 | 伝導度変調型mosfet |
JPH0750791B2 (ja) | 1989-09-20 | 1995-05-31 | 株式会社日立製作所 | 半導体整流ダイオード及びそれを使つた電源装置並びに電子計算機 |
US4946547A (en) | 1989-10-13 | 1990-08-07 | Cree Research, Inc. | Method of preparing silicon carbide surfaces for crystal growth |
JPH03157974A (ja) | 1989-11-15 | 1991-07-05 | Nec Corp | 縦型電界効果トランジスタ |
US5166760A (en) | 1990-02-28 | 1992-11-24 | Hitachi, Ltd. | Semiconductor Schottky barrier device with pn junctions |
JPH03225870A (ja) | 1990-01-31 | 1991-10-04 | Toshiba Corp | ヘテロ接合バイポーラトランジスタの製造方法 |
US5210051A (en) | 1990-03-27 | 1993-05-11 | Cree Research, Inc. | High efficiency light emitting diodes from bipolar gallium nitride |
JP2542448B2 (ja) | 1990-05-24 | 1996-10-09 | シャープ株式会社 | 電界効果トランジスタおよびその製造方法 |
US5292501A (en) | 1990-06-25 | 1994-03-08 | Degenhardt Charles R | Use of a carboxy-substituted polymer to inhibit plaque formation without tooth staining |
US5200022A (en) | 1990-10-03 | 1993-04-06 | Cree Research, Inc. | Method of improving mechanically prepared substrate surfaces of alpha silicon carbide for deposition of beta silicon carbide thereon and resulting product |
US5345100A (en) | 1991-03-29 | 1994-09-06 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor rectifier having high breakdown voltage and high speed operation |
JPH04302172A (ja) | 1991-03-29 | 1992-10-26 | Kobe Steel Ltd | ダイヤモンドショットキーダイオード |
US5262669A (en) | 1991-04-19 | 1993-11-16 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor rectifier having high breakdown voltage and high speed operation |
US5192987A (en) | 1991-05-17 | 1993-03-09 | Apa Optics, Inc. | High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions |
US5270554A (en) | 1991-06-14 | 1993-12-14 | Cree Research, Inc. | High power high frequency metal-semiconductor field-effect transistor formed in silicon carbide |
US5155289A (en) | 1991-07-01 | 1992-10-13 | General Atomics | High-voltage solid-state switching devices |
US5170455A (en) | 1991-10-30 | 1992-12-08 | At&T Bell Laboratories | Optical connective device |
US5242841A (en) | 1992-03-25 | 1993-09-07 | Texas Instruments Incorporated | Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate |
US6344663B1 (en) | 1992-06-05 | 2002-02-05 | Cree, Inc. | Silicon carbide CMOS devices |
US5459107A (en) | 1992-06-05 | 1995-10-17 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
US5629531A (en) | 1992-06-05 | 1997-05-13 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
US5726463A (en) | 1992-08-07 | 1998-03-10 | General Electric Company | Silicon carbide MOSFET having self-aligned gate structure |
US5587870A (en) | 1992-09-17 | 1996-12-24 | Research Foundation Of State University Of New York | Nanocrystalline layer thin film capacitors |
JP3146694B2 (ja) | 1992-11-12 | 2001-03-19 | 富士電機株式会社 | 炭化けい素mosfetおよび炭化けい素mosfetの製造方法 |
US5506421A (en) | 1992-11-24 | 1996-04-09 | Cree Research, Inc. | Power MOSFET in silicon carbide |
KR100305123B1 (ko) | 1992-12-11 | 2001-11-22 | 비센트 비.인그라시아, 알크 엠 아헨 | 정적랜덤액세스메모리셀및이를포함하는반도체장치 |
US5342803A (en) | 1993-02-03 | 1994-08-30 | Rohm, Co., Ltd. | Method for isolating circuit elements for semiconductor device |
JP3117831B2 (ja) | 1993-02-17 | 2000-12-18 | シャープ株式会社 | 半導体装置 |
JPH0799312A (ja) | 1993-02-22 | 1995-04-11 | Texas Instr Inc <Ti> | 半導体装置とその製法 |
JP2811526B2 (ja) | 1993-04-19 | 1998-10-15 | 東洋電機製造株式会社 | 静電誘導ショットキー短絡構造を有する静電誘導型半導体素子 |
US6097046A (en) | 1993-04-30 | 2000-08-01 | Texas Instruments Incorporated | Vertical field effect transistor and diode |
US5371383A (en) | 1993-05-14 | 1994-12-06 | Kobe Steel Usa Inc. | Highly oriented diamond film field-effect transistor |
US5539217A (en) | 1993-08-09 | 1996-07-23 | Cree Research, Inc. | Silicon carbide thyristor |
US5479316A (en) | 1993-08-24 | 1995-12-26 | Analog Devices, Inc. | Integrated circuit metal-oxide-metal capacitor and method of making same |
JPH0766433A (ja) | 1993-08-26 | 1995-03-10 | Hitachi Ltd | 半導体整流素子 |
JPH07122749A (ja) | 1993-09-01 | 1995-05-12 | Toshiba Corp | 半導体装置及びその製造方法 |
US5510630A (en) | 1993-10-18 | 1996-04-23 | Westinghouse Electric Corporation | Non-volatile random access memory cell constructed of silicon carbide |
US5393993A (en) | 1993-12-13 | 1995-02-28 | Cree Research, Inc. | Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices |
US5396085A (en) | 1993-12-28 | 1995-03-07 | North Carolina State University | Silicon carbide switching device with rectifying-gate |
JPH07221327A (ja) * | 1994-02-01 | 1995-08-18 | Murata Mfg Co Ltd | 半導体装置 |
US5385855A (en) | 1994-02-24 | 1995-01-31 | General Electric Company | Fabrication of silicon carbide integrated circuits |
US5399887A (en) | 1994-05-03 | 1995-03-21 | Motorola, Inc. | Modulation doped field effect transistor |
US5488236A (en) | 1994-05-26 | 1996-01-30 | North Carolina State University | Latch-up resistant bipolar transistor with trench IGFET and buried collector |
CN1040814C (zh) | 1994-07-20 | 1998-11-18 | 电子科技大学 | 一种用于半导体器件的表面耐压区 |
US5523589A (en) | 1994-09-20 | 1996-06-04 | Cree Research, Inc. | Vertical geometry light emitting diode with group III nitride active layer and extended lifetime |
JPH0897441A (ja) | 1994-09-26 | 1996-04-12 | Fuji Electric Co Ltd | 炭化けい素ショットキーダイオードの製造方法 |
JPH08213607A (ja) | 1995-02-08 | 1996-08-20 | Ngk Insulators Ltd | 半導体装置およびその製造方法 |
US5510281A (en) | 1995-03-20 | 1996-04-23 | General Electric Company | Method of fabricating a self-aligned DMOS transistor device using SiC and spacers |
JP3521246B2 (ja) | 1995-03-27 | 2004-04-19 | 沖電気工業株式会社 | 電界効果トランジスタおよびその製造方法 |
DE69512021T2 (de) | 1995-03-31 | 2000-05-04 | Cons Ric Microelettronica | DMOS-Anordnung-Struktur und Verfahren zur Herstellung |
SE9501310D0 (sv) | 1995-04-10 | 1995-04-10 | Abb Research Ltd | A method for introduction of an impurity dopant in SiC, a semiconductor device formed by the mehtod and a use of a highly doped amorphous layer as a source for dopant diffusion into SiC |
EP0825988A1 (en) | 1995-05-17 | 1998-03-04 | E.I. Du Pont De Nemours And Company | Fungicidal cyclic amides |
JPH08316164A (ja) | 1995-05-17 | 1996-11-29 | Hitachi Ltd | 半導体素子の作成方法 |
US5734180A (en) | 1995-06-02 | 1998-03-31 | Texas Instruments Incorporated | High-performance high-voltage device structures |
US6078090A (en) | 1997-04-02 | 2000-06-20 | Siliconix Incorporated | Trench-gated Schottky diode with integral clamping diode |
JP3555250B2 (ja) | 1995-06-23 | 2004-08-18 | 株式会社デンソー | 車両用交流発電機及びショットキバリアダイオード |
US6693310B1 (en) | 1995-07-19 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
DE19530525A1 (de) | 1995-08-19 | 1997-02-20 | Daimler Benz Ag | Schaltkreis mit monolithisch integrierter PIN-/Schottky-Diodenanordnung |
US5967795A (en) | 1995-08-30 | 1999-10-19 | Asea Brown Boveri Ab | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
JPH11261061A (ja) | 1998-03-11 | 1999-09-24 | Denso Corp | 炭化珪素半導体装置及びその製造方法 |
DE19636302C2 (de) | 1995-09-06 | 1998-08-20 | Denso Corp | Siliziumkarbidhalbleitervorrichtung und Verfahren zur Herstellung |
US6573534B1 (en) | 1995-09-06 | 2003-06-03 | Denso Corporation | Silicon carbide semiconductor device |
JP4001960B2 (ja) | 1995-11-03 | 2007-10-31 | フリースケール セミコンダクター インコーポレイテッド | 窒化酸化物誘電体層を有する半導体素子の製造方法 |
US5972801A (en) | 1995-11-08 | 1999-10-26 | Cree Research, Inc. | Process for reducing defects in oxide layers on silicon carbide |
US6136728A (en) | 1996-01-05 | 2000-10-24 | Yale University | Water vapor annealing process |
US6133587A (en) | 1996-01-23 | 2000-10-17 | Denso Corporation | Silicon carbide semiconductor device and process for manufacturing same |
JPH09205202A (ja) | 1996-01-26 | 1997-08-05 | Matsushita Electric Works Ltd | 半導体装置 |
SE9601174D0 (sv) | 1996-03-27 | 1996-03-27 | Abb Research Ltd | A method for producing a semiconductor device having a semiconductor layer of SiC and such a device |
US5877045A (en) | 1996-04-10 | 1999-03-02 | Lsi Logic Corporation | Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition |
US5612567A (en) | 1996-05-13 | 1997-03-18 | North Carolina State University | Schottky barrier rectifiers and methods of forming same |
US5719409A (en) | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
US5763905A (en) | 1996-07-09 | 1998-06-09 | Abb Research Ltd. | Semiconductor device having a passivation layer |
SE9602745D0 (sv) | 1996-07-11 | 1996-07-11 | Abb Research Ltd | A method for producing a channel region layer in a SiC-layer for a voltage controlled semiconductor device |
US6002159A (en) | 1996-07-16 | 1999-12-14 | Abb Research Ltd. | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
US5917203A (en) | 1996-07-29 | 1999-06-29 | Motorola, Inc. | Lateral gate vertical drift region transistor |
SE9602993D0 (sv) | 1996-08-16 | 1996-08-16 | Abb Research Ltd | A bipolar semiconductor device having semiconductor layers of SiC and a method for producing a semiconductor device of SiC |
DE19633183A1 (de) | 1996-08-17 | 1998-02-19 | Daimler Benz Ag | Halbleiterbauelement mit durch Ionenimplantation eingebrachten Fremdatomen und Verfahren zu dessen Herstellung |
DE19633184B4 (de) | 1996-08-17 | 2006-10-05 | Daimlerchrysler Ag | Verfahren zur Herstellung eines Halbleiterbauelements mit durch Ionenimplantation eingebrachten Fremdatomen |
US5939763A (en) | 1996-09-05 | 1999-08-17 | Advanced Micro Devices, Inc. | Ultrathin oxynitride structure and process for VLSI applications |
EP0837508A3 (en) | 1996-10-18 | 1999-01-20 | Hitachi, Ltd. | Semiconductor device and electric power conversion apparatus therewith |
US6028012A (en) | 1996-12-04 | 2000-02-22 | Yale University | Process for forming a gate-quality insulating layer on a silicon carbide substrate |
US5837572A (en) | 1997-01-10 | 1998-11-17 | Advanced Micro Devices, Inc. | CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein |
SE9700141D0 (sv) | 1997-01-20 | 1997-01-20 | Abb Research Ltd | A schottky diode of SiC and a method for production thereof |
SE9700156D0 (sv) | 1997-01-21 | 1997-01-21 | Abb Research Ltd | Junction termination for Si C Schottky diode |
US6180958B1 (en) | 1997-02-07 | 2001-01-30 | James Albert Cooper, Jr. | Structure for increasing the maximum voltage of silicon carbide power transistors |
DE19809554B4 (de) | 1997-03-05 | 2008-04-03 | Denso Corp., Kariya | Siliziumkarbidhalbleitervorrichtung |
EP0865085A1 (en) | 1997-03-11 | 1998-09-16 | STMicroelectronics S.r.l. | Insulated gate bipolar transistor with high dynamic ruggedness |
JPH10284718A (ja) | 1997-04-08 | 1998-10-23 | Fuji Electric Co Ltd | 絶縁ゲート型サイリスタ |
JP3287269B2 (ja) | 1997-06-02 | 2002-06-04 | 富士電機株式会社 | ダイオードとその製造方法 |
DE19723176C1 (de) | 1997-06-03 | 1998-08-27 | Daimler Benz Ag | Leistungshalbleiter-Bauelement und Verfahren zu dessen Herstellung |
US6121633A (en) | 1997-06-12 | 2000-09-19 | Cree Research, Inc. | Latch-up free power MOS-bipolar transistor |
US5969378A (en) | 1997-06-12 | 1999-10-19 | Cree Research, Inc. | Latch-up free power UMOS-bipolar transistor |
JP3618517B2 (ja) | 1997-06-18 | 2005-02-09 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5877041A (en) | 1997-06-30 | 1999-03-02 | Harris Corporation | Self-aligned power field effect transistor in silicon carbide |
US6063698A (en) | 1997-06-30 | 2000-05-16 | Motorola, Inc. | Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits |
DE19832329A1 (de) | 1997-07-31 | 1999-02-04 | Siemens Ag | Verfahren zur Strukturierung von Halbleitern mit hoher Präzision, guter Homogenität und Reproduzierbarkeit |
JP3180895B2 (ja) | 1997-08-18 | 2001-06-25 | 富士電機株式会社 | 炭化けい素半導体装置の製造方法 |
CN1267397A (zh) | 1997-08-20 | 2000-09-20 | 西门子公司 | 具有预定的α碳化硅区的半导体结构及此半导体结构的应用 |
US6239463B1 (en) | 1997-08-28 | 2001-05-29 | Siliconix Incorporated | Low resistance power MOSFET or other device containing silicon-germanium layer |
WO1999013512A1 (de) | 1997-09-10 | 1999-03-18 | Infineon Technologies Ag | Halbleiterbauelement mit einer driftzone |
SE9704150D0 (sv) | 1997-11-13 | 1997-11-13 | Abb Research Ltd | Semiconductor device of SiC with insulating layer a refractory metal nitride layer |
JP3085272B2 (ja) | 1997-12-19 | 2000-09-04 | 富士電機株式会社 | 炭化けい素半導体装置の熱酸化膜形成方法 |
JPH11191559A (ja) | 1997-12-26 | 1999-07-13 | Matsushita Electric Works Ltd | Mosfetの製造方法 |
JPH11251592A (ja) | 1998-01-05 | 1999-09-07 | Denso Corp | 炭化珪素半導体装置 |
JP3216804B2 (ja) | 1998-01-06 | 2001-10-09 | 富士電機株式会社 | 炭化けい素縦形fetの製造方法および炭化けい素縦形fet |
JPH11266017A (ja) | 1998-01-14 | 1999-09-28 | Denso Corp | 炭化珪素半導体装置及びその製造方法 |
JPH11238742A (ja) | 1998-02-23 | 1999-08-31 | Denso Corp | 炭化珪素半導体装置の製造方法 |
JP3893725B2 (ja) | 1998-03-25 | 2007-03-14 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
JPH11330468A (ja) | 1998-05-20 | 1999-11-30 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
US6627539B1 (en) | 1998-05-29 | 2003-09-30 | Newport Fab, Llc | Method of forming dual-damascene interconnect structures employing low-k dielectric materials |
US6100169A (en) | 1998-06-08 | 2000-08-08 | Cree, Inc. | Methods of fabricating silicon carbide power devices by controlled annealing |
US6107142A (en) | 1998-06-08 | 2000-08-22 | Cree Research, Inc. | Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion |
US6316793B1 (en) | 1998-06-12 | 2001-11-13 | Cree, Inc. | Nitride based transistors on semi-insulating silicon carbide substrates |
US5960289A (en) | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
JP4123636B2 (ja) | 1998-06-22 | 2008-07-23 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
JP3959856B2 (ja) | 1998-07-31 | 2007-08-15 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
US6221700B1 (en) | 1998-07-31 | 2001-04-24 | Denso Corporation | Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities |
JP2000106371A (ja) | 1998-07-31 | 2000-04-11 | Denso Corp | 炭化珪素半導体装置の製造方法 |
US6972436B2 (en) | 1998-08-28 | 2005-12-06 | Cree, Inc. | High voltage, high temperature capacitor and interconnection structures |
US6246076B1 (en) | 1998-08-28 | 2001-06-12 | Cree, Inc. | Layered dielectric on silicon carbide semiconductor structures |
JP3616258B2 (ja) | 1998-08-28 | 2005-02-02 | 株式会社ルネサステクノロジ | ショットキーダイオードおよびそれを用いた電力変換器 |
SE9802909L (sv) | 1998-08-31 | 1999-10-13 | Abb Research Ltd | Metod för framställning av en pn-övergång för en halvledaranordning av SiC samt en halvledaranordning av SiC med pn-övergång |
EP1001459B1 (en) | 1998-09-09 | 2011-11-09 | Texas Instruments Incorporated | Integrated circuit comprising a capacitor and method |
JP3361062B2 (ja) | 1998-09-17 | 2003-01-07 | 株式会社東芝 | 半導体装置 |
JP4186337B2 (ja) | 1998-09-30 | 2008-11-26 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
US6204203B1 (en) | 1998-10-14 | 2001-03-20 | Applied Materials, Inc. | Post deposition treatment of dielectric films for interface control |
US6048766A (en) | 1998-10-14 | 2000-04-11 | Advanced Micro Devices | Flash memory device having high permittivity stacked dielectric and fabrication thereof |
US6239466B1 (en) | 1998-12-04 | 2001-05-29 | General Electric Company | Insulated gate bipolar transistor for zero-voltage switching |
US6190973B1 (en) | 1998-12-18 | 2001-02-20 | Zilog Inc. | Method of fabricating a high quality thin oxide |
JP2002535840A (ja) | 1999-01-12 | 2002-10-22 | オイペツク オイロペーイツシエ ゲゼルシヤフト フユール ライスツングスハルプライター エムベーハー ウント コンパニイ コマンデイートゲゼルシヤフト | メサ形縁端部を備えるパワー半導体素子 |
US6252288B1 (en) | 1999-01-19 | 2001-06-26 | Rockwell Science Center, Llc | High power trench-based rectifier with improved reverse breakdown characteristic |
US6228720B1 (en) | 1999-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Method for making insulated-gate semiconductor element |
JP3943749B2 (ja) | 1999-02-26 | 2007-07-11 | 株式会社日立製作所 | ショットキーバリアダイオード |
JP2000261006A (ja) * | 1999-03-12 | 2000-09-22 | Nippon Inter Electronics Corp | ショットキー接合形成用半導体基板、それを使用した半導体素子、およびショットキーバリアダイオード |
US6448160B1 (en) | 1999-04-01 | 2002-09-10 | Apd Semiconductor, Inc. | Method of fabricating power rectifier device to vary operating parameters and resulting device |
US6420225B1 (en) | 1999-04-01 | 2002-07-16 | Apd Semiconductor, Inc. | Method of fabricating power rectifier device |
US6399996B1 (en) | 1999-04-01 | 2002-06-04 | Apd Semiconductor, Inc. | Schottky diode having increased active surface area and method of fabrication |
US6238967B1 (en) | 1999-04-12 | 2001-05-29 | Motorola, Inc. | Method of forming embedded DRAM structure |
US6218680B1 (en) | 1999-05-18 | 2001-04-17 | Cree, Inc. | Semi-insulating silicon carbide without vanadium domination |
JP2000349081A (ja) | 1999-06-07 | 2000-12-15 | Sony Corp | 酸化膜形成方法 |
US6329675B2 (en) | 1999-08-06 | 2001-12-11 | Cree, Inc. | Self-aligned bipolar junction silicon carbide transistors |
US6365932B1 (en) | 1999-08-20 | 2002-04-02 | Denso Corporation | Power MOS transistor |
JP3630594B2 (ja) | 1999-09-14 | 2005-03-16 | 株式会社日立製作所 | SiCショットキーダイオード |
JP4192353B2 (ja) | 1999-09-21 | 2008-12-10 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
WO2001022498A1 (de) | 1999-09-22 | 2001-03-29 | Siced Electronics Development Gmbh & Co. Kg | Sic-halbleitervorrichtung mit einem schottky-kontakt und verfahren zu deren herstellung |
US6373076B1 (en) | 1999-12-07 | 2002-04-16 | Philips Electronics North America Corporation | Passivated silicon carbide devices with low leakage current and method of fabricating |
US6303508B1 (en) | 1999-12-16 | 2001-10-16 | Philips Electronics North America Corporation | Superior silicon carbide integrated circuits and method of fabricating |
US7186609B2 (en) | 1999-12-30 | 2007-03-06 | Siliconix Incorporated | Method of fabricating trench junction barrier rectifier |
US6703642B1 (en) | 2000-02-08 | 2004-03-09 | The United States Of America As Represented By The Secretary Of The Army | Silicon carbide (SiC) gate turn-off (GTO) thyristor structure for higher turn-off gain and larger voltage blocking when in the off-state |
US7125786B2 (en) | 2000-04-11 | 2006-10-24 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
US6475889B1 (en) | 2000-04-11 | 2002-11-05 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
US6784486B2 (en) * | 2000-06-23 | 2004-08-31 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions therein |
JP3523156B2 (ja) | 2000-06-30 | 2004-04-26 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6429041B1 (en) | 2000-07-13 | 2002-08-06 | Cree, Inc. | Methods of fabricating silicon carbide inversion channel devices without the need to utilize P-type implantation |
DE10036208B4 (de) | 2000-07-25 | 2007-04-19 | Siced Electronics Development Gmbh & Co. Kg | Halbleiteraufbau mit vergrabenem Inselgebiet und Konaktgebiet |
US6956238B2 (en) | 2000-10-03 | 2005-10-18 | Cree, Inc. | Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel |
US7067176B2 (en) | 2000-10-03 | 2006-06-27 | Cree, Inc. | Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment |
US6610366B2 (en) | 2000-10-03 | 2003-08-26 | Cree, Inc. | Method of N2O annealing an oxide layer on a silicon carbide layer |
US6767843B2 (en) | 2000-10-03 | 2004-07-27 | Cree, Inc. | Method of N2O growth of an oxide layer on a silicon carbide layer |
US6593620B1 (en) | 2000-10-06 | 2003-07-15 | General Semiconductor, Inc. | Trench DMOS transistor with embedded trench schottky rectifier |
JP3881840B2 (ja) | 2000-11-14 | 2007-02-14 | 独立行政法人産業技術総合研究所 | 半導体装置 |
US6548333B2 (en) | 2000-12-01 | 2003-04-15 | Cree, Inc. | Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment |
JP3940560B2 (ja) | 2001-01-25 | 2007-07-04 | 独立行政法人産業技術総合研究所 | 半導体装置の製造方法 |
JP3655834B2 (ja) * | 2001-03-29 | 2005-06-02 | 株式会社東芝 | 半導体装置 |
DE10214150B4 (de) | 2001-03-30 | 2009-06-18 | Denso Corporation, Kariya | Siliziumkarbidhalbleitervorrichtung und Verfahren zur Herstellung derselben |
JP4892787B2 (ja) | 2001-04-09 | 2012-03-07 | 株式会社デンソー | ショットキーダイオード及びその製造方法 |
US6524900B2 (en) | 2001-07-25 | 2003-02-25 | Abb Research, Ltd | Method concerning a junction barrier Schottky diode, such a diode and use thereof |
US20030025175A1 (en) | 2001-07-27 | 2003-02-06 | Sanyo Electric Company, Ltd. | Schottky barrier diode |
JP4026339B2 (ja) | 2001-09-06 | 2007-12-26 | 豊田合成株式会社 | SiC用電極及びその製造方法 |
JP4064085B2 (ja) | 2001-10-18 | 2008-03-19 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP3559971B2 (ja) | 2001-12-11 | 2004-09-02 | 日産自動車株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP4044332B2 (ja) | 2001-12-26 | 2008-02-06 | 関西電力株式会社 | 高耐電圧半導体装置 |
JP3778153B2 (ja) | 2002-02-19 | 2006-05-24 | 日産自動車株式会社 | 炭化珪素ショットキーダイオードおよびその製造方法 |
US7183575B2 (en) | 2002-02-19 | 2007-02-27 | Nissan Motor Co., Ltd. | High reverse voltage silicon carbide diode and method of manufacturing the same high reverse voltage silicon carbide diode |
US6855970B2 (en) | 2002-03-25 | 2005-02-15 | Kabushiki Kaisha Toshiba | High-breakdown-voltage semiconductor device |
DE10392870B4 (de) | 2002-06-28 | 2009-07-30 | National Institute Of Advanced Industrial Science And Technology | Verfahren zur Herstellung einer Halbleitervorrichtung und Halbleitervorrichtung |
JP4319810B2 (ja) * | 2002-07-16 | 2009-08-26 | 日本インター株式会社 | 半導体装置及びその製造方法 |
JP4086602B2 (ja) | 2002-09-17 | 2008-05-14 | 株式会社日立製作所 | 多気筒エンジンの制御装置及び制御方法 |
US7217950B2 (en) | 2002-10-11 | 2007-05-15 | Nissan Motor Co., Ltd. | Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same |
US7132321B2 (en) | 2002-10-24 | 2006-11-07 | The United States Of America As Represented By The Secretary Of The Navy | Vertical conducting power semiconductor devices implemented by deep etch |
DE10259373B4 (de) | 2002-12-18 | 2012-03-22 | Infineon Technologies Ag | Überstromfeste Schottkydiode mit niedrigem Sperrstrom |
US7221010B2 (en) | 2002-12-20 | 2007-05-22 | Cree, Inc. | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors |
US7026650B2 (en) | 2003-01-15 | 2006-04-11 | Cree, Inc. | Multiple floating guard ring edge termination for silicon carbide devices |
JP2004247545A (ja) | 2003-02-14 | 2004-09-02 | Nissan Motor Co Ltd | 半導体装置及びその製造方法 |
CN1532943B (zh) | 2003-03-18 | 2011-11-23 | 松下电器产业株式会社 | 碳化硅半导体器件及其制造方法 |
KR100900562B1 (ko) | 2003-03-24 | 2009-06-02 | 페어차일드코리아반도체 주식회사 | 향상된 uis 내성을 갖는 모스 게이트형 트랜지스터 |
US6979863B2 (en) | 2003-04-24 | 2005-12-27 | Cree, Inc. | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same |
US7074643B2 (en) | 2003-04-24 | 2006-07-11 | Cree, Inc. | Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same |
US20050012143A1 (en) | 2003-06-24 | 2005-01-20 | Hideaki Tanaka | Semiconductor device and method of manufacturing the same |
JP2005057080A (ja) | 2003-08-05 | 2005-03-03 | Nippon Inter Electronics Corp | 半導体装置 |
US20050104072A1 (en) | 2003-08-14 | 2005-05-19 | Slater David B.Jr. | Localized annealing of metal-silicon carbide ohmic contacts and devices so formed |
US7973381B2 (en) | 2003-09-08 | 2011-07-05 | International Rectifier Corporation | Thick field oxide termination for trench schottky device |
US7018554B2 (en) | 2003-09-22 | 2006-03-28 | Cree, Inc. | Method to reduce stacking fault nucleation sites and reduce forward voltage drift in bipolar devices |
CA2545628A1 (en) | 2003-11-12 | 2005-05-26 | Cree, Inc. | Methods of processing semiconductor wafer backsides having light emitting devices (leds) thereon and leds so formed |
JP2005167035A (ja) | 2003-12-03 | 2005-06-23 | Kansai Electric Power Co Inc:The | 炭化珪素半導体素子およびその製造方法 |
CN103199017B (zh) | 2003-12-30 | 2016-08-03 | 飞兆半导体公司 | 形成掩埋导电层方法、材料厚度控制法、形成晶体管方法 |
US7005333B2 (en) | 2003-12-30 | 2006-02-28 | Infineon Technologies Ag | Transistor with silicon and carbon layer in the channel region |
US7407837B2 (en) | 2004-01-27 | 2008-08-05 | Fuji Electric Holdings Co., Ltd. | Method of manufacturing silicon carbide semiconductor device |
JP2005303027A (ja) | 2004-04-13 | 2005-10-27 | Nissan Motor Co Ltd | 半導体装置 |
DE102005017814B4 (de) | 2004-04-19 | 2016-08-11 | Denso Corporation | Siliziumkarbid-Halbleiterbauelement und Verfahren zu dessen Herstellung |
US20060006394A1 (en) * | 2004-05-28 | 2006-01-12 | Caracal, Inc. | Silicon carbide Schottky diodes and fabrication method |
US7071518B2 (en) | 2004-05-28 | 2006-07-04 | Freescale Semiconductor, Inc. | Schottky device |
US7118970B2 (en) | 2004-06-22 | 2006-10-10 | Cree, Inc. | Methods of fabricating silicon carbide devices with hybrid well regions |
US7294860B2 (en) * | 2004-07-08 | 2007-11-13 | Mississippi State University | Monolithic vertical junction field effect transistor and Schottky barrier diode fabricated from silicon carbide and method for fabricating the same |
EP1619276B1 (en) | 2004-07-19 | 2017-01-11 | Norstel AB | Homoepitaxial growth of SiC on low off-axis SiC wafers |
US20060211210A1 (en) | 2004-08-27 | 2006-09-21 | Rensselaer Polytechnic Institute | Material for selective deposition and etching |
JP4777630B2 (ja) | 2004-09-21 | 2011-09-21 | 株式会社日立製作所 | 半導体装置 |
JP3914226B2 (ja) | 2004-09-29 | 2007-05-16 | 株式会社東芝 | 高耐圧半導体装置 |
JP4954463B2 (ja) | 2004-10-22 | 2012-06-13 | 三菱電機株式会社 | ショットキーバリアダイオード |
JP4899405B2 (ja) | 2004-11-08 | 2012-03-21 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
DE102004053761A1 (de) | 2004-11-08 | 2006-05-18 | Robert Bosch Gmbh | Halbleitereinrichtung und Verfahren für deren Herstellung |
US7304363B1 (en) | 2004-11-26 | 2007-12-04 | United States Of America As Represented By The Secretary Of The Army | Interacting current spreader and junction extender to increase the voltage blocked in the off state of a high power semiconductor device |
JP4764003B2 (ja) | 2004-12-28 | 2011-08-31 | 日本インター株式会社 | 半導体装置 |
US7737522B2 (en) | 2005-02-11 | 2010-06-15 | Alpha & Omega Semiconductor, Ltd. | Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction |
US9419092B2 (en) | 2005-03-04 | 2016-08-16 | Vishay-Siliconix | Termination for SiC trench devices |
US7615774B2 (en) | 2005-04-29 | 2009-11-10 | Cree.Inc. | Aluminum free group III-nitride based high electron mobility transistors |
US7544963B2 (en) | 2005-04-29 | 2009-06-09 | Cree, Inc. | Binary group III-nitride based high electron mobility transistors |
US8901699B2 (en) | 2005-05-11 | 2014-12-02 | Cree, Inc. | Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection |
US7679223B2 (en) | 2005-05-13 | 2010-03-16 | Cree, Inc. | Optically triggered wide bandgap bipolar power switching devices and circuits |
US7414268B2 (en) | 2005-05-18 | 2008-08-19 | Cree, Inc. | High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities |
JP4942134B2 (ja) | 2005-05-20 | 2012-05-30 | 日産自動車株式会社 | 炭化珪素半導体装置の製造方法 |
US7528040B2 (en) | 2005-05-24 | 2009-05-05 | Cree, Inc. | Methods of fabricating silicon carbide devices having smooth channels |
US20060267021A1 (en) | 2005-05-27 | 2006-11-30 | General Electric Company | Power devices and methods of manufacture |
JP4777699B2 (ja) | 2005-06-13 | 2011-09-21 | 本田技研工業株式会社 | バイポーラ型半導体装置およびその製造方法 |
GB0512095D0 (en) | 2005-06-14 | 2005-07-20 | Unilever Plc | Fabric softening composition |
US7548112B2 (en) | 2005-07-21 | 2009-06-16 | Cree, Inc. | Switch mode power amplifier using MIS-HEMT with field plate extension |
JP2007036052A (ja) | 2005-07-28 | 2007-02-08 | Toshiba Corp | 半導体整流素子 |
JP5303819B2 (ja) | 2005-08-05 | 2013-10-02 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
CN101263581B (zh) | 2005-09-16 | 2010-09-29 | 克里公司 | 其上有碳化硅功率器件的半导体晶圆的处理方法 |
US7304334B2 (en) | 2005-09-16 | 2007-12-04 | Cree, Inc. | Silicon carbide bipolar junction transistors having epitaxial base regions and multilayer emitters and methods of fabricating the same |
JP2007103784A (ja) | 2005-10-06 | 2007-04-19 | Matsushita Electric Ind Co Ltd | ヘテロ接合バイポーラトランジスタ |
US7345310B2 (en) | 2005-12-22 | 2008-03-18 | Cree, Inc. | Silicon carbide bipolar junction transistors having a silicon carbide passivation layer on the base region thereof |
US7592211B2 (en) | 2006-01-17 | 2009-09-22 | Cree, Inc. | Methods of fabricating transistors including supported gate electrodes |
JP4257921B2 (ja) | 2006-03-02 | 2009-04-30 | シャープ株式会社 | 折畳み式携帯電子機器 |
JP4781850B2 (ja) | 2006-03-03 | 2011-09-28 | ナップエンタープライズ株式会社 | 音声入力イヤーマイク |
JP2007305609A (ja) | 2006-04-10 | 2007-11-22 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP5560519B2 (ja) | 2006-04-11 | 2014-07-30 | 日産自動車株式会社 | 半導体装置及びその製造方法 |
JP2007287782A (ja) | 2006-04-13 | 2007-11-01 | Hitachi Ltd | メサ型バイポーラトランジスタ |
US7728403B2 (en) | 2006-05-31 | 2010-06-01 | Cree Sweden Ab | Semiconductor device |
US7372087B2 (en) | 2006-06-01 | 2008-05-13 | Northrop Grumman Corporation | Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage |
EP2674966B1 (en) | 2006-06-29 | 2019-10-23 | Cree, Inc. | Silicon carbide switching devices including P-type channels |
JP4921880B2 (ja) * | 2006-07-28 | 2012-04-25 | 株式会社東芝 | 高耐圧半導体装置 |
US7728402B2 (en) | 2006-08-01 | 2010-06-01 | Cree, Inc. | Semiconductor devices including schottky diodes with controlled breakdown |
US8432012B2 (en) | 2006-08-01 | 2013-04-30 | Cree, Inc. | Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same |
US8710510B2 (en) | 2006-08-17 | 2014-04-29 | Cree, Inc. | High power insulated gate bipolar transistors |
US7595241B2 (en) * | 2006-08-23 | 2009-09-29 | General Electric Company | Method for fabricating silicon carbide vertical MOSFET devices |
JP5046083B2 (ja) | 2006-08-24 | 2012-10-10 | 独立行政法人産業技術総合研究所 | 炭化珪素半導体装置の製造方法 |
JP5098293B2 (ja) | 2006-10-30 | 2012-12-12 | 富士電機株式会社 | ワイドバンドギャップ半導体を用いた絶縁ゲート型半導体装置およびその製造方法 |
JP2008147362A (ja) | 2006-12-08 | 2008-06-26 | Toyota Central R&D Labs Inc | 半導体装置 |
JP4314277B2 (ja) | 2007-01-11 | 2009-08-12 | 株式会社東芝 | SiCショットキー障壁半導体装置 |
US8384181B2 (en) | 2007-02-09 | 2013-02-26 | Cree, Inc. | Schottky diode structure with silicon mesa and junction barrier Schottky wells |
US8835987B2 (en) | 2007-02-27 | 2014-09-16 | Cree, Inc. | Insulated gate bipolar transistors including current suppressing layers |
JP4450241B2 (ja) | 2007-03-20 | 2010-04-14 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
JP4620075B2 (ja) | 2007-04-03 | 2011-01-26 | 株式会社東芝 | 電力用半導体素子 |
JP4356767B2 (ja) | 2007-05-10 | 2009-11-04 | 株式会社デンソー | ジャンクションバリアショットキーダイオードを備えた炭化珪素半導体装置 |
JP4375439B2 (ja) | 2007-05-30 | 2009-12-02 | 株式会社デンソー | ジャンクションバリアショットキーダイオードを備えた炭化珪素半導体装置 |
US8866150B2 (en) | 2007-05-31 | 2014-10-21 | Cree, Inc. | Silicon carbide power devices including P-type epitaxial layers and direct ohmic contacts |
JP4539684B2 (ja) | 2007-06-21 | 2010-09-08 | 株式会社デンソー | 炭化珪素半導体装置およびその製造方法 |
JP4333782B2 (ja) | 2007-07-05 | 2009-09-16 | 株式会社デンソー | ジャンクションバリアショットキーダイオードを備えた炭化珪素半導体装置 |
US7687825B2 (en) | 2007-09-18 | 2010-03-30 | Cree, Inc. | Insulated gate bipolar conduction transistors (IBCTS) and related methods of fabrication |
US8492771B2 (en) | 2007-09-27 | 2013-07-23 | Infineon Technologies Austria Ag | Heterojunction semiconductor device and method |
CN101855726B (zh) | 2007-11-09 | 2015-09-16 | 克里公司 | 具有台面结构及包含台面台阶的缓冲层的功率半导体器件 |
JP2009141062A (ja) | 2007-12-05 | 2009-06-25 | Panasonic Corp | 半導体装置及びその製造方法 |
US7989882B2 (en) | 2007-12-07 | 2011-08-02 | Cree, Inc. | Transistor with A-face conductive channel and trench protecting well region |
JP2009177028A (ja) * | 2008-01-25 | 2009-08-06 | Toshiba Corp | 半導体装置 |
US9640609B2 (en) | 2008-02-26 | 2017-05-02 | Cree, Inc. | Double guard ring edge termination for silicon carbide devices |
US7851881B1 (en) | 2008-03-21 | 2010-12-14 | Microsemi Corporation | Schottky barrier diode (SBD) and its off-shoot merged PN/Schottky diode or junction barrier Schottky (JBS) diode |
US7842590B2 (en) | 2008-04-28 | 2010-11-30 | Infineon Technologies Austria Ag | Method for manufacturing a semiconductor substrate including laser annealing |
JP5415018B2 (ja) | 2008-05-13 | 2014-02-12 | 新電元工業株式会社 | 半導体装置 |
US8232558B2 (en) | 2008-05-21 | 2012-07-31 | Cree, Inc. | Junction barrier Schottky diodes with current surge capability |
US8097919B2 (en) | 2008-08-11 | 2012-01-17 | Cree, Inc. | Mesa termination structures for power semiconductor devices including mesa step buffers |
US8497552B2 (en) | 2008-12-01 | 2013-07-30 | Cree, Inc. | Semiconductor devices with current shifting regions and related methods |
US8536582B2 (en) | 2008-12-01 | 2013-09-17 | Cree, Inc. | Stable power devices on low-angle off-cut silicon carbide crystals |
US8288220B2 (en) | 2009-03-27 | 2012-10-16 | Cree, Inc. | Methods of forming semiconductor devices including epitaxial layers and related structures |
US20100277839A1 (en) * | 2009-04-29 | 2010-11-04 | Agilent Technologies, Inc. | Overpower protection circuit |
JP5600411B2 (ja) | 2009-10-28 | 2014-10-01 | 三菱電機株式会社 | 炭化珪素半導体装置 |
US8372738B2 (en) * | 2009-10-30 | 2013-02-12 | Alpha & Omega Semiconductor, Inc. | Method for manufacturing a gallium nitride based semiconductor device with improved termination scheme |
US8704292B2 (en) * | 2010-02-23 | 2014-04-22 | Donald R. Disney | Vertical capacitive depletion field effect transistor |
US9557895B2 (en) | 2011-01-27 | 2017-01-31 | Hewlett Packard Enterprise Development Lp | Electronic book with changeable paths |
US9318623B2 (en) * | 2011-04-05 | 2016-04-19 | Cree, Inc. | Recessed termination structures and methods of fabricating electronic devices including recessed termination structures |
US9142662B2 (en) * | 2011-05-06 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with low source resistance |
EP2740327A4 (en) | 2011-08-04 | 2015-05-20 | 3M Innovative Properties Co | BARRIER ASSEMBLIES |
US8680587B2 (en) | 2011-09-11 | 2014-03-25 | Cree, Inc. | Schottky diode |
US8618582B2 (en) | 2011-09-11 | 2013-12-31 | Cree, Inc. | Edge termination structure employing recesses for edge termination elements |
US8664665B2 (en) | 2011-09-11 | 2014-03-04 | Cree, Inc. | Schottky diode employing recesses for elements of junction barrier array |
US9318624B2 (en) * | 2012-11-27 | 2016-04-19 | Cree, Inc. | Schottky structure employing central implants between junction barrier elements |
-
2011
- 2011-09-11 US US13/229,749 patent/US8680587B2/en active Active
-
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- 2012-09-07 JP JP2014529880A patent/JP6088518B2/ja active Active
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- 2012-09-07 WO PCT/US2012/054091 patent/WO2013036722A1/en active Application Filing
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- 2015-07-28 US US14/810,678 patent/US9865750B2/en active Active
-
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- 2017-02-02 JP JP2017017499A patent/JP6417432B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101385146A (zh) * | 2006-02-16 | 2009-03-11 | 财团法人电力中央研究所 | 肖特基结半导体元件及其制造方法 |
CN101467262A (zh) * | 2006-04-04 | 2009-06-24 | 半南实验室公司 | 结势垒肖特基整流器及其制造方法 |
CN101978502A (zh) * | 2008-03-17 | 2011-02-16 | 三菱电机株式会社 | 半导体器件 |
US20110207321A1 (en) * | 2010-02-19 | 2011-08-25 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device manufacturiing method |
US20110215338A1 (en) * | 2010-03-08 | 2011-09-08 | Qingchun Zhang | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105226102A (zh) * | 2014-06-25 | 2016-01-06 | 辛纳普蒂克斯显像装置合同会社 | 结势垒肖特基二极管及其制造方法 |
CN105226102B (zh) * | 2014-06-25 | 2019-05-31 | 辛纳普蒂克斯日本合同会社 | 结势垒肖特基二极管及其制造方法 |
CN106067415A (zh) * | 2015-04-24 | 2016-11-02 | 富士电机株式会社 | 碳化硅半导体装置的制造方法 |
CN106067415B (zh) * | 2015-04-24 | 2021-01-12 | 富士电机株式会社 | 碳化硅半导体装置的制造方法 |
CN108140676A (zh) * | 2015-10-30 | 2018-06-08 | 三菱电机株式会社 | 碳化硅半导体器件 |
CN108140676B (zh) * | 2015-10-30 | 2020-12-18 | 三菱电机株式会社 | 碳化硅半导体器件 |
CN110534583A (zh) * | 2019-08-01 | 2019-12-03 | 山东天岳电子科技有限公司 | 一种肖特基二极管及其制备方法 |
CN110571281A (zh) * | 2019-08-01 | 2019-12-13 | 山东天岳电子科技有限公司 | 一种混合PiN结肖特基二极管及制造方法 |
CN110534583B (zh) * | 2019-08-01 | 2023-03-28 | 山东天岳电子科技有限公司 | 一种肖特基二极管及其制备方法 |
CN110571281B (zh) * | 2019-08-01 | 2023-04-28 | 山东天岳电子科技有限公司 | 一种混合PiN结肖特基二极管及制造方法 |
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TW201324790A (zh) | 2013-06-16 |
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