CN103684440A - Clock and data recovery circuit and clock and data recovery - Google Patents
Clock and data recovery circuit and clock and data recovery Download PDFInfo
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- CN103684440A CN103684440A CN201210323865.2A CN201210323865A CN103684440A CN 103684440 A CN103684440 A CN 103684440A CN 201210323865 A CN201210323865 A CN 201210323865A CN 103684440 A CN103684440 A CN 103684440A
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Abstract
The invention discloses a clock and data recovery circuit which comprises a sequential data input end, a reference clock input end, a control circuit, a detection circuit and a controlled oscillator, wherein the sequential data input end is used for receiving sequential data, the reference clock input end is used for receiving a reference clock, the control circuit is used for selectively setting the clock and data recovery circuit in one of multiple stages, the detection circuit is used for generating a first regulation signal when the clock and data recovery circuit is operated in the frequency lock stage and generating a second regulation signal when the clock and data recovery circuit is operated in the clock and data recovery stage, and the controlled oscillator is used for generating a recovery clock according to the first regulation signal in the frequency lock stage, and generating a recovery clock according to the second regulation signal in the clock and data recovery stage.
Description
Technical field
The present invention is relevant to clock pulse and data recovery circuit, espespecially a kind of multimodal clock pulse and data recovery circuit (multi-mode clock and data recovery circuit) and associated method.
Background technology
In a communication system, receiving terminal need to be used clock pulse and data recovery circuit correctly to sample the signal receiving, yet along with clock pulse and the data volume of the system specification significantly raises, and some system, passive type fiberoptical networking (passive optical network for example, PON) and gigabit passive type fiberoptical networking (Gigabit-capable passive optical network, GPON) require receiving terminal within the short time, to complete the reply of clock pulse and data, for reaching requirement, the existing practice is in a phase-locked loop, to adopt a voltage-controlled oscillator to come locking frequency to provide receiving terminal one local clock pulse, and a lock controlled oscillator is set in addition carrys out quick lock in phase place, this lock controlled oscillator is subject to the control voltage identical with this voltage-controlled oscillator and controls, and after Frequency Locking then locking phase at once.
Although two oscillators are controlled by identical control voltage, in practice, but may produce because of the impact of technique or other factors not mating in frequency each other, and make follow-up data recovery more difficult, or when extreme situation (consecutive identical bit (Consecutive Identical Digits for example, CIDs), that is receive compared with long number object continuous 0 or continuous 1 sequence data) make the error rate (bit error rate, BER) increase.
Summary of the invention
Object of the present invention solves the problems referred to above at a kind of clock pulse of announcement and data recovery circuit and associated method.
According to embodiments of the invention, disclose a kind of clock pulse and data recovery circuit.This clock pulse and data recovery circuit include a sequence data input, with reference to clock pulse input, a control circuit, a testing circuit and a controlled oscillator processed.This sequence data input is used for receiving a sequence data.This is used for receiving one with reference to clock pulse with reference to clock pulse input.This control circuit is used for producing one of them that a control signal carrys out optionally this clock pulse and data recovery circuit to be set in a plurality of stages.This testing circuit is used for operating in a Frequency Locking during stage in this clock pulse and data recovery circuit, at least according to this, with reference to clock pulse, produce one first and adjust signal, and this clock pulse and data recovery circuit operate in a clock pulse and data recovery during the stage, at least according to this sequence data, produce one second and adjust signal.This controlled oscillator processed is used for operating in this Frequency Locking during the stage in this clock pulse and data recovery circuit, according to this first adjustment signal, produce a recovered clock, and this clock pulse and data recovery circuit operate in this clock pulse and data recovery during the stage, according to this, second adjust signal and produce this recovered clock.
According to embodiments of the invention, separately disclose a kind of clock pulse and data recovery method.This clock pulse and data recovery method include: receive a sequence data; Receive one with reference to clock pulse; When operating in a Frequency Locking during stage, at least according to this, with reference to clock pulse, produce one first and adjust signal, and with a controlled oscillator processed according to this first adjustment signal to produce a recovered clock; And when operating in a clock pulse and data recovery during the stage, at least according to this sequence data, produce one second and adjust signal, and with this controlled oscillator processed according to this second adjustment signal to produce this recovered clock.
In an embodiment, this controlled oscillator processed is a lock controlled oscillator.This clock pulse and data recovery circuit can divide three phases to complete respectively Frequency Locking, fast phase locking and clock pulse and data recovery, the mode of its operation shares this testing circuit of this lock controlled oscillator and part, and utilizes circuit that this control circuit switches common sparing to one of them of three phases.
In another embodiment, this controlled oscillator processed is a lock controlled oscillator.This clock pulse and data recovery circuit can divide three phases to complete respectively Frequency Locking, set time fast phase locking and clock pulse and data recovery, the mode of its operation is this testing circuit that shares this lock controlled oscillator and part, and utilizes circuit that this control circuit switches common sparing to one of them of three phases.
In another embodiment, it is a lock controlled oscillator that this controlled oscillator processed does not limit.This clock pulse and data recovery circuit can divide two stages to complete respectively Frequency Locking and clock pulse and data recovery, the mode of its operation is this testing circuit that shares this controlled oscillator processed and part, and utilizes this control circuit to switch one of them of circuit to two stage of common sparing.
In the present invention, for example, due to phase-locked loop circuit and clock pulse and the shared same controlled oscillator processed (lock controlled oscillator) of weakened phase restoring loop circuit, therefore compared to the way of using traditionally two lock controlled oscillators, the embodiment that the present invention discloses has exempted the ill effect that two lock controlled oscillators unmatched risk each other may occur and therefore cause.In addition, share testing circuit and oscillator and can also reduce the hardware cost in implementation.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the first embodiment of clock pulse of the present invention and data recovery circuit.
Fig. 2 is the sequential chart of a plurality of operational phases of the clock pulse shown in Fig. 1 and data recovery circuit.
Fig. 3 is the schematic diagram of the second embodiment of clock pulse of the present invention and data recovery circuit.
Fig. 4 is the schematic diagram of the 3rd embodiment of clock pulse of the present invention and data recovery circuit.
Wherein, description of reference numerals is as follows:
100,300,400 clock pulse and data recovery circuits;
102 sequence data inputs;
104 with reference to clock pulse input;
106,202,404 control circuits;
108 testing circuits;
110 lock controlled oscillators;
112 phase-locked loop lock detecting circuits;
114 clock pulse data recovery lock detecting circuits;
116,204,406 controllers;
118 detection modules;
120 charge pumps;
122 loop filters;
123 frequency eliminators;
124 phase frequency testing circuits;
126 phase detecting circuits;
128 multiplexers;
402 controlled oscillators processed.
Embodiment
At specification and in the middle of applying for a patent claim, used some vocabulary to censure specific element.In affiliated field, technical staff should understand, and same element may be called with different nouns by manufacturer.This specification and apply for a patent claim scope and be not used as distinguishing the mode of element with the difference of title, but the difference in function is used as the criterion of distinguishing with element.In the whole text, in the middle of specification and follow-up claim, be an open term mentioned " comprising ", therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this.Therefore, if describe a first device in literary composition, be coupled to one second device, represent that this first device can directly be electrically connected in this second device, or be indirectly electrically connected to this second device by other devices or connection means.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of the first embodiment of clock pulse of the present invention and data recovery circuit.In the present embodiment, clock pulse and data recovery circuit 100 include a sequence data input 102, with reference to clock pulse input 104, a control circuit 106, a testing circuit 108 and a lock controlled oscillator (gated oscillator) 110.Sequence data input 102 receives a sequence data DIN (data to be decoded that for example receiver of previous stage receives), and is coupled to respectively control circuit 106, testing circuit 108 and lock controlled oscillator 110.With reference to clock pulse input 104, for example receive one, with reference to clock pulse CLKREF (clock pulse that the quartz (controlled) oscillator of local side produces), and be coupled to respectively control circuit 106 and testing circuit 108.As shown in the figure, the input of control circuit 106 is coupled to respectively the output with reference to clock pulse input 104, sequence data input 102 and lock controlled oscillator 110, and the output of control circuit 106 is coupled to respectively the input of testing circuit 108 and the input of lock controlled oscillator 110.Control circuit 106 includes a phase-locked loop lock detecting circuit (PLL locking detector) 112, one clock pulse data recovery lock detecting circuit (CDR locking detector) 114 and one controller 116.
The input of testing circuit 108 is coupled to respectively with reference to the output of clock pulse input 104, sequence data input 102, control circuit 106 and the output of lock controlled oscillator 110, and the output of testing circuit 108 is coupled to the input of lock controlled oscillator 110.As shown in the figure, testing circuit 108 includes a detection module 118, a charge pump 120, a loop filter 122 and a frequency eliminator 123, and wherein detection module 118 includes a phase frequency testing circuit 124, a phase detecting circuit 126 and a multiplexer 128.In addition, the input of lock controlled oscillator 110 is coupled to respectively the output of sequence data input 102, control circuit 106 and the output of testing circuit 108, and the output of lock controlled oscillator 110 is coupled to respectively the input of control circuit 106 and the input of testing circuit 108.
Fig. 2 is the sequential chart of a plurality of operational phases of the clock pulse shown in Fig. 1 and data recovery circuit.It should be noted, in the middle of the clock pulse that the present invention discloses and data recovery circuit, use same set of hardware to carry out multimodal operation, be described in detail as follows.Three patterns in first embodiment of the invention are respectively a Frequency Locking stage, a phase place locked stage and a clock pulse and data recovery stage.What this Frequency Locking stage was performed is phase-locked loop operation, in this stage, local side (that is receiving terminal) can produce one and receive clock pulse, what follow-up phase place locked stage was performed is quick lock in operation, in this stage, lock controlled oscillator 110 can be adjusted the phase place of this reception clock pulse rapidly.Finally, what clock pulse and data recovery stage were performed is clock pulse and data recovery circuit operation, and in this stage, the phase-locked loop in Frequency Locking stage can be through suitable switching and configuration and become clock pulse and data recovery loop again.
Furthermore, when operating in this Frequency Locking stage (being the initial operation state of clock pulse and data recovery circuit 100), clock pulse and data recovery circuit 100 can be regarded as a phase-locked loop circuit, at this Frequency Locking under the stage, the control of the control signal SCTRL that multiplexer 128 in testing circuit 108, charge pump 120 and loop filter 122 are subject to exporting from control circuit 106 and the dynamic configuration of adjustment itself, for example multiplexer 128 is understood the one first detection signal SD1 that phase frequency testing circuit 124 is produced and is exported charge pump 120 to.Generally speaking, the frequency of the recovered clock CLKRCV that lock controlled oscillator 110 produces can be higher than the frequency with reference to clock pulse CLKREF, therefore, frequency eliminator 123 can be based on a predetermined value by frequency elimination recovered clock CLKRCV to produce a feedback clock pulse CLKFB, and phase frequency testing circuit 124 is for by feedback clock pulse CLKFB and difference reaction with reference to clock pulse CLKREF out, and make charge pump 120 produce one first charge pump output signal SC1 to export loop filter 122 to.In addition, whether frequency eliminator 123 can be selected implements (optional), and phase frequency testing circuit 124 be for by recovered clock CLKRCV with reference to the difference reaction of clock pulse CLKREF out, and make charge pump 120 produce the first charge pump output signal SC1 to export loop filter 122 to.Comprehensively above-mentioned, phase frequency testing circuit 124 can according to reference to clock pulse CLKREF and recovered clock CLKRCV (directly with reference to recovered clock CLKRCV or by feeding back clock pulse CLKFB indirect reference recovered clock CLKRCV) produce the first detection signal SD1.
When clock pulse and data recovery circuit 100 operate in this phase place locked stage (being second mode of operation of clock pulse and data recovery circuit 100 in first embodiment of the invention), the control signal SCTRL that control circuit 106 is exported can suspend the action of testing circuit 108, and the phase place of the recovered clock CLKRCV that lock controlled oscillator 110 the is exported phase place of lock sequence data DIN rapidly, now the clock pulse data recovery lock detecting circuit 114 in control circuit 106 can dynamically check the relativeness between recovered clock CLKRCV and sequence data DIN, once assert, clock pulse data recovery lock detecting circuit 114 locked, its one second lock detecting signal SL2 exporting will be upgraded to 1 by 0 as shown in Figure 2, and the control signal SCTRL (that is output of control circuit 106) of controller 116 outputs can make change to control accordingly testing circuit 108 and gate oscillator 110 simultaneously, in other words, this phase place locked stage has completed and has entered this follow-up clock pulse and data recovery stage.
When operating in this clock pulse and data recovery stage (being the 3rd mode of operation of clock pulse and data recovery circuit 100 in first embodiment of the invention), clock pulse and data recovery circuit 100 can be regarded as a clock pulse and data recovery circuit, at this clock pulse and data recovery under the stage, multiplexer 128 in testing circuit 108, the control of the control signal SCTRL that charge pump 120 and loop filter 122 are subject to exporting from control circuit 106 and the dynamic configuration of adjustment itself, the one second detection signal SD2 that for example multiplexer 128 can produce phase detecting circuit 126 exports charge pump 120 to, be noted that, as previously mentioned, the frequency of the recovered clock CLKRCV that lock controlled oscillator 110 produces can be higher than the frequency with reference to clock pulse CLKREF, therefore, frequency eliminator 123 can carry out frequency elimination to produce feedback clock pulse CLKFB to recovered clock CLKRCV based on a predetermined value, and phase detecting circuit 126 is used for by the difference reaction of feedback clock pulse CLKFB and sequence data DIN out, and make charge pump 120 produce one second charge pump output signal SC2 and export loop filter 122 to, similarly, in other application or implementation mode, whether frequency eliminator 123 can be selected implements, therefore, phase detecting circuit 126 is for by the difference reaction of recovered clock CLKRCV and sequence data DIN out, and make charge pump 120 produce the second charge pump output signal SC2 and export loop filter 122 to.Generally speaking, phase detecting circuit 124 can according to sequence data DIN and recovered clock CLKRCV (directly with reference to recovered clock CLKRCV or by feeding back clock pulse CLKFB indirect reference recovered clock CLKRCV) produce the second detection signal SD2.Loop filter 122 can be considered a low pass filter, its purposes is mainly the high-frequency noise part that reduces charge pump output signal SC2, and the one second adjustment signal SLF2 that now loop filter 122 is exported is testing circuit 108 in clock pulse and the output signal in data recovery stage.At this clock pulse and data recovery in the stage, the effect of lock controlled oscillator 110 is as this Frequency Locking stage and as a simple oscillator controlled processed, and can dynamically change according to the second adjustment signal SLF2 the frequency of exported recovered clock CLKRCV.Because clock pulse and data recovery circuit 100 have completed the locking of phase place when this phase place locked stage finishes, therefore at ensuing this clock pulse and data recovery in the stage, clock pulse and data recovery loop can stably be followed the trail of and lock sequence data DIN.
In some system, gigabit passive type fiberoptical networking for example, in phase place locked stage (being this above-mentioned phase place locked stage), lower time series data DIN is the adjustment sequence (training sequence) of continuous 0,1 conversion, and requires clock pulse and data recovery circuit within the time, to complete phase place locking at 25 bits.Because lock controlled oscillator originally just has the characteristic of quick lock in, in general can complete locking a bit time, therefore in one second disclosed embodiment, can further remove the clock pulse data recovery lock detecting circuit 114 in first embodiment of the invention, coupled system standard and instead use a fixing locking time, and in through after this fixing locking time, automatically by phase place locked stage, switch to clock pulse and data recovery stage.
Please refer to Fig. 3, Fig. 3 is the schematic diagram of the second embodiment of clock pulse of the present invention and data recovery circuit.In the present embodiment, clock pulse and data recovery circuit 300 include a control circuit 202 with above-mentioned sequence data input 102, with reference to clock pulse input 104, testing circuit 108 and lock controlled oscillator 110.Clock pulse and data recovery circuit 300 are that with the difference of clock pulse and data recovery circuit 100 control circuit 202 comprises a controller 204 and aforesaid phase-locked loop lock detecting circuit 112, and do not comprise clock pulse data recovery lock detecting circuit 114.
The operation in the Frequency Locking stage in second embodiment of the invention is identical with the operation in the Frequency Locking stage in first embodiment of the invention, finishing this Frequency Locking after the stage, clock pulse and data recovery circuit 300 can enter a phase place locked stage equally, and rest on one set time of this phase place locked stage (for example 25 bit times), for example, controller 204 can use a counter when this set time has met, initiatively send that control signal SCTRL controls clock pulse and data recovery circuit 300 switches to a clock pulse and data recovery stage by this phase place locked stage.Yet it is only example that usage counter comes control phase locked stage and clock pulse and the switching in data recovery stage, non-restrictive condition of the present invention, any design that can reach similar functions, all belongs to the scope that the present invention is contained.In addition, this clock pulse in second embodiment of the invention is identical with clock pulse and data recovery stage in first embodiment of the invention with the data recovery stage.The function of controller 204 and class of operation are similar to function and the operation of controller 110, difference is that controller 204 can be controlled voluntarily clock pulse after a Preset Time and data recovery circuit 300 switches to clock pulse and data recovery stage by phase place locked stage, without the second lock detecting signal SL2 providing with reference to clock pulse data recovery lock detecting circuit 114.Those skilled in the art, should understand the details of operation of the clock pulse shown in Fig. 3 and data recovery circuit 300, therefore omit, carefully state.
Please refer to Fig. 4, Fig. 4 is the schematic diagram of the 3rd embodiment of clock pulse of the present invention and data recovery circuit.In the present embodiment, clock pulse and data recovery circuit 400 include a controlled oscillator 402 processed, a control circuit 404 with above-mentioned sequence data input 102, with reference to clock pulse input 104, testing circuit 108 and controlled oscillator processed 402.In the present embodiment, controlled oscillator 402 processed is lock controlled oscillator not necessarily, and control circuit 404 comprises a controller 406 and above-mentioned phase-locked loop lock detecting circuit 112.
Because the clock pulse in the first and second embodiment and data recovery stage (being clock pulse and data recovery pattern) have the function of phase place locking, just the phase place lock speed under initial condition is not so good as the fast of lock controlled oscillator, if there is no again the strict data recovery speed of standard in general system, in practice, might not need to use lock controlled oscillator, meaning can directly enter the pattern of clock pulse and data recovery circuit after Frequency Locking.For example, the lock controlled oscillator 110 replacing in the present invention first and the second embodiment with controlled oscillator 402 processed in the 3rd embodiment, and the operation in the operation in the Frequency Locking stage in the present embodiment and Frequency Locking stage in the present invention first and the second embodiment is identical, and finishing this Frequency Locking after the stage, controller 406 meetings control clock pulse according to the first lock detecting signal SL1 of phase-locked loop lock detecting circuit 112 and data recovery circuit 400 directly enters a clock pulse and data recovery stage, and this clock pulse is identical with clock pulse and the operation in data recovery stage in the present invention first and the second embodiment with the operation in data recovery stage.Those skilled in the art should understand the details of operation of the clock pulse shown in Fig. 4 and data recovery circuit 400, therefore omit, carefully state.
Note that charge pump in above-described embodiment 120 separately can dynamically adjust according to control signal SCTRL the configuration of charge pump.For example, compared to the Frequency Locking stage, charge pump 120 had different circuit frameworks or under same circuit framework, has different element characteristic (for example different resistance values and/or capacitance) in clock pulse and data recovery stage.Similarly, loop filter 122 in above-described embodiment also can dynamically be adjusted according to control signal SCTRL the configuration of loop filter, for example, compared to the Frequency Locking stage, loop filter 122 can have different circuit frameworks or under same circuit framework, have different element characteristic (for example different resistance values and/or capacitance) in clock pulse and data recovery stage.
The foregoing is only moral embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to the covering scope of the claims in the present invention.
Claims (17)
1. clock pulse and a data recovery circuit, include:
One sequence data input, is used for receiving a sequence data;
One with reference to clock pulse input, is used for receiving one with reference to clock pulse;
One control circuit, is used for producing one of them that a control signal carrys out optionally this clock pulse and data recovery circuit to be set in a plurality of stages;
One testing circuit, be used for operating in a Frequency Locking during stage in this clock pulse and data recovery circuit, at least according to this, with reference to clock pulse, produce one first and adjust signal, and operate in a clock pulse and data recovery during the stage in this clock pulse and data recovery circuit, at least according to this sequence data, produce one second and adjust signal; And
One controlled oscillator processed, be used for operating in this Frequency Locking during the stage in this clock pulse and data recovery circuit, according to this first adjustment signal, produce a recovered clock, and operate in this clock pulse and data recovery during the stage in this clock pulse and data recovery circuit, according to this, second adjust signal and produce this recovered clock.
2. clock pulse as claimed in claim 1 and data recovery circuit, wherein this controlled oscillator processed is a lock controlled oscillator, and when this clock pulse and data recovery circuit operate in a phase place locked stage, this lock controlled oscillator receives this sequence data and makes the phase place of this recovered clock and the Phase synchronization of this sequence data according to this sequence data.
3. clock pulse as claimed in claim 2 and data recovery circuit, wherein this control circuit separately comprises:
One phase-locked loop lock detecting circuit, is used for reference to clock pulse and this recovered clock, producing one first lock detecting signal according to this; And
One controller, is coupled to this phase-locked loop lock detecting circuit, is used for producing this control signal according to this first lock detecting signal, to control this clock pulse and data recovery circuit, by this Frequency Locking stage, switches to this phase place locked stage.
4. clock pulse as claimed in claim 3 and data recovery circuit, wherein this control circuit separately comprises:
One clock pulse data recovery lock detecting circuit, is used for producing one second lock detecting signal according to this sequence data and this recovered clock;
Wherein this controller separately produces this control signal according to this second lock detecting signal, to control this clock pulse and data recovery circuit, by this phase place locked stage, switches to this clock pulse and data recovery stage.
5. clock pulse as claimed in claim 1 and data recovery circuit, wherein this testing circuit includes:
One detection module, be used for operating in this Frequency Locking during the stage in this clock pulse and data recovery circuit, according to this, with reference to clock pulse and this recovered clock, produce one first detection signal, and operate in this clock pulse and data recovery during the stage in this clock pulse and data recovery circuit, according to this sequence data and this recovered clock, produce one second detection signal;
One charge pump, be coupled to this detection module, be used for operating in this Frequency Locking during the stage in this clock pulse and data recovery circuit, according to this first detection signal, produce one first charge pump output signal, and operate in this clock pulse and data recovery during the stage in this clock pulse and data recovery circuit, according to this second detection signal, produce one second charge pump output signal; And
One loop filter, be coupled between this charge pump and this controlled oscillator processed, be used for operating in this Frequency Locking during the stage in this clock pulse and data recovery circuit, according to this first charge pump output signal, produce this first adjustment signal, and operate in this clock pulse and data recovery during the stage in this clock pulse and data recovery circuit, according to this second charge pump output signal, produce this and second adjust signal.
6. clock pulse as claimed in claim 5 and data recovery circuit, wherein this charge pump is separately dynamically adjusted a configuration of this charge pump according to this control signal.
7. clock pulse as claimed in claim 5 and data recovery circuit, wherein this loop filter is separately dynamically adjusted a configuration of this loop filter according to this control signal.
8. clock pulse as claimed in claim 5 and data recovery circuit, wherein this detection module includes:
One phase frequency testing circuit, is used for reference to clock pulse and this recovered clock, producing this first detection signal according to this;
One phase detecting circuit, is used for producing this second detection signal according to this sequence data and this recovered clock; And
One multiplexer, be coupled to this phase frequency testing circuit and this phase detecting circuit, be used for operating in this Frequency Locking during the stage in this clock pulse and data recovery circuit, export this first detection signal to this charge pump, and operate in this clock pulse and data recovery during the stage in this clock pulse and data recovery circuit, export this second detection signal to this charge pump.
9. clock pulse as claimed in claim 1 and data recovery circuit, wherein this control circuit comprises:
One phase-locked loop lock detecting circuit, is used for reference to clock pulse and this recovered clock, producing a lock detecting signal according to this; And
One controller, is coupled to this phase-locked loop lock detecting circuit, in order to produce this control signal according to this lock detecting signal, to control this clock pulse and data recovery circuit, by this Frequency Locking stage, switches to this clock pulse and data recovery stage.
10. clock pulse and a data recovery method, include:
Receive a sequence data;
Receive one with reference to clock pulse;
When operating in a Frequency Locking during stage, at least according to this, with reference to clock pulse, produce one first and adjust signal, and with a controlled oscillator processed according to this first adjustment signal to produce a recovered clock; And
When operating in a clock pulse and data recovery during the stage, at least according to this sequence data, produce one second and adjust signal, and with this controlled oscillator processed according to this second adjustment signal to produce this recovered clock.
11. clock pulses as claimed in claim 10 and data recovery method, wherein this controlled oscillator processed is a lock controlled oscillator, and the method separately comprises:
When operating in a phase place locked stage, with this lock controlled oscillator receive this sequence data and at least according to this sequence data so that the phase place of this recovered clock and the Phase synchronization of this sequence data.
12. clock pulses as claimed in claim 11 and data recovery method, separately comprise:
According to this, with reference to clock pulse and this recovered clock, produce one first lock detecting signal; And
According to this first lock detecting signal, control and switch to this phase place locked stage by this Frequency Locking stage.
13. clock pulses as claimed in claim 12 and data recovery method, separately comprise:
According to this sequence data and this recovered clock, produce one second lock detecting signal; And
According to this second lock detecting signal, control by this phase place locked stage and switch to this clock pulse and data recovery stage.
14. clock pulses as claimed in claim 10 and data recovery method, wherein at least produce this first step of adjusting signal according to this with reference to clock pulse and comprise:
According to this, with reference to clock pulse and this recovered clock, produce one first detection signal;
With a charge pump according to this first detection signal to produce one first charge pump output signal; And
With a loop filter, according to this first charge pump output signal, to produce this, first adjust signal; And
At least according to this sequence data, producing this second step of adjusting signal comprises:
According to this sequence data and this recovered clock, produce one second detection signal;
With this charge pump according to this second detection signal to produce one second charge pump output signal; And
With this loop filter, according to this second charge pump output signal, to produce this, second adjust signal.
15. clock pulses as claimed in claim 14 and data recovery method, separately comprise:
Dynamically adjust a configuration of this charge pump.
16. clock pulses as claimed in claim 14 and data recovery method, separately comprise:
Dynamically adjust a configuration of this loop filter.
17. clock pulses as claimed in claim 10 and data recovery method, separately comprise:
According to this, with reference to clock pulse and this recovered clock, produce a lock detecting signal; And
According to this lock detecting signal, control and switch to this clock pulse and data recovery stage by this Frequency Locking stage.
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| CN201210323865.2A CN103684440B (en) | 2012-09-04 | 2012-09-04 | Clock pulse and data recovery circuit and clock pulse and data recovery method |
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| CN201210323865.2A CN103684440B (en) | 2012-09-04 | 2012-09-04 | Clock pulse and data recovery circuit and clock pulse and data recovery method |
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| CN104253621A (en) * | 2014-06-30 | 2014-12-31 | 友达光电股份有限公司 | Data receiver and data receiving method |
| CN106533433A (en) * | 2015-09-09 | 2017-03-22 | 晨星半导体股份有限公司 | Clock pulse data replying device, clock pulse data replying method and phase detector |
| CN107612547A (en) * | 2016-07-11 | 2018-01-19 | 创意电子股份有限公司 | Lock loss detection device, lock loss detection method and clock data recovery circuit |
| CN107800427A (en) * | 2016-09-05 | 2018-03-13 | 创意电子股份有限公司 | Clock data recovery module |
| CN108595138A (en) * | 2018-02-21 | 2018-09-28 | 友达光电股份有限公司 | data acquisition method and device |
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| CN107612547B (en) * | 2016-07-11 | 2020-10-02 | 创意电子股份有限公司 | Lock loss detection device, lock loss detection method and clock data recovery circuit |
| CN107800427A (en) * | 2016-09-05 | 2018-03-13 | 创意电子股份有限公司 | Clock data recovery module |
| CN107800427B (en) * | 2016-09-05 | 2021-04-06 | 创意电子股份有限公司 | Clock data recovery module |
| CN108595138A (en) * | 2018-02-21 | 2018-09-28 | 友达光电股份有限公司 | data acquisition method and device |
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