CN103678728B - A kind of construction method of High-speed Data Recording System based on FPGA+DSP framework - Google Patents
A kind of construction method of High-speed Data Recording System based on FPGA+DSP framework Download PDFInfo
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Abstract
The construction method of a kind of High-speed Data Recording System based on FPGA+DSP framework, including following five steps；Step one: record system initialization and self-inspection；Step 2: raw data acquisition；The data gathered are needed to be divided into 3 parts: the reference voltage that 1.AD chip MAX1270 gathers；2.485 communication interface end transmission original data signals；The data such as 3.GSP is punctual, ephemeris information；Step 3: DSP core control chip write principal function, control system flow process；Step 4: fpga core control chip controls FLASH storage chip and realizes data storage；Step 5: PC end TT&C software realizes digital independent analysis；Digital data recording system completes data record in the case of being not connected with PC, is connected with PC by USB interface afterwards, is stored data as the form of Excel form by PC end TT&C software, it is simple to be analyzed data.
Description
Technical field:
The present invention relates to the construction method of a kind of High-speed Data Recording System based on FPGA+DSP framework, should
Design belongs to communication technical field.
Background technology:
In modern communication develops, data communication miscellaneous has already taken up critical role.Increasingly
In the case of Duo, storage and analysis to real time data become user's demand widely.And grind in various science
Studying carefully with detection, storing data and analyzing becomes a kind of important and necessary means especially.Data are deposited
Storage equipment (being commonly called as black box) has been obtained for much being widely applied in real life.Flying as applied
In machine, the various flight parameters recording black box record are the weights searched after aircraft has an accident and analyze reason
Will foundation.Additionally, black box vehicle-mounted, carrier-borne is the most gradually applied.Even if but in civil area, number
Such as cost is there is also high, the shortcomings such as applied environment is harsh according to recording equipment.For these reasons, this patent
Application provides the digital data recording system of a kind of designed, designed.
Summary of the invention:
1, purpose: present invention aim at providing a kind of high-speed data recording based on FPGA+DSP framework
System and construction method thereof, it is capable of real-time recorded data and the function of PC environment reading data, originally
System designs with FPGA Yu DSP as master devices, is equipped with bus communication interface, analog data collection
Interface and PC data communication interface.Whole system, with various power modules for power supply basis, is turned by 5V power supply
Change various level supply chip into normally to work.The present invention is mainly completed by VHDL hardware description language
Fpga core control chip function, C language realizes DSP core control chip function, and completion system designs.
2, technical scheme: the purpose of the present invention is achieved through the following technical solutions.
(1) a kind of High-speed Data Recording System based on FPGA+DSP framework, this system includes: PC end
TT&C software, fpga core control chip, DSP core control chip, power supply chip, FLASH store
Chip, usb communication chip, HDLC protocol communication chip, A/D chip and GPS communication daughter board.They
Between position annexation and signal trend be: in the entire system, fpga core control chip control
The USB module of PC communication when data are uploaded, cache module when communicating with DSP core control chip,
The module for reading and writing of FLASH storage chip, the control of GPS communication daughter board, and bus communication module are i.e.
HDLC protocol communication chip sends, accepts data module.DSP core control chip controls data transmission note
System self-test under record pattern, Analog Data Acquistion Module, and logical with fpga core control chip
Letter module.Power supply chip is connected with each chip, it is provided that the voltage needed for whole system work.System construction drawing
As shown in Figure 1.
The TT&C software VC of PC end is designed.The work that it mainly completes is at hardware system and PC
During communication, demonstrate data at PC end, it is simple to be analyzed.This TT&C software is with interface processing and USB
Interface Controller is main, is sent bookbinding parameter by interface to master control borad, uploads the orders such as data, and will obtain
Data be stored as Excel file, on interface, show relevant information simultaneously.The population structure of software such as figure
Shown in 2, Interface Control and display, instruction transmission, data receiver and data can be divided into process four parts.
The workflow of the TT&C software of PC end is substantially such as workflow diagram as shown in Figure 3:
A. opening software, whether detection USB device connects；
B. starting shooting and send self-inspection order from trend equipment, whether detection equipment connects normally；
C. can start test pattern, detection functions of the equipments are the most normal；
D. the data reading and drawing on interface FLASH chip store information；
E. the up-to-date data once stored in memory block are searched；
F. control the director data that reception equipment is uploaded, frame head part key message is shown on interface；
G. the director data received is stored in computer with the form of Excel；
H. off device, analytical data.
This software interface unit has provided the user parameter input, instruction controls the input interfaces such as button, and has
The functions such as standby display storage state, subpackage is ordered instruction area, FLASH control zone, is searched data information area, number
Showing district and six, data frame originating point information viewing area part according to read area, memory map, respective function is as follows:
Binding instructio district includes address parameter input frame, address code send button, antenna select button etc., complete
The multiple functions such as order line answering machine data record analysis device address code bookbinding in pairs, sky line options and switching
Control.
FLASH control zone completes to remove the function of FLASH all storages data.
Search data information area mainly have comprise lookup internal memory up-to-date storage position and display memory scattergram by
Key, latest page is initial, latest page terminates and initiates leader will display information.
There are two buttons in digital independent district: reads and saves as Excel.Read start page and read termination page table
Show the scope reading FLASH；Currently read bag number and read bag number for showing Load Game.
It is a pie chart viewing area that memory map shows district, is controlled by the display memory scattergram in memory management district.
Data information area the first row is title, represents frame head, initial address and end address.At most can show front 100
Group data.
Described fpga core control chip is the XC5VLX50T that Xilinx company produces.XC5VLX50T
Have 1M system door, 7200 slices, at most can use the distributed RAM memory space of 480Kbits,
Up to 7200 user's I/O interfaces.The up to internal clock rates of 550MHz, the data of I/O interface
Transfer rate is up to more than 840Mb/s.It addition, this model FPGA has high-performance clock control circuit,
Up to 12 digital dock control modules have the spies such as the compensation of accurate clock phase, high-resolution phase skew
Point.Many performances make XC5VLX50T disclosure satisfy that all demands that system designs, and enter having system
Too much waste resource is not had while one step upgrading, perfect in shape and function.Fpga core control chip belongs to
The core main control part of the present invention, the network interface module of PC communication when responsible data are uploaded, when communicating with DSP
Cache module, the module for reading and writing of FLASH storage chip, GPS daughter board controls, and bus communication module
I.e. HDLC communication protocol sends, accepts data module.
Described DSP core control chip is working-flow main control part, is responsible for data transfer record pattern
Under System self-test, Analog Data Acquistion Module, and with the communication of fpga core control chip.Pin
Technology requirement to native system, DSP core control chip uses the TMS320F2812 of TI company.
TMS320F2812 has the high-performance static state CMOS manufacturing technology of 150MHz；High-effect 32BitCPU
It is capable of breathing out not bus structures, it is possible to quick-speed interruption responds；4M linear program addressing space and 4M number
According to addressing space；Additionally, there is the SARAM of Flash and 18Kx16 of 128Kx16 on chip, 16
12 analog-to-digital conversion modules (ADC) of channel.In this digital data recording system, DSP core control chip master
The external interface wanted has level acquisition interface, gps data coffret and controls core with fpga core
The data of sheet and address interface, its external connection figure is as shown in Figure 4.Wherein DSP core control chip with
GPS module and level acquisition module are directly connected to, owing to DSP2812 chip provides a SCI
Interface, defines the interface between GPS module by the conversion of RS232 level, complete by this interface
Become the communication between GPS module；Additionally 12 AD on one 16 tunnel of DSP2812 built-in chip type adopt
Storage, the collection voltage range of this AD harvester is 0～3V, by adding corresponding divider resistance on hardware
And the increase of voltage reversal circuit realiration measurement scope, the level input gathering-13V～+13V can be met.
And the connection between DSP core control chip and fpga core control chip uses EMIF A interface, this
The memorizer of kind of interface support include synchronous dynamic ram (SDRAM), asynchronous device (asynchronous FIFO,
ROM etc.), the outside device etc. sharing memory space.Fpga core control chip controls with DSP core
Chip carries out synchronous data communication by EMIF A, needs the EBI of interconnection to include data/address bus XD
(32bit), address bus XA (20bit), spatial choice CE (4bit), byte input enables BE (4bit),
Write enable signal SSWE, output enables SSOE, reads to enable signal SSRE, synchronizes to read clock ECLKOUT.
For other auxiliary signal, such as bus control interface (HOLD, HOLDA), asynchronous communication interface
(ARDY) signal such as, as system reserve, has also been connected on fpga core control chip.In addition DSP
Although kernel control chip is not directly connected to FLASH on hardware, middle by fpga core control
Coremaking sheet is changed, and simply by the data wire of FLASH and ground inside fpga core control chip
Location line has carried out simple decoding and has processed so that DSP core control chip can be by less exterior I O
Pin processes FLASH, saves the exterior I O resource that DSP core control chip is valuable.And FPGA
Kernel control chip is not engaged in more controlling in the middle of this.DSP core control chip attachment structure figure is such as
Shown in Fig. 4.
Described power supply chip is PTH05000 chip, it is possible to provide the output voltage of-0.6～10V.Power supply chip
Voltage needed for whole system work is provided.The present invention use kind of a voltage: 27V, 5V, 1.0V, 1.9V,
2.5V and 3.3V.Wherein, 1.0V is the kernel supply voltage of fpga core control chip, and 1.9V is
The core voltage of DSP core control chip work, 3.3V is fpga core control chip and DSP core
The I/O supply voltage of control chip and the supply voltage of other chip, 2.5V is peripheral chip running voltage.
Owing to external system only provides 5V and 27V voltage to record system, so in logging recorder system hardware,
Need design voltage change-over circuit.
Described FLASH storage chip is K9F8G08U0M chip, and this chip-stored amount is up to 8Gbit,
Separately there is 256Mbit memory space as standby, right by the level change enabling, controlling pin is realized
The read-write operation of FLASH chip.FLASH storage chip is the storage part of system, is mainly responsible for data
Storage, be controlled by fpga core control chip, it is simple to carry out test post analysis.
Described usb communication chip is the EZ-USB FX2 chip CY7C68013 conduct that Cypress company produces
Connect the device chip of the two.CY7C68013 is USB2.0 agreement, is divided into port, GPIF and Slave
Tri-kinds of working methods of FIFO.The most lower theoretical signal rate up to 12Mbps, the most lower signal rate up to
480Mbps.When system is connected with PC, user can send instruction from PC environmental interface to system, enters
Line command bookbinding or to the lookup of canned data, read, erasing etc..Fpga core control chip designs
Include decoding module and the control module of network interface data transmission that PC instructs.When communicating with PC, principle is such as
Shown in Fig. 5.For ease of communication, facilitating system synergistic working, USB uses Slave FIFO mode of operation,
Chip is controlled by fpga core control chip.Fpga core control chip is believed according to FIFO empty full scale will
The data/address bus of number control chip, controls the read-write enable etc. in bus, can realize the high speed of data completely
Transmission.The initialization program of chip is stored in the middle of the firmware chip 24LC64 of matched work.Pass through
Write firmware program and can select the mode of operation of 68013, and the FIFO storage size of inside, data
Transmission direction etc..PC environment combines the CY7C68013 corresponding A PI function library that Cypress company provides,
Visual interface platform is write, it is simple to order, the transmission of data and acceptance by VC++.During work, boundary
Face platform sends order to system, and firmware program selects FIFO port according to command determination.Data pass through FIFO
It is transmitted, completes order, the transmission of data and reading.
Native system communicates with external equipment--use standard HDLC (High-level during transmitting and receiving data
Data Link Control) communication protocol.HDLC protocol is the high progression that International Organization for Standardization ISO formulates
According to link control procedure, it is widely used in digital communicating field.HDLC using frame as transmission elementary cell,
Main transmission structure is: head flag bit, destination address, control, valid data, Frame Check Sequence FCS,
Tail flag bit.By memory element, (DSP the most hereinbefore mentioned is passed to data by ping-pong transmission
In the RAM of FPGA) through serioparallel exchange, CRC check, slotting " 0 ", data packing (packaging frame head
Postamble) etc. function by data send；System detection frame head postamble flag bit, CRC school when judging to receive data
After testing, data are carried out serioparallel exchange and stores in RAM (then with the communication mode record introduced above
In storage device FLASH).
The RS-485 differential level characteristic of AMS2486 chip that system uses Analog company to produce completes
The connection with peripheral hardware of system design and communication.This chip can reach the transfer rate of 20M in theory, and sets
In respect of isolating device structure and current foldback circuit, it is possible to effectively protect system while being PERCOM peripheral communication
Hardware platform.For meeting the needs of different designs, inside fpga core control chip, it is provided with special baud
Rate depositor, can be by bookbinding or Non-follow control two ways from PC environment, by fpga core
The internal special clock module of control chip controls to send, accept the baud rate of data.
Described A/D chip is the MAX1270AEAI of MAXIM company.Native system needs to enter 5 road voltages
Row acquisition testing, carrys out decision-making system the most working properly, or detection external voltage duty.This function
The A/D chip controlled by fpga core control chip is realized.This MAX1270 chip can gather
8 tunnel analogue signals.Collection voltage is-10V～+10V, designs level adjustment circuit before level inputs,
The level input gathering-13V～+13V can be met.System work clock is 2MHz, single acquisition communication
Being not more than 32 clock cycle, gather required time is 0.5 μ s × 32=16 μ s the most every time.System needs altogether
Sampling 5 road analog signal levels, therefore a sampling period is 16 μ s × 5=80 μ s.
Described GPS communication daughter board is OEMStar.It is a of the up-to-date release of NovAtel company of Canada
The GNSS of high-performance and low-cost receives board, and it uses RHCP polarization mode, and impedance is 50ohms,
Yield value is 26dB, and precision 3dB, noise is at 2.8dB.Operating temperature is-55～+85 degrees Celsius, antenna
Width is 89mm, and height is 15mm.This support GLONASS function of applying for card, hardware size and interface,
Data form can be compatible with SSII and OEMV-1/1G board, supports OEMV series of products the most completely
Operational order.Its characteristic is as follows:
Ephemeris information etc. needed for later stage carrier difference.
(2) present invention proposes the structure side of a kind of High-speed Data Recording System based on FPGA+DSP framework
Method, the method specifically comprises the following steps that
Step one: record system initialization and self-inspection.
After system equipment powers up start, system is automatically fpga core control chip and DSP core control chip
Loading FLASH in program be loaded in corresponding control chip, make acp chip complete initialize.DSP
Kernel control chip end mainly configures each depositor, including bus control register, interrupt register etc.,
To ensure the normal operation of DSP.DSP core control chip correspondence pin is also entered by fpga core control chip
Row configuration, simultaneously using the output clock of DSP core control chip as local global clock, for this chip
Work.
Fpga core control chip controls self-inspection order and judges, observing and controlling assessment equipment is logical after sending self-inspection order
Crossing HDLC interface and be sent to leading portion equipment, leading portion equipment is by sending out to observing and controlling assessment equipment after System self-test
The number of delivering letters, after digital data recording system confirms that System self-test completes, lights self-inspection display lamp.Fpga core control
Chip controls processed bookbinding address code, user selects required address, fpga core control by stirring toggle switch
After coremaking sheet receives address instruction, by HDLC interface, receiver system address is bound, receive
After machine bookbinding, return information is to digital data recording system, and it is right that system is lighted by fpga core control chip
Answer address display lamp.Fpga core control chip controls sky line options function, selects sky by toggle switch
Line address, is configured Systematic selection antenna by fpga core control chip program, lights sky simultaneously
Line options display lamp.Fpga core control chip control instruction handoff functionality, by toggle switch to descending
Line switching command selects, and lights corresponding display lamp idsplay order state after having selected.User uses
When equipment is configured by toggle switch, equipment only reads a dial-up state when powering on, and equipment is normally
Dial-up state will be no longer read, until system work is complete during work.
Step 2: raw data acquisition.
The data gathered are needed to be divided into 3 parts:
1) reference voltage that A/D chip MAX1270 gathers
2) 485 communication interface end transmission original data signal
3) data such as punctual, the ephemeris information of GSP.
Wherein, data and the gps data of AD collection voltage is directly entered fpga core control chip and carries out follow-up
Processing, the data that 4 communication port transfers come are then through HDLC protocol communication chip, are converted to meet
485 formatted datas of protocol requirement, are transferred into fpga core control chip and carry out subsequent treatment.485 connect
The existing data recording equipment of cause for gossip communicates with front-end generating data equipment.Communicate with fpga core control chip
485 signal demands carry out level conversion through DS96F174/175ME chip.Equipment and the communication of answering machine
Controlled by fpga core control chip, send out including transmission self-inspection order, the bookbinding of answering machine state, downlink data
Give, the different order such as reply data reception.Additionally, these orders use HDLC protocol to send and receive,
This protocol conversion process is completed by fpga core control chip.HDLC interface transfer rate is 4Mbps,
Use and receiver phase same rate, to realize being in communication with each other.DS96F174/175ME chip is to lead to for RS485
The low-voltage level conversion chip of letter Protocol Design, can become 485 agreement operation levels by common level conversion.
When fpga core control chip receives and sends 485 signal, first have to carry out electricity through a LMDS Light Coupled Device
Gas performance isolation, LMDS Light Coupled Device selection HCPL-5631, this two optocoupler is by GaAsP luminescence two
The photoelectric coupled device that pole pipe and an integrated high-gain photodetector are constituted.Detection chip output is one
Open-collector schottky clamped transistor, its internal shield provides the common mode transient state of 15 kilovolts/μ s to resist
Degree of disturbing.
The HDLC protocol communication chip realized based on fpga core control chip includes sending and receiving two moulds
Block, first transmitting terminal sends banner word 0x7E, because both sides' available machine time is different, in order to avoid losing data,
Banner word repeated several times, then carries out parallel/serial conversion by parallel data to be sent, and simultaneity factor is the completeest
Become the HDLC protocol such as CRC coding, " 0 " bit insertion to require function, then data after process are pressed synchronous serial
Transmission means sends.Receiving terminal receive synchronous serial data, then by system be automatically performed banner word detection,
Go " 0 " and CRC check, export in 8 parallel-by-bit modes that synchronous serial data is converted into.Whole system is adopted
Use same global clock.
The design has the function of the automatic prover time of system.When being not received by gps signal, in system
DS3231 chip can provide the clock of a benchmark.When there being gps signal, can be to fpga core control
Chip and chip clock are calibrated.For clock control and the calibration of DS3231, it is all at FPGA core
Heart control chip completes, it is achieved control the sequential of ds3231 chip, it is possible to during high-ranking officers, the time is by parallel time
Be converted in serial time write ds3231, and read the ds3231 time, serial data be converted into parallel
Data.
Step 3: DSP core control chip write principal function, control system flow process.
Fixed point, floating-point operation ability in conjunction with DSP core control chip are strong, the features such as code development is simple,
For the actual application indexes requirement of native system, the bookbinding for pre-stored data is compared, to the fortune receiving data
The work such as calculation and Analysis all complete in DSP core control chip.Compare and fpga core control chip,
Being completed this function by DSP core control chip makes the readability of calling program higher, system amendment, upgrading,
The suitability is more extensive.
DSP core control chip major function is to realize communicating with PC, and detection PC end TT&C software is corresponding
Order.
The workflow of measurement and control unit DSP core control chip program is approximately as shown, and its workflow diagram is such as
Shown in Fig. 9:
A. electrifying startup DSP core control chip；
B. initialize DSP core control chip and each depositor of fpga core control chip, search FLASH number
According to tail address, as the initial address of these write data；
C. entering principal function circulation, whether cycle detection has the order issued from PC and is sent out by SCI mouth
The instruction sent；
D. after detecting that PC sends lookup latest position order, then up-to-date write-once FLASH is inquired about
This information is also uploaded to PC by the first address；
E. after detecting that PC sends reading data command, then the number of appropriate address in FLASH chip is read
According to and be uploaded to PC；
F. after detecting that PC sends erasing FLASH order, then all data in erasing FLASH chip,
And data initial address is set to FLASH chip first address, send to PC after completing erasing operation
Wipe complete order；
G. whether inquiry SCI interface has data, if having, then obtains data；
H. the Frame command word classification process sent according to SCI processes Frame, extracts wherein valid data
It is stored in FLASH chip；
I. measurement and control unit power-off, jumps out major cycle, EP (end of program).
First, principal function completes and the initial configuration of external device internal to DSP core control chip,
The device such as including FLASH, GPS and SCI interface, when wherein DSP core control chip just powers on, to FLASH
Storage chip the most once travels through, and inquiry obtains the end of data record, rising as follow-up write data
Beginning address, reads defect block addresses record simultaneously；Gps data is reset, and resets GPS mark, read
Outside dial-up is arranged and respective settings GPS renewal frequency；Initialize SCI interface and then include that arranging data stops
Position and Asynchronous Transfer Mode, reading outside dial-up setting relative set data transmission bauds.
Step 4: fpga core control chip controls FLASH storage chip and realizes data storage.
FLASH storage chip controls to realize in the FLASH module of PFGA kernel control chip end.At this mould
In block, FLASH control function mainly includes reading FLASH function, write FLASH function, erasing FLASH
Function and lookup FLASH bad block function.Corresponding function is completed by calling these functions in principal function.
Wherein read FLASH function and write FLASH function respectively by configure FLASH read-write register it
After by digital independent or write FLASH storage chip in；Wipe FLASH function then to complete to deposit FLASH
Storage chip specify the data of block address to carry out the function wiped；Search FLASH bad block function then by traversal
The bad block mark of FLASH storage chip is searched in FLASH bad block and records its address.
Write FLASH function flow process is as shown in Figure 9；
Read the flow process of FLASH data as shown in Figure 10；
The flow process of erasing FLASH data is as shown in figure 11；
Search the flow process of FLASH bad block as shown in figure 12；
Step 5: PC end TT&C software realizes digital independent analysis.、
Digital data recording system completes data record in the case of being not connected with PC, afterwards by USB interface with
PC connects, and is stored data as the form of Excel form by PC end TT&C software, it is simple to enter data
Row is analyzed.
(3) advantage and effect:
Hardware circuit is simple, small volume, it is simple to be applied to multiple systems.
System can the real-time record data of high speed.
Programming is simple, it is easy to amendment, makes system have the biggest versatility and motility.
The intended function of complete realization, it is achieved simple, controls uncomplicated.
Interface Matching with other external chip.
Systemic-function is complete.
Accompanying drawing explanation
Fig. 1 is system construction drawing.
Fig. 2 is TT&C software structure chart.
Fig. 3 is software principal function flow chart.
Fig. 4 is DSP attachment structure figure.
Fig. 5 is by USB Yu PC Principle of Communication figure.
Fig. 6 is working-flow figure.
Fig. 7 is table tennis transmission communication pattern schematic diagram.
Fig. 8 is DSP core control chip workflow diagram.
Fig. 9 is write FLASH function flow chart.
Figure 10 is the flow chart reading FLASH data.
Figure 11 is the flow chart of erasing FLASH data.
Figure 12 is to look for the flow chart of FLASH bad block.
In figure, symbol description is as follows:
1, fpga core control chip 2, DSP core control chip
3, GPS communication daughter board 4, FPGA store FLASH
5, DSP stores FLASH 6, FLASH storage chip
7, HDLC protocol conversion chip 8, A/D chip
9, usb communication chip 10A, 10B, 10C, 10D, 10E, power supply chip
Detailed description of the invention
The operating mode of a kind of High-speed Data Recording System based on FPGA+DSP framework is summarized as follows:
The present invention is a kind of High-speed Data Recording System based on FPGA+DSP framework, and this system includes:
Fpga core control chip, DSP core control chip, power supply chip, FLASH storage chip, USB
Communication chip, HDLC protocol communication chip, A/D chip, GPS communication daughter board and the end observing and controlling of system PC are soft
Part.System construction drawing is as shown in Figure 1.The population structure of software as in figure 2 it is shown, can be divided into Interface Control and
Display, instruction transmission, data receiver and data process four parts.The work principal function stream of TT&C software
Journey is as shown in Figure 3.Fig. 4 is DSP attachment structure figure.Fig. 5 is by USB Yu PC Principle of Communication figure.
This invention system signal flow trend and hardware configuration are as shown in Figure 1.The main logic of this invention controls
Device is DSP core control chip, two digital circuits of fpga core control chip, both co-ordinations,
Complete the writing function of the information such as initial data.
Position annexation between them and signal trend be: in the entire system, fpga core controls core
Sheet controls the network interface module of PC communication, caching mould when communicating when data are uploaded with DSP core control chip
Block, the module for reading and writing of FLASH storage chip, GPS communication daughter board controls, and bus communication module is i.e.
HDLC protocol communication chip sends, accepts data module.DSP core control chip controls data transmission note
System self-test under record pattern, Analog Data Acquistion Module, and logical with fpga core control chip
Letter module.Power supply chip is connected with each chip, it is provided that the voltage needed for whole system work；
As shown in Figure 6, in the case of being connected with PC, system can realize parameter from PC environment
Bookbinding, the inquiry of data and reading, and save as EXCEL form by PC environment, it is simple to the reading of data
With analysis.PC environment is equipped with self test mode simultaneously, can complete the transmission of data, record under PC environment
Simulation etc. function.When system detection is not connected with PC, it is judged that start data transfer record pattern.
In such a mode, system calls bookbinding data, sends specified format order and data by HDLC protocol,
And judge to take orders data according to agreement, by fpga core control chip and DSP core control chip
Control to store in FLASH.
Fpga core control chip belongs to the core main control part of the present invention, and when responsible data are uploaded, PC leads to
The USB module of letter, cache module when communicating with DSP, the module for reading and writing of FLASH storage chip, GPS
Daughter board controls, and bus communication module i.e. HDLC communication protocol sends, accepts data module.
In system work fpga core control chip need and DSP core control chip to carry out handshake communication complete
Become the order transmission and functional realiey specified.Fpga core control chip indoor design has corresponding address to translate
Code module.When PC reads data and departs from PC transmission data, DSP core control chip passes through address bus
Data command sends to fpga core control chip, and fpga core control chip passes through address decoding will
Data separation packing is transferred to PC.During record data, the data of pre-stored are led to by fpga core control chip
Cross decoding and pass to DSP core control chip, be stored in FLASH.
This system in the course of the work, has between fpga core control chip and DSP core control chip
It is in communication with each other.Read data in view of system and need the regular hour, and DSP core control chip processes
The features such as order is quick not as good as fpga core control chip, in order to avoid, factor data is tediously long, transmission time interval
Shorter and cause data overlap to be obscured situation occur, system in data transmission procedure, fpga core control
Coremaking sheet and DSP core control chip communication use table tennis transmission mode.Fpga core control chip passes through
Decode in the RAM that the data write sent by DSP core control chip is different.RAM can revise and deposit
Storage size, it is also possible to change double table tennises into many ping pong scheme by changing decoded mode, substantially increase data
Transmission quantity and transfer rate.When receiving data, fpga core control chip uses multichannel storage ram, i.e.
By ram compartmentalization, such as Fig. 7.The most both ensure that receiving speed can't lose data, saves again resource.
The present invention proposes the construction method of a kind of High-speed Data Recording System based on FPGA+DSP framework, should
Method specifically comprises the following steps that
Step one: record system initialization and self-inspection.
After system equipment powers up start, system is automatically fpga core control chip and DSP core control chip
Loading FLASH in program be loaded in corresponding control chip, be acp chip complete initialize.DSP
Kernel control chip end mainly configures each depositor, including bus control register, interrupt register etc.,
To ensure the normal operation of DSP.DSP core control chip correspondence pin is also entered by fpga core control chip
Row configuration, simultaneously using the output clock of DSP core control chip as local global clock, for this chip
Work.
Fpga core control chip controls self-inspection order and judges, observing and controlling assessment equipment is logical after sending self-inspection order
Crossing HDLC interface and be sent to leading portion equipment, leading portion equipment is by sending out to observing and controlling assessment equipment after System self-test
The number of delivering letters, after digital data recording system confirms that System self-test completes, lights self-inspection display lamp.Fpga core control
Chip controls processed bookbinding address code, user selects required address, fpga core control by stirring toggle switch
After coremaking sheet receives address instruction, by HDLC interface, receiver system address is bound, receive
After machine bookbinding, return information is to digital data recording system, and it is right that system is lighted by fpga core control chip
Answer address display lamp.Fpga core control chip controls sky line options function, selects sky by toggle switch
Line address, is configured Systematic selection antenna by fpga core control chip program, lights sky simultaneously
Line options display lamp.Fpga core control chip control instruction handoff functionality, by toggle switch to descending
Line switching command selects, and lights corresponding display lamp idsplay order state after having selected.User uses
When equipment is configured by toggle switch, equipment only reads a dial-up state when powering on, and equipment is normally
Dial-up state will be no longer read, until system work is complete during work.
Step 2: raw data acquisition.
The data gathered are needed to be divided into 3 parts:
4) reference voltage that A/D chip MAX1270 gathers
5) 485 communication interface end transmission original data signal
6) data such as punctual, the ephemeris information of GSP.
Wherein, AD gathers the data of voltage and gps data is directly entered after fpga core control chip carries out
Continuous process, the data that 4 communication port transfers come are then through HDLC protocol modular converter, are converted to full
485 formatted datas of the certain protocol requirement of foot, are transferred into fpga core control chip and carry out subsequent treatment.
485 interfaces realize data recording equipment and front-end generating data equipment communication.Enter with fpga core control chip
485 signal demands of row communication carry out level conversion through DS96F174/175ME chip.Equipment and answering machine
Communication by FPGA control, including sending self-inspection order, the bookbinding of answering machine state, downlink data send, should
Answer the different orders such as data receiver.Additionally, these orders use HDLC protocol to send and receive, this association
View transformation process is completed by fpga core control chip.HDLC interface transfer rate is 4Mbps, use with
Receiver phase same rate, to realize being in communication with each other.
DS96F174/175ME chip is the low-voltage level conversion chip for RS485 communication protocol design, can be by
Common level conversion becomes 485 agreement operation levels.
When fpga core control chip receives and sends 485 signal, first have to enter through a LMDS Light Coupled Device
Row electric property is isolated, and LMDS Light Coupled Device selects HCPL-5631, and this two optocoupler is to be sent out by GaAsP
The photoelectric coupled device that optical diode and an integrated high-gain photodetector are constituted.Detection chip output is
One open-collector schottky clamped transistor, its internal shield provides the common mode wink of 15 kilovolts/μ s
State immunity to interference.
The HDLC protocol controller realized based on fpga core control chip includes sending and receiving two modules,
First transmitting terminal sends banner word 0x7E, because both sides' available machine time is different, in order to avoid losing data, and mark
Will word repeated several times, then carries out parallel/serial conversion by parallel data to be sent, and simultaneity factor is automatically performed
The HDLC protocol such as CRC coding, " 0 " bit insertion require function, then data after process are pressed synchronous serial biography
Defeated mode sends.Receiving terminal receive synchronous serial data, then by system be automatically performed banner word detection,
Go " 0 " and CRC check, export in 8 parallel-by-bit modes that synchronous serial data is converted into.Whole system is adopted
Use same global clock.
The design has the function of the automatic prover time of system.When being not received by gps signal, in system
DS3231 chip can provide the clock of a benchmark.When there being gps signal, can be to fpga core control
Chip and chip clock are calibrated.For clock control and the calibration of DS3231, it is all at FPGA core
Heart control chip completes, it is achieved control the sequential of ds3231 chip, it is possible to during high-ranking officers, the time is by parallel time
Be converted in serial time write ds3231, and read the ds3231 time, serial data be converted into parallel
Data.
Step 3: DSP core control chip write principal function, control system flow process.
Fixed point, floating-point operation ability in conjunction with DSP core control chip are strong, the features such as code development is simple,
For the actual application indexes requirement of native system, the bookbinding for pre-stored data is compared, to the fortune receiving data
The work such as calculation and Analysis complete the most in dsp.Compare and fpga core control chip, by DSP core
Control chip completes this function makes the readability of calling program higher, and system amendment, upgrading, the suitability are wider
General.
DSP core control chip major function is to realize communicating with PC, and detection PC end TT&C software is corresponding
Order.
The workflow of measurement and control unit DSP core control chip program is approximately as shown, and its workflow diagram is such as
Shown in Fig. 8:
J. electrifying startup DSP；
K. initialize each depositor of DSP and FPGA, search FLASH data tail address, write number as this
According to initial address；
L. entering principal function circulation, whether cycle detection has the order issued from PC and is sent out by SCI mouth
The instruction sent；
M. after detecting that PC sends lookup latest position order, then up-to-date write-once FLASH is inquired about
This information is also uploaded to PC by the first address；
N. after detecting that PC sends reading data command, then the number of appropriate address in FLASH chip is read
According to and be uploaded to PC；
O. after detecting that PC sends erasing FLASH order, then all data in erasing FLASH chip,
And data initial address is set to FLASH chip first address, send to PC after completing erasing operation
Wipe complete order；
P. whether inquiry SCI interface has data, if having, then obtains data；
Q. the Frame command word classification process sent according to SCI processes Frame, extracts wherein valid data
It is stored in FLASH chip；
R. measurement and control unit power-off, jumps out major cycle, EP (end of program).
First, principal function completes and the initial configuration of external device internal to DSP core control chip,
The device such as including FLASH, GPS and SCI interface, when wherein DSP core control chip just powers on, to FLASH
Chip the most once travels through, and inquiry obtains the end of data record, as the starting point of follow-up write data
Location, reads defect block addresses record simultaneously；Gps data is reset, and resets GPS mark, read outside
Dial-up is arranged and respective settings GPS renewal frequency；Initialize SCI interface then include arranging data stop position and
Asynchronous Transfer Mode, the outside dial-up of reading are arranged and relative set data transmission bauds.
Step 4: fpga core control chip controls FLASH and realizes data storage.
FLASH controls to realize in the FLASH module of PFGA kernel control chip end.In this module,
FLASH control function mainly includes reading FLASH function, write FLASH function, erasing FLASH function
And search FLASH bad block function.Corresponding function is completed by calling these functions in principal function.
Wherein read FLASH function and write FLASH function respectively by configure FLASH read-write register it
After by digital independent or write FLASH in；Wipe FLASH function then to complete FLASH to specify block ground
The data of location carry out the function wiped；Search FLASH bad block function then by traveling through the bad block mark of FLASH
Search in FLASH bad block and record its address.
Write FLASH function flow process is as shown in Figure 9；
Read the flow process of FLASH data as shown in Figure 10；
The flow process of erasing FLASH data is as shown in figure 11；
Search the flow process of FLASH bad block as shown in figure 12.
Step 5: PC end TT&C software realizes digital independent analysis.
Digital data recording system completes data record in the case of being not connected with PC, afterwards by USB interface with
PC connects, and is stored data as the form of Excel form by PC end TT&C software, it is simple to enter data
Row is analyzed.
Claims (1)
1. a construction method for High-speed Data Recording System based on FPGA+DSP framework, this construction method
Enforcement be High-speed Data Recording System based on FPGA+DSP framework, this system includes: PC end observing and controlling
Software, fpga core control chip, DSP core control chip, power supply chip, FLASH storage chip,
Usb communication chip, HDLC protocol communication chip, A/D chip and GPS communication daughter board；Fpga core
Control chip controls the USB module of PC communication when data are uploaded, when communicating with DSP core control chip
Cache module, the module for reading and writing of FLASH storage chip, the control of GPS communication daughter board, and HDLC association
View communication chip sends, accepts data module；DSP core control chip controls under data transfer record pattern
System self-test, Analog Data Acquistion Module, and with the communication module of fpga core control chip；
Power supply chip is connected with each chip, it is provided that the voltage needed for whole system work；
The TT&C software VC of described PC end is designed, and the work that it completes is at hardware system and PC
During communication, demonstrate data at PC end, it is simple to be analyzed；
Described fpga core control chip is XC5VLX50T, the network interface of PC communication when responsible data are uploaded
Module, cache module when communicating with DSP, the module for reading and writing of FLASH storage chip, GPS daughter board controls,
And HDLC communication protocol sends, accepts data module；
Described DSP core control chip is TMS320F2812, is responsible for the system under data transfer record pattern
Self-inspection, Analog Data Acquistion Module and the communication with fpga core control chip；At this data record
In system, the external interface of DSP core control chip have level acquisition interface, gps data coffret,
And with the data of fpga core control chip and address interface；And DSP core control chip and FPGA
Connection between kernel control chip uses EMIF A interface；
Described power supply chip is PTH05000 chip, it is provided that the output voltage of-0.6～10V, this power supply chip
Voltage needed for whole system work is provided；
Described FLASH storage chip is K9F8G08U0M chip, by the electricity enabling, controlling pin
Flat change realizes the read-write operation to FLASH chip, and FLASH storage chip is responsible for the storage of data, logical
Cross fpga core control chip to be controlled, it is simple to carry out testing post analysis；
Described usb communication chip is the EZ-USB FX2 chip CY7C68013 equipment as both connections
Chip；CY7C68013 is USB2.0 agreement, is divided into port, tri-kinds of work sides of GPIF and Slave FIFO
Formula；When system is connected with PC, user sends instruction from PC environmental interface to system, carries out order bookbinding
Or to the lookup of canned data, read, wipe；
Described HDLC protocol communication chip is AMS2486, and the RS-485 differential level characteristic of this chip completes
The connection with peripheral hardware of system design and communication；
Described A/D chip is MAX1270AEAI；Native system needs 5 road voltages are acquired detection, comes
Decision-making system is the most working properly, and this function is come real by the A/D chip that fpga core control chip controls
Existing, this MAX1270 chip can gather 8 tunnel analogue signals；
Described GPS communication daughter board is OEMStar, and it is the GNSS reception board of a high-performance and low-cost,
It uses RHCP polarization mode；
It is characterized in that: the method specifically comprises the following steps that
Step one: record system initialization and self-inspection；
After system equipment powers up start, system is automatically fpga core control chip and DSP core control chip
Loading FLASH in program be loaded in corresponding control chip, make acp chip complete initialize；DSP
Kernel control chip end is to configure each depositor, including bus control register, interrupt register, to protect
The normal operation of card DSP；DSP core control chip correspondence pin is also joined by fpga core control chip
Put, simultaneously using the output clock of DSP core control chip as local global clock, for this chip operation；
Fpga core control chip controls self-inspection order and judges, observing and controlling assessment equipment passes through after sending self-inspection order
HDLC interface is sent to leading portion equipment, and leading portion equipment is by sending to observing and controlling assessment equipment after System self-test
Signal, after digital data recording system confirms that System self-test completes, lights self-inspection display lamp；Fpga core controls core
Sheet controls bookbinding address code, and user selects required address, fpga core control chip by stirring toggle switch
After receiving address instruction, being bound receiver system address by HDLC interface, receiver is bound
After return information light corresponding address to digital data recording system, system by fpga core control chip
Display lamp；Fpga core control chip controls sky line options function, selects antenna address by toggle switch,
By fpga core control chip program, Systematic selection antenna is configured, light a day line options simultaneously and refer to
Show lamp；Fpga core control chip control instruction handoff functionality, by toggle switch to downlink switching command
Select, after having selected, light corresponding display lamp idsplay order state；User uses toggle switch pair
When equipment is configured, equipment only reads a dial-up state when powering on, and equipment will not when normal work
Read dial-up state again, until system work is complete；
Step 2: raw data acquisition；
The data gathered are needed to be divided into 3 parts:
1) reference voltage that A/D chip MAX1270 gathers
2) 485 communication interface end transmission original data signal
3) GSP is punctual, ephemeris information data；
Wherein, data and the gps data of AD collection voltage are directly entered fpga core control chip and carry out subsequent treatment,
The data that 4 communication port transfers come are then through HDLC protocol communication chip, are converted to meet agreement and want
485 formatted datas asked, are transferred into fpga core control chip and carry out subsequent treatment；485 interfaces realize
Data recording equipment communicates with front-end generating data equipment, with fpga core control chip communicate 485
Signal demand carries out level conversion through DS96F174/175ME chip；The communication of equipment and answering machine is by FPGA
Kernel control chip controls, including sending self-inspection order, the bookbinding of answering machine state, downlink data transmission, answering
Answer data receiver；Additionally, these orders use HDLC protocol to send and receive, this protocol conversion process leads to
Cross fpga core control chip to complete；HDLC interface transfer rate is 4Mbps, uses mutually synchronized with receiver
Rate, to realize being in communication with each other；DS96F174/175ME chip is the low-voltage for RS485 communication protocol design
Electrical level transferring chip, becomes 485 agreement operation levels by common level conversion；
When fpga core control chip receives and sends 485 signal, first have to carry out through a LMDS Light Coupled Device
Electric property is isolated, and LMDS Light Coupled Device selects HCPL-5631, and this two optocoupler is by GaAsP luminescence two
The photoelectric coupled device that pole pipe and an integrated high-gain photodetector are constituted, detection chip output is one
Open-collector schottky clamped transistor, its internal shield provides the common mode transient state anti-interference of 15 kilovolts/μ s
Degree；The HDLC protocol communication chip realized based on fpga core control chip includes sending and receiving two moulds
Block, first transmitting terminal sends banner word 0x7E, because both sides' available machine time is different, in order to avoid losing data,
Banner word repeats plural number, then parallel data to be sent is carried out parallel/serial conversion, and simultaneity factor is the completeest
One-tenth CRC encodes, " 0 " bit inserts HDLC protocol and requires function, then data after process are pressed synchronous serial biography
Defeated mode sends；Receiving terminal receive synchronous serial data, then by system be automatically performed banner word detection,
Going " 0 " and CRC check, export in the 8 parallel-by-bit modes that are converted into by synchronous serial data, whole system is adopted
Use same global clock；
System has the function of automatic prover time；When being not received by gps signal, DS3231 in system
Chip can provide the clock of a benchmark, when there being gps signal, and can be to fpga core control chip and core
Sheet clock is calibrated；For clock control and the calibration of DS3231, it is all at fpga core control chip
In complete, it is achieved control ds3231 chip sequential, it is possible to during high-ranking officers, the time is converted to serial by parallel time
In time write ds3231, and read the ds3231 time, serial data be converted into parallel data；
Step 3: DSP core control chip write principal function, control system flow process；
Fixed point, floating-point operation ability in conjunction with DSP core control chip are strong, the simple feature of code development,
For the actual application indexes requirement of native system, the bookbinding for pre-stored data is compared, to the fortune receiving data
Calculation and Analysis work all completes in DSP core control chip；Compare and fpga core control chip, by
DSP core control chip completes this function makes the readability of calling program higher, and system is revised, upgrades, is suitable for
Property is more extensive；
DSP core control chip major function is to realize communicating with PC, and detection PC end TT&C software is ordered accordingly
Order；
The workflow of measurement and control unit DSP core control chip program is approximately as shown:
A. electrifying startup DSP core control chip；
B. initialize DSP core control chip and each depositor of fpga core control chip, search FLASH number
According to tail address, as the initial address of these write data；
C. entering principal function circulation, whether cycle detection has the order issued from PC and is sent out by SCI mouth
The instruction sent；
D. after detecting that PC sends lookup latest position order, then up-to-date write-once FLASH is inquired about
This information is also uploaded to PC by the first address；
E. after detecting that PC sends reading data command, then the number of appropriate address in FLASH chip is read
According to and be uploaded to PC；
F. after detecting that PC sends erasing FLASH order, then all data in erasing FLASH chip,
And data initial address is set to FLASH chip first address, send to PC after completing erasing operation
Wipe complete order；
G. whether inquiry SCI interface has data, if having, then obtains data；
H. the Frame command word classification process sent according to SCI processes Frame, extracts wherein valid data and deposits
It is stored in FLASH chip；
I. measurement and control unit power-off, jumps out major cycle, EP (end of program)；
First, principal function completes and the initial configuration of external device internal to DSP core control chip,
Including FLASH, GPS and SCI interface device, when wherein DSP core control chip just powers on, to FLASH
Storage chip the most once travels through, and inquiry obtains the end of data record, rising as follow-up write data
Beginning address, reads defect block addresses record simultaneously；Gps data is reset, and resets GPS mark, read
Outside dial-up is arranged and respective settings GPS renewal frequency；Initialize SCI interface and then include that arranging data stops
Position and Asynchronous Transfer Mode, reading outside dial-up setting relative set data transmission bauds；
Step 4: fpga core control chip controls FLASH storage chip and realizes data storage；
FLASH storage chip controls to realize in the FLASH module of PFGA kernel control chip end；At this mould
In block, FLASH control function mainly includes reading FLASH function, write FLASH function, erasing FLASH
Function and lookup FLASH bad block function；Corresponding function is completed by calling these functions in principal function；
Wherein read FLASH function and write FLASH function respectively by configure FLASH read-write register it
After by digital independent or write FLASH storage chip in；Wipe FLASH function then to complete to deposit FLASH
Storage chip specify the data of block address to carry out the function wiped；Search FLASH bad block function then by traversal
The bad block mark of FLASH storage chip is searched in FLASH bad block and records its address；
Step 5: PC end TT&C software realizes digital independent analysis；
Digital data recording system completes data record in the case of being not connected with PC, afterwards by USB interface and PC
Connect, stored data as the form of Excel form by PC end TT&C software, it is simple to data are carried out point
Analysis.
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