CN103678728A - High-speed data recording system based on FPGA+DSP framework and establishment method thereof - Google Patents
High-speed data recording system based on FPGA+DSP framework and establishment method thereof Download PDFInfo
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Abstract
The invention discloses a high-speed data recording system based on an FPGA+DSP framework. The high-speed data recording system based on the FPGA+DSP framework comprises PC end measurement and control software, an FPGA core control chip, a DSP core control chip, a power supply chip, an FLASH memory chip, a USB communication chip, an HDLC protocol communication chip, an AD chip and a GPS communication daughter board, wherein the FPGA core control chip controls a USB module for PC communication during data uploading, a cache module during communication between the FPGA core control chip and the DSP core control chip, a reading and writing module of the FLASH memory chip, a control module of the GPS communication daughter board and a data sending and receiving module of the HDLC protocol communication chip, the DSP core control chip controls system self-detection in a data transmission and recording mode, an analog quantity data acquisition module and a communication module of the FPGA core control chip, and the power supply chip is connected with all the chips and is used for providing voltage needed by working of the whole system. An establishment method of the high-speed data recording system based on the FPGA+DSP framework comprises five main steps. The high-speed data recording system based on the FPGA+DSP framework has the advantages that a hardware circuit is simple, the size is small, and data can be recorded in real time at a high speed. The high-speed data recording system based on the FPGA+DSP framework can be applied to various systems conveniently.
Description
Technical field:
The present invention relates to a kind of High-speed Data Recording System and construction method thereof based on FPGA+DSP framework, this design belongs to communication technical field.
Background technology:
In modern communication development, data communication miscellaneous has occupied critical role.In increasing situation, the storage of real time data and analysis are become to user's demand widely.And in various scientific researches and detecting, data are stored with analysis and become especially a kind of important and necessary means.Data storage device (being commonly called as black box) has obtained much application widely in real life.As be applied in aircraft, the various flight parameters of recording black box record are after aircraft has an accident, to search the important evidence of analyzing reason.In addition, vehicle-mounted, carrier-borne black box is also applied gradually.Even if but in civil area, the shortcoming such as data recording equipment also exists such as cost high, applied environment harshness.For these reasons, present patent application provides a kind of digital data recording system of designed, designed.
Summary of the invention:
1, object: the object of the invention is to provide a kind of High-speed Data Recording System and construction method thereof based on FPGA+DSP framework, it can realize the function of real-time recorded data and PC environment reading out data, it is master control device that FPGA and DSP are take in native system design, outfit is with bus communication interface, analog data collection interface and PC data communication interface.Whole system be take various power modules as power supply basis, converts various level supply chips to normally work by 5V power supply.The present invention mainly completes fpga core control chip function by VHDL hardware description language, and DSP kernel control chip function realized in C language, completion system design.
2, technical scheme: object of the present invention is achieved through the following technical solutions.
(1) a kind of High-speed Data Recording System based on FPGA+DSP framework of the present invention, this system comprises: PC end TT&C software, fpga core control chip, DSP kernel control chip, power supply chip, FLASH storage chip, usb communication chip, HDLC protocol communication chip, the AD chip daughter board of communicating by letter with GPS.Position annexation between them and signal trend are: in whole system, the USB module of PC communication when fpga core control chip is controlled data upload, cache module while communicating by letter with DSP kernel control chip, the module for reading and writing of FLASH storage chip, the control of GPS communication daughter board, and bus communication module is that HDLC protocol communication chip sends, accepts data module.System self-test under DSP kernel control chip control data transmission logging mode, Analog Data Acquistion Module, and with the communication module of fpga core control chip.Power supply chip is connected with each chip, provides whole system work required voltage.System construction drawing as shown in Figure 1.
The TT&C software of PC end designs with VC.The work that it mainly completes is when hardware system is communicated by letter with PC, at PC end, demonstrates data, is convenient to analyze.This TT&C software be take interface processing and USB interface and is controlled as main, sends the orders such as bookbinding parameter, uploading data, and the data that obtain are stored as to Excel file by interface to master control borad, shows relevant information simultaneously on interface.The general structure of software as shown in Figure 2, can be divided into interface control and demonstration, instruction transmission, data receiver and four parts of data processing.
The workflow of the TT&C software of PC end roughly as workflow diagram as shown in Figure 3:
A. open software, detect USB device and whether connect;
B. start shooting and send self check order from trend equipment, whether checkout equipment connects normally;
C. can start test pattern, whether checkout equipment function is normal;
D. read and draw the data storing information of FLASH chip on interface;
E. search the up-to-date once data of storage in memory block;
F. control the director data that receiving equipment is uploaded, frame head part key message is shown on interface;
G. the director data receiving is stored in computing machine with the form of Excel;
H. off device, analyzes data.
The input interfaces such as button are controlled for user provides parameter input, instruction in this software interface unit, and possesses functions such as showing store status, minute bookbinding instruction area, FLASH control zone, search the aobvious district in data information area, data read area, memory map and six of Frame header viewing areas part, function is as follows separately:
Binding instructio district comprises that address parameter input frame, address code send button, day line options button etc., complete the control to multiple functions such as the bookbinding of order line answering machine data recording analytical equipment address code, day line options and switchings.
FLASH control zone completes the function of removing all storage data of FLASH.
Search data information area and mainly contain to comprise and search the up-to-date memory location of internal memory and display memory distribution plan button, latest page is initial, latest page stops and initial leader will shows information.
Data read area has two buttons: read and save as Excel.Read start page and read termination page table and show the scope that reads FLASH; Current reading wrapped number and read bag number for showing Load Game.
The aobvious district of memory map is a pie chart viewing area, controlled by the display memory distribution plan in memory management district.Data information area the first row is title, represents frame head, start address and end address.Can show at most front 100 groups of data.
Described fpga core control chip is the XC5VLX50T that Xilinx company produces.XC5VLX50T has 1M system door, 7200 slices, the distributed RAM storage space of maximum available 480Kbits, nearly 7200 user I/O interfaces.The internal clocking speed that is up to 550MHz, more than the message transmission rate of I/O interface can reach 840Mb/s.In addition, this model FPGA has high-performance clock control circuit, and nearly 12 digital dock control modules have the features such as accurate clock phase compensation, high-resolution phase skew.Many performances make XC5VLX50T can meet all demands of system, having that system is further upgraded, in perfect in shape and function, do not have too much waste resource.Fpga core control chip belongs to core main control part of the present invention, the network interface module of PC communication while being responsible for data upload, cache module while communicating by letter with DSP, the module for reading and writing of FLASH storage chip, GPS daughter board is controlled, and bus communication module is that HDLC communication protocol sends, accepts data module.
Described DSP kernel control chip is working-flow main control part, is responsible for the System self-test under data transfer record pattern, Analog Data Acquistion Module, and with the communicating by letter of fpga core control chip.For the technical requirement of native system, DSP kernel control chip adopts the TMS320F2812 of TI company.TMS320F2812 has the static CMOS manufacturing technology of high-performance of 150MHz; High-effect 32BitCPU can realize and breathe out not bus structure, can respond by quick-speed interruption; 4M linear program addressing space and 4M addressing data space; In addition, on chip, there are the Flash of 128Kx16 and the SARAM of 18Kx16,16 12 analog-to-digital conversion modules of channel (ADC).In this digital data recording system, the main external interface of DSP kernel control chip have level acquisition interface, gps data transmission interface and with data and the address interface of fpga core control chip, its outside connection layout is as shown in Figure 4.Wherein DSP kernel control chip and GPS module and level acquisition module are direct-connected, because DSP2812 chip provides a SCI interface, conversion by RS232 level formed and GPS module between interface, by this interface complete with GPS module between communicate by letter; 12 AD collectors on DSP2812 built-in chip type Yi Ge 16 tunnels in addition, the collection voltage range of this AD collector is 0～3V, by add corresponding divider resistance and voltage reversal circuit on hardware, realize the increase of measurement range, can meet the level input of collection-13V～+ 13V.And use EMIF A interface, the storer of this interface support to comprise synchronous dynamic ram (SDRAM), asynchronous device (asynchronous FIFO, ROM etc.), the outside device of sharing storage space etc. being connected between DSP kernel control chip and fpga core control chip.Fpga core control chip and DSP kernel control chip carry out synchronous data communication by EMIF A, need the bus interface of interconnection to comprise data bus XD (32bit), address bus XA(20bit), CE(4bit is selected in space), byte input enables BE(4bit), write enable signal SSWE, output enable SSOE, read enable signal SSRE, synchronously read clock ECLKOUT.For other auxiliary signal, as signals such as bus control interface (HOLD, HOLDA), asynchronous communication interfaces (ARDY), as system reserve, be also connected on fpga core control chip.Although DSP kernel control chip is not directly connected with FLASH on hardware in addition, change by fpga core control chip centre, and just the data line of FLASH and address wire have been carried out to simple decoding processing in fpga core control chip inside, make DSP kernel control chip to process FLASH by exterior I O pin still less, saved the exterior I O resource of DSP kernel control chip preciousness.And fpga core control chip is in the middle of this and have neither part nor lot in more control.DSP kernel control chip johning knot composition as shown in Figure 4.
Described power supply chip is PTH05000 chip, the output voltage of can provide-0.6～10V.Power supply chip provides whole system work required voltage.The present invention uses kind of a voltage: 27V, 5V, 1.0V, 1.9V, 2.5V and 3.3V.Wherein, 1.0V is the kernel supply voltage of fpga core control chip, 1.9V is the core voltage of DSP kernel control chip work, and 3.3V is the I/O supply voltage of fpga core control chip and DSP kernel control chip and the supply voltage of other chip, and 2.5V is peripheral chip operating voltage.Because external system only provides 5V and 27V voltage to register system, so in logging recorder system hardware, need design voltage change-over circuit.
Described FLASH storage chip is K9F8G08U0M chip, and this chip-stored amount, up to 8Gbit, separately has 256Mbit storage space as standby, by changing to enabling, control the level of pin the read-write operation of realizing FLASH chip.FLASH storage chip is the storage area of system, is mainly responsible for the storage of data, by fpga core control chip, controls, and is convenient to test post analysis.
Described usb communication chip is the EZ-USB FX2 chip CY7C68013 that produces of Cypress company as connecting the two device chip.CY7C68013 is USB2.0 agreement, is divided into port, GPIF and tri-kinds of working methods of Slave FIFO.Theoretical at full speed lower signal rate can reach 12Mbps, and at a high speed lower signal rate can reach 480Mbps.When system is connected with PC, user can send instruction to system from PC environmental interface, carries out order bookbinding or searching, read, wiping etc. canned data.The design of fpga core control chip comprises the decoding module of PC instruction and the control module of network interface data transmission.While communicating by letter with PC, principle as shown in Figure 5.For ease of communication, facilitate system synergistic working, USB adopts Slave FIFO mode of operation, and chip is controlled by fpga core control chip.Fpga core control chip is according to the data bus of the empty full scale will of FIFO signal controlling chip, and the read-write in control bus enables etc., can realize the high-speed transfer of data completely.The initialize routine of chip is stored in the middle of the firmware chip 24LC64 of auxiliary work with it.By writing firmware program, can select 68013 mode of operation, and inner FIFO storage size, data transfer direction etc.The CY7C68013 corresponding A PI function library that PC environment provides in conjunction with Cypress company, writes visualization interface platform by VC++, is convenient to transmission and the acceptance of order, data.During work, interface platform sends order to system, and firmware program is selected FIFO port according to command determination.Data are transmitted by FIFO, complete the transmission of order, data and read.
Native system and external equipment communicate--during transmitting and receiving data, use standard HDLC (High-level Data Link Control) communication protocol.HDLC agreement is the high-level data link control procedure that ISO (International Standards Organization) ISO formulates, and is widely used in digital communicating field.HDLC is usingd frame as the elementary cell of transmitting, and main transmission structure is: a zone bit, destination address, control, valid data, Frame Check Sequence FCS, tail zone bit.Data by storage unit (DSP mentioning in above passes in the RAM of FPGA by ping-pong transmission) through string conversion, CRC check, insert the functions such as " 0 ", data packing (packing frame head postamble) data sent; When judgement receives data, after system detection frame head postamble zone bit, CRC check, data are gone here and there and change and store in RAM and (then with the communication mode of introducing above, be recorded in memory device FLASH).
System adopt the AMS2486 chip that Analog company produces the design of RS-485 differential level characteristic completion system with being connected and communicating by letter of peripheral hardware.This chip can reach the transfer rate of 20M in theory, and is designed with isolating device structure and current foldback circuit, protection system hardware platform effectively when can be PERCOM peripheral communication.For meeting the needs of different designs, fpga core control chip inside is provided with special baud rate register, can or manually control two kinds of modes by bookbinding from PC environment, by the clock module that fpga core control chip is inner special, control the baud rate that sends, accepts data.
Described AD chip is the MAX1270AEAI of MAXIM company.Whether native system need to carry out acquisition testing to 5 road voltages, come decision-making system working properly, or detects external voltage duty.The AD chip that this function is controlled by fpga core control chip is realized.This MAX1270 chip can gather 8 tunnel simulating signals.Gathering voltage is-10V～+ 10V, and design level adjustment circuit before level input can meet the level input of collection-13V～+ 13V.System works clock is 2MHz, and single acquisition communication is not more than 32 clock period, and gather required time is 0.5 μ s * 32=16 μ s at every turn.The system 5 road analog signal levels of need to sampling altogether, therefore a sampling period is 16 μ s * 5=80 μ s.
Described GPS communication daughter board is OEMStar.It is the GNSS reception board of a high-performance and low-cost of the up-to-date release of Canadian NovAtel company, and it adopts RHCP polarization mode, and impedance is 50ohms, and yield value is 26dB, precision 3dB, and noise is at 2.8dB.Working temperature is-55～+ 85 degrees Celsius, and a day line width is 89mm, is highly 15mm.This is applied for card and supports GLONASS function, and hardware size and interface, data layout can be compatible with SSII and OEMV-1/1G board, also support the operational order of OEMV series of products completely.Its characteristic is as follows:
A) single-point location: 1.5m RMS
b)DGPS： 0.6m RMS
C) velocity accuracy: 0.05m/s RMS
D) time precision: 20ns RMS
E) positioning time: 60s
F) reacquisition: 1s
G) speed: <515m/s
H) highly: 18288 meters
I) data updating rate: 10Hz
J) port number: 14 passages
K) GPS difference information: this GPS receiver record current time, longitude and latitude, highly,
The ephemeris information that later stage carrier difference is required etc.
(2) construction method of a kind of High-speed Data Recording System based on FPGA+DSP framework of the present invention, the method concrete steps are as follows:
Step 1: register system initialization and self check.
System equipment powers up after start, and system is loaded into the program in the loading FLASH of fpga core control chip and DSP kernel control chip in corresponding control chip automatically, makes acp chip complete initialization.DSP kernel control chip end is mainly each register of configuration, comprises bus control register, interrupt register etc., to guarantee the normal operation of DSP.Fpga core control chip is also configured the corresponding pin of DSP kernel control chip, simultaneously using the output clock of DSP kernel control chip as local global clock, for this chip operation.
Fpga core control chip is controlled self check order and is judged, observing and controlling assessment apparatus sends to leading portion equipment by HDLC interface after sending self check order, leading portion equipment can be to observing and controlling assessment apparatus transmitted signal after passing through System self-test, digital data recording system is lighted self check pilot lamp after confirming that System self-test completes.Fpga core control chip is controlled bookbinding address code, user selects required address by stirring toggle switch, fpga core control chip receives after address instruction, by HDLC interface, receiver system address is bound, after receiver bookbinding, return message is to digital data recording system, and system is lighted corresponding address pilot lamp by fpga core control chip.Fpga core control chip control antenna selection function, selects antenna address by toggle switch, by fpga core control chip program, to system, selects antenna to be configured, and lights a day line options pilot lamp simultaneously.Fpga core control chip steering order handoff functionality, selects downlink switching command by toggle switch, lights corresponding pilot lamp idsplay order state after having selected.When user uses toggle switch to arrange equipment, equipment only reads one time dial-up state when powering on, and equipment will no longer read dial-up state when normal work, until system works is complete.
Step 2: raw data acquisition.
Need the data that gather to be divided into 3 parts:
1) reference voltage that AD chip MAX1270 gathers
2) 485 communication interface end transmission original data signals
3) data such as punctual, the ephemeris information of GSP.
Wherein, the data of AD collection voltage and gps data directly enter fpga core control chip and carry out subsequent treatment, the data that 4 communication port transmit are through HDLC protocol communication chip, be converted to 485 formatted datas that meet protocol requirement, transmission enters fpga core control chip and carries out subsequent treatment.485 Interface realization data recording equipments produce data equipment with front end and communicate by letter.485 signal demands that communicate with fpga core control chip carry out level conversion through DS96F174/175ME chip.Equipment is controlled by fpga core control chip with communicating by letter of answering machine, comprises different orders such as sending self check order, the bookbinding of answering machine state, downlink data transmission, reply data reception.In addition, these orders adopt HDLC agreement sending and receiving, and this protocol conversion process completes by fpga core control chip.HDLC interface transfer rate is 4Mbps, adopts and receiver phase same rate, to realize intercommunication mutually.DS96F174/175ME chip is the low-voltage level conversion chip for RS485 communication protocol design, common level conversion can be become to 485 agreement operation levels.When fpga core control chip receives and sends 485 signal, first to carry out electric property isolation through a Light Coupled Device, Light Coupled Device is selected HCPL-5631, and this two optocoupler is by GaAsP light emitting diode and a photoelectric coupled device that integrated high-gain photodetector forms.Detection chip output is an open-collector schottky clamped transistor, and its internal shield provides the common mode transient state immunity to interference of 15 kilovolts/μ s.
The HDLC protocol communication chip of realizing based on fpga core control chip comprises two modules of sending and receiving, first transmitting terminal sends banner word 0x7E, because both sides' on time is different, for fear of obliterated data, banner word repeated several times, then parallel data to be sent is carried out to parallel/serial conversion, simultaneity factor completes the HDLC protocol requirement functions such as CRC coding, " 0 " bit insertion automatically, then after processing, data send by synchronous serial transmission mode.Receiving end receives synchronous serial data, then by the detection of the automatic complement mark word of system, go " 0 " and CRC check, in 8 bit parallel modes that synchronous serial data is converted to, export.Whole system adopts same global clock.
The design has the function of system automatic calibration time.When not receiving gps signal, in system, DS3231 chip can provide the clock of a benchmark.When having gps signal, in the time of can carrying out school to fpga core control chip and chip clock.Clock control and calibration for DS3231, be all to complete in fpga core control chip, realize control the sequential of ds3231 chip, in the time of can high-ranking officers, the time be converted to the serial time by parallel time and writes in ds3231, and read the ds3231 time, by serial data, be converted into parallel data.
Step 3: DSP kernel control chip writes principal function, control system flow process.
Fixed point, floating-point operation ability in conjunction with DSP kernel control chip are strong, the features such as code development is simple, for the practical application index request of native system, for the bookbinding comparison of pre-deposit data, all complete in DSP kernel control chip receiving the work such as operational analysis of data.Compare and fpga core control chip, complete this function make the readability of calling program stronger by DSP kernel control chip, system modification, upgrading, applicability are more extensive.
DSP kernel control chip major function is to realize communicating by letter with PC, detects PC end TT&C software the corresponding command.
The workflow of measurement and control unit DSP kernel control chip program is roughly as follows, its workflow diagram as shown in Figure 9:
A. electrifying startup DSP kernel control chip;
B. initialization DSP kernel control chip and each register of fpga core control chip, search FLASH data tail address, as the start address of this data writing;
C. enter principal function circulation, whether cycle detection has the order issuing from PC and the instruction being sent by SCI mouth;
D. detect after PC sends and to search latest position order, inquire about the first address of up-to-date write-once FLASH and this information is uploaded to PC;
E., after the order of PC transmission reading out data being detected, read the data of appropriate address in FLASH chip and be uploaded to PC;
F. detect after PC sends and to wipe FLASH order, wipe all data in FLASH chip, and data start address is made as to FLASH chip first address, to PC transmission, wipe complete order after completing erase operation;
Whether have data, if having, obtain data if g. inquiring about SCI interface;
H. process frames of data is processed in the Frame command word classification sending according to SCI, extracts wherein valid data and is stored in FLASH chip;
I. measurement and control unit power-off, jumps out major cycle, EOP (end of program).
First, principal function completes the initial configuration to DSP kernel control chip inside and external device thereof, comprise the devices such as FLASH, GPS and SCI interface, when wherein DSP kernel control chip has just powered on, FLASH storage chip is first once traveled through, inquiry obtains the end of data record, as the start address of follow-up data writing, reads defect block addresses record simultaneously; By gps data zero clearing, and the GPS sign of resetting, read outside dial-up setting respective settings GPS renewal frequency; Initialization SCI interface comprises and data position of rest and Asynchronous Transfer Mode are set, read outside dial-up setting relative set data transmission bauds.
Step 4: fpga core control chip is controlled FLASH storage chip and realized data storage.
FLASH storage chip is controlled in the FLASH module of PFGA kernel control chip end and realizes.In this module, FLASH control function mainly comprises and reads FLASH function, writes FLASH function, wipes FLASH function and search the bad piece function of FLASH.In principal function, by calling these functions, complete corresponding function.
Wherein read FLASH function and write FLASH function respectively by data being read or write in FLASH storage chip after configuration FLASH read-write register; Wipe FLASH function and complete the function that the data of specifying block address in FLASH storage chip are wiped; Searching the bad piece function of FLASH is searched in FLASH bad piece and is recorded its address by the bad block mark of traversal FLASH storage chip.
Write FLASH function flow process as shown in Figure 9;
Read the flow process of FLASH data as shown in figure 10;
Wipe the flow process of FLASH data as shown in figure 11;
Search the flow process of bad piece of FLASH as shown in figure 12;
Step 5: PC end TT&C software realizes data and reads analysis.、
Digital data recording system completes data recording in the situation that not connecting PC, is connected afterwards by USB interface with PC, by PC, holds TT&C software data to be stored as to the form of Excel form, is convenient to data analysis.
(3) advantage and effect:
system can the real-time record data of high speed.
the function of complete realization expection, realizes simply, controls uncomplicated.
interface Matching with other external chip.
Accompanying drawing explanation
Fig. 1 is system construction drawing.
Fig. 2 is TT&C software structural drawing.
Fig. 3 is software principal function process flow diagram.
Fig. 4 is DSP johning knot composition.
Fig. 5 is by USB and PC Principle of Communication figure.
Fig. 6 is working-flow figure.
Fig. 7 is table tennis transport communication pattern diagram.
Fig. 8 is DSP kernel control chip workflow diagram.
Fig. 9 writes FLASH function process flow diagram.
Figure 10 is the process flow diagram that reads FLASH data.
Figure 11 is the process flow diagram of wiping FLASH data.
Figure 12 is the process flow diagram of searching bad piece of FLASH.
In figure, symbol description is as follows:
1, fpga core control chip 2, DSP kernel control chip
3, GPS communication daughter board 4, FPGA store FLASH
5, DSP storage FLASH 6, FLASH storage chip
7, HDLC protocol conversion chip 8, AD chip
9, usb communication chip 10A, 10B, 10C, 10D, 10E, power supply chip
Embodiment
The operating mode of a kind of High-speed Data Recording System based on FPGA+DSP framework of the present invention is summarized as follows:
The present invention is a kind of High-speed Data Recording System based on FPGA+DSP framework, and this system comprises: fpga core control chip, DSP kernel control chip, power supply chip, FLASH storage chip, usb communication chip, HDLC protocol communication chip, AD chip, GPS communication daughter board and system PC end TT&C software.System construction drawing as shown in Figure 1.The general structure of software as shown in Figure 2, can be divided into interface control and demonstration, instruction transmission, data receiver and four parts of data processing.The work principal function flow process of TT&C software as shown in Figure 3.Fig. 4 is DSP johning knot composition.Fig. 5 is by USB and PC Principle of Communication figure.
This invention system signal flow process trend and hardware configuration are as shown in Figure 1.The main logic control device of this invention is DSP kernel control chip, two digital circuits of fpga core control chip, and both co-ordinations, complete the recording of information functions such as raw data.
Position annexation between them and signal trend are: in whole system, the network interface module of PC communication when fpga core control chip is controlled data upload, cache module while communicating by letter with DSP kernel control chip, the module for reading and writing of FLASH storage chip, GPS communication daughter board is controlled, and bus communication module is that HDLC protocol communication chip sends, accepts data module.System self-test under DSP kernel control chip control data transmission logging mode, Analog Data Acquistion Module, and with the communication module of fpga core control chip.Power supply chip is connected with each chip, provides whole system work required voltage;
As shown in Figure 6, in the situation that being connected with PC, system can realize the bookbinding of parameter from PC environment, the inquiry of data with read, and save as EXCEL form by PC environment, be convenient to reading and analyzing of data.Simultaneously PC environment is equipped with the pattern of testing oneself, and can under PC environment, complete the simulation of the functions such as transmission, record of data.When system detection is not connected with PC, judgement log-on data transmission log pattern.Under this pattern, system call bookbinding data, send specified format order and data by HDLC agreement, and according to agreement the judgement data that take orders, by fpga core control chip and the control store of DSP kernel control chip in FLASH.
Fpga core control chip belongs to core main control part of the present invention, the USB module of PC communication while being responsible for data upload, the cache module while communicating by letter with DSP, the module for reading and writing of FLASH storage chip, GPS daughter board is controlled, and bus communication module is that HDLC communication protocol sends, accepts data module.
In system works, fpga core control chip need to carry out command transfer and the function realization that handshake communication completes appointment with DSP kernel control chip.The indoor design of fpga core control chip has corresponding address decoding module.When PC reading out data and disengaging PC send data, DSP kernel control chip sends data command to fpga core control chip by address bus, and fpga core control chip is transferred to PC by address decoding by data separation packing.During record data, fpga core control chip passes to DSP kernel control chip by the data of pre-stored by decoding, is stored in FLASH.
This system in the course of the work, has intercommunication mutually between fpga core control chip and DSP kernel control chip.The system reading out data of considering needs the regular hour, and DSP kernel control chip processing command is not as good as the feature such as fpga core control chip is quick, in order to avoid, factor data is tediously long, transmission time interval causes the situation that data overlap is obscured to occur compared with short, system is in data transmission procedure, and fpga core control chip is communicated by letter with DSP kernel control chip and adopted table tennis transmission mode.The data that fpga core control chip sends DSP kernel control chip by decoding write in different RAM.RAM can revise storage size, also can change two table tennis into many ping pong schemes by changing decoded mode, has greatly improved transmission quantity and the transfer rate of data.While receiving data, fpga core control chip adopts multichannel storage ram, is about to ram compartmentalization, as Fig. 7.So both guaranteed that inbound pacing can't obliterated data, again saving resource.
The construction method of a kind of High-speed Data Recording System based on FPGA+DSP framework of the present invention, the method concrete steps are as follows:
Step 1: register system initialization and self check.
System equipment powers up after start, and system is loaded into the program in the loading FLASH of fpga core control chip and DSP kernel control chip in corresponding control chip automatically, is that acp chip completes initialization.DSP kernel control chip end is mainly each register of configuration, comprises bus control register, interrupt register etc., to guarantee the normal operation of DSP.Fpga core control chip is also configured the corresponding pin of DSP kernel control chip, simultaneously using the output clock of DSP kernel control chip as local global clock, for this chip operation.
Fpga core control chip is controlled self check order and is judged, observing and controlling assessment apparatus sends to leading portion equipment by HDLC interface after sending self check order, leading portion equipment can be to observing and controlling assessment apparatus transmitted signal after passing through System self-test, digital data recording system is lighted self check pilot lamp after confirming that System self-test completes.Fpga core control chip is controlled bookbinding address code, user selects required address by stirring toggle switch, fpga core control chip receives after address instruction, by HDLC interface, receiver system address is bound, after receiver bookbinding, return message is to digital data recording system, and system is lighted corresponding address pilot lamp by fpga core control chip.Fpga core control chip control antenna selection function, selects antenna address by toggle switch, by fpga core control chip program, to system, selects antenna to be configured, and lights a day line options pilot lamp simultaneously.Fpga core control chip steering order handoff functionality, selects downlink switching command by toggle switch, lights corresponding pilot lamp idsplay order state after having selected.When user uses toggle switch to arrange equipment, equipment only reads one time dial-up state when powering on, and equipment will no longer read dial-up state when normal work, until system works is complete.
Step 2: raw data acquisition.
Need the data that gather to be divided into 3 parts:
4) reference voltage that AD chip MAX1270 gathers
5) 485 communication interface end transmission original data signals
6) data such as punctual, the ephemeris information of GSP.
Wherein, the data of AD collection voltage and gps data directly enter fpga core control chip and carry out subsequent treatment, the data that 4 communication port transmit are through HDLC protocol conversion module, be converted to 485 formatted datas that meet certain protocol requirement, transmission enters fpga core control chip and carries out subsequent treatment.485 Interface realization data recording equipments produce data equipment with front end and communicate by letter.485 signal demands that communicate with fpga core control chip carry out level conversion through DS96F174/175ME chip.Equipment is controlled by FPGA with communicating by letter of answering machine, comprises different orders such as sending self check order, the bookbinding of answering machine state, downlink data transmission, reply data reception.In addition, these orders adopt HDLC agreement sending and receiving, and this protocol conversion process completes by fpga core control chip.HDLC interface transfer rate is 4Mbps, adopts and receiver phase same rate, to realize intercommunication mutually.
DS96F174/175ME chip is the low-voltage level conversion chip for RS485 communication protocol design, common level conversion can be become to 485 agreement operation levels.
When fpga core control chip receives and sends 485 signal, first to carry out electric property isolation through a Light Coupled Device, Light Coupled Device is selected HCPL-5631, and this two optocoupler is by GaAsP light emitting diode and a photoelectric coupled device that integrated high-gain photodetector forms.Detection chip output is an open-collector schottky clamped transistor, and its internal shield provides the common mode transient state immunity to interference of 15 kilovolts/μ s.
The HDLC protocol controller of realizing based on fpga core control chip comprises two modules of sending and receiving, first transmitting terminal sends banner word 0x7E, because both sides' on time is different, for fear of obliterated data, banner word repeated several times, then parallel data to be sent is carried out to parallel/serial conversion, simultaneity factor completes the HDLC protocol requirement functions such as CRC coding, " 0 " bit insertion automatically, then after processing, data send by synchronous serial transmission mode.Receiving end receives synchronous serial data, then by the detection of the automatic complement mark word of system, go " 0 " and CRC check, in 8 bit parallel modes that synchronous serial data is converted to, export.Whole system adopts same global clock.
The design has the function of system automatic calibration time.When not receiving gps signal, in system, DS3231 chip can provide the clock of a benchmark.When having gps signal, in the time of can carrying out school to fpga core control chip and chip clock.Clock control and calibration for DS3231, be all to complete in fpga core control chip, realize control the sequential of ds3231 chip, in the time of can high-ranking officers, the time be converted to the serial time by parallel time and writes in ds3231, and read the ds3231 time, by serial data, be converted into parallel data.
Step 3: DSP kernel control chip writes principal function, control system flow process.
The features such as fixed point, floating-point operation ability in conjunction with DSP kernel control chip are strong, and code development is simple, for the practical application index request of native system, for the bookbinding comparison of pre-deposit data, all complete in DSP receiving the work such as operational analysis of data.Compare and fpga core control chip, complete this function make the readability of calling program stronger by DSP kernel control chip, system modification, upgrading, applicability are more extensive.
DSP kernel control chip major function is to realize communicating by letter with PC, detects PC end TT&C software the corresponding command.
The workflow of measurement and control unit DSP kernel control chip program is roughly as follows, its workflow diagram as shown in Figure 8:
J. electrifying startup DSP;
K. each register of initialization DSP and FPGA, searches FLASH data tail address, as the start address of this data writing;
L. enter principal function circulation, whether cycle detection has the order issuing from PC and the instruction being sent by SCI mouth;
M. detect after PC sends and to search latest position order, inquire about the first address of up-to-date write-once FLASH and this information is uploaded to PC;
N., after the order of PC transmission reading out data being detected, read the data of appropriate address in FLASH chip and be uploaded to PC;
O. detect after PC sends and to wipe FLASH order, wipe all data in FLASH chip, and data start address is made as to FLASH chip first address, to PC transmission, wipe complete order after completing erase operation;
Whether have data, if having, obtain data if p. inquiring about SCI interface;
Q. process frames of data is processed in the Frame command word classification sending according to SCI, extracts wherein valid data and is stored in FLASH chip;
R. measurement and control unit power-off, jumps out major cycle, EOP (end of program).
First, principal function completes the initial configuration to DSP kernel control chip inside and external device thereof, comprise the devices such as FLASH, GPS and SCI interface, when wherein DSP kernel control chip has just powered on, FLASH chip is first once traveled through, inquiry obtains the end of data record, as the start address of follow-up data writing, reads defect block addresses record simultaneously; By gps data zero clearing, and the GPS sign of resetting, read outside dial-up setting respective settings GPS renewal frequency; Initialization SCI interface comprises and data position of rest and Asynchronous Transfer Mode are set, read outside dial-up setting relative set data transmission bauds.
Step 4: fpga core control chip is controlled FLASH and realized data storage.
FLASH is controlled in the FLASH module of PFGA kernel control chip end and realizes.In this module, FLASH control function mainly comprises and reads FLASH function, writes FLASH function, wipes FLASH function and search the bad piece function of FLASH.In principal function, by calling these functions, complete corresponding function.
Wherein read FLASH function and write FLASH function respectively by data being read or write in FLASH after configuration FLASH read-write register; Wipe FLASH function and complete the function that the data of specifying block address in FLASH are wiped; Searching the bad piece function of FLASH is searched in FLASH bad piece and is recorded its address by the bad block mark of traversal FLASH.
Write FLASH function flow process as shown in Figure 9;
Read the flow process of FLASH data as shown in figure 10;
Wipe the flow process of FLASH data as shown in figure 11;
Search the flow process of bad piece of FLASH as shown in figure 12.
Step 5: PC end TT&C software realizes data and reads analysis.、
Digital data recording system completes data recording in the situation that not connecting PC, is connected afterwards by USB interface with PC, by PC, holds TT&C software data to be stored as to the form of Excel form, is convenient to data analysis.
Claims (2)
1. the High-speed Data Recording System based on FPGA+DSP framework, is characterized in that: this system comprises: PC end TT&C software, fpga core control chip, DSP kernel control chip, power supply chip, FLASH storage chip, usb communication chip, HDLC protocol communication chip, the AD chip daughter board of communicating by letter with GPS; The USB module of PC communication when fpga core control chip is controlled data upload, cache module while communicating by letter with DSP kernel control chip, the module for reading and writing of FLASH storage chip, the control of GPS communication daughter board, and HDLC protocol communication chip sends, accepts data module; System self-test under DSP kernel control chip control data transmission logging mode, Analog Data Acquistion Module, and with the communication module of fpga core control chip; Power supply chip is connected with each chip, provides whole system work required voltage;
The TT&C software of described PC end designs with VC, and the work that it completes is when hardware system is communicated by letter with PC, at PC end, demonstrates data, is convenient to analyze;
Described fpga core control chip is XC5VLX50T, the network interface module of PC communication while being responsible for data upload, and the cache module while communicating by letter with DSP, the module for reading and writing of FLASH storage chip, GPS daughter board is controlled, and HDLC communication protocol sends, accepts data module;
Described DSP kernel control chip is TMS320F2812, is responsible for the System self-test under data transfer record pattern, Analog Data Acquistion Module and with the communicating by letter of fpga core control chip; In this digital data recording system, the external interface of DSP kernel control chip have level acquisition interface, gps data transmission interface and with data and the address interface of fpga core control chip; And use EMIF A interface being connected between DSP kernel control chip and fpga core control chip;
Described power supply chip is PTH05000 chip, the output voltage of provide-0.6～10V, and this power supply chip provides whole system work required voltage;
Described FLASH storage chip is K9F8G08U0M chip, by changing to enabling, control the level of pin the read-write operation of realizing FLASH chip, FLASH storage chip is responsible for the storage of data, by fpga core control chip, controls, and is convenient to test post analysis;
Described usb communication chip is EZ-USB FX2 chip CY7C68013 as connecting the two device chip; CY7C68013 is USB2.0 agreement, is divided into port, GPIF and tri-kinds of working methods of Slave FIFO; When system is connected with PC, user sends instruction from PC environmental interface to system, carries out order bookbinding or searching, read, wiping canned data;
Described HDLC protocol communication chip is AMS2486, the design of the RS-485 differential level characteristic completion system of this chip with being connected and communicating by letter of peripheral hardware;
Described AD chip is MAX1270AEAI; Whether native system need to carry out acquisition testing to 5 road voltages, come decision-making system working properly, and the AD chip that this function is controlled by fpga core control chip is realized, and this MAX1270 chip can gather 8 tunnel simulating signals;
Described GPS communication daughter board is OEMStar, and it is the GNSS reception board of a high-performance and low-cost, and it adopts RHCP polarization mode.
2. a construction method for the High-speed Data Recording System based on FPGA+DSP framework, is characterized in that: the method concrete steps are as follows:
Step 1: register system initialization and self check;
System equipment powers up after start, and system is loaded into the program in the loading FLASH of fpga core control chip and DSP kernel control chip in corresponding control chip automatically, makes acp chip complete initialization; DSP kernel control chip end is each register of configuration, comprises bus control register, interrupt register, to guarantee the normal operation of DSP; Fpga core control chip is also configured the corresponding pin of DSP kernel control chip, simultaneously using the output clock of DSP kernel control chip as local global clock, for this chip operation;
Fpga core control chip is controlled self check order and is judged, observing and controlling assessment apparatus sends to leading portion equipment by HDLC interface after sending self check order, leading portion equipment can be to observing and controlling assessment apparatus transmitted signal after passing through System self-test, digital data recording system is lighted self check pilot lamp after confirming that System self-test completes; Fpga core control chip is controlled bookbinding address code, user selects required address by stirring toggle switch, fpga core control chip receives after address instruction, by HDLC interface, receiver system address is bound, after receiver bookbinding, return message is to digital data recording system, and system is lighted corresponding address pilot lamp by fpga core control chip; Fpga core control chip control antenna selection function, selects antenna address by toggle switch, by fpga core control chip program, to system, selects antenna to be configured, and lights a day line options pilot lamp simultaneously; Fpga core control chip steering order handoff functionality, selects downlink switching command by toggle switch, lights corresponding pilot lamp idsplay order state after having selected; When user uses toggle switch to arrange equipment, equipment only reads one time dial-up state when powering on, and equipment will no longer read dial-up state when normal work, until system works is complete;
Step 2: raw data acquisition;
Need the data that gather to be divided into 3 parts:
1) reference voltage that AD chip MAX1270 gathers
2) 485 communication interface end transmission original data signals
3) punctual, the ephemeris information data of GSP;
Wherein, the data of AD collection voltage and gps data directly enter fpga core control chip and carry out subsequent treatment, the data that 4 communication port transmit are through HDLC protocol communication chip, be converted to 485 formatted datas that meet protocol requirement, transmission enters fpga core control chip and carries out subsequent treatment; 485 Interface realization data recording equipments produce data equipment with front end and communicate by letter, and 485 signal demands that communicate with fpga core control chip carry out level conversion through DS96F174/175ME chip; Equipment is controlled by fpga core control chip with communicating by letter of answering machine, comprises and sends self check order, the bookbinding of answering machine state, downlink data transmission, reply data reception; In addition, these orders adopt HDLC agreement sending and receiving, and this protocol conversion process completes by fpga core control chip; HDLC interface transfer rate is 4Mbps, adopts and receiver phase same rate, to realize intercommunication mutually; DS96F174/175ME chip is the low-voltage level conversion chip for RS485 communication protocol design, and common level conversion is become to 485 agreement operation levels;
When fpga core control chip receives and sends 485 signal, first to carry out electric property isolation through a Light Coupled Device, Light Coupled Device is selected HCPL-5631, this two optocoupler is by GaAsP light emitting diode and a photoelectric coupled device that integrated high-gain photodetector forms, detection chip output is an open-collector schottky clamped transistor, and its internal shield provides the common mode transient state immunity to interference of 15 kilovolts/μ s; The HDLC protocol communication chip of realizing based on fpga core control chip comprises two modules of sending and receiving, first transmitting terminal sends banner word 0x7E, because both sides' on time is different, for fear of obliterated data, banner word repeats plural number, then parallel data to be sent is carried out to parallel/serial conversion, simultaneity factor completes CRC coding automatically, " 0 " bit inserts HDLC protocol requirement function, then after processing, data send by synchronous serial transmission mode; Receiving end receives synchronous serial data, then by the detection of the automatic complement mark word of system, go " 0 " and CRC check, in 8 bit parallel modes that synchronous serial data is converted to, export, whole system adopts same global clock;
System has the function of automatic calibration time; When not receiving gps signal, in system, DS3231 chip can provide the clock of a benchmark, when having gps signal, in the time of can carrying out school to fpga core control chip and chip clock; Clock control and calibration for DS3231, be all to complete in fpga core control chip, realize control the sequential of ds3231 chip, in the time of can high-ranking officers, the time be converted to the serial time by parallel time and writes in ds3231, and read the ds3231 time, by serial data, be converted into parallel data;
Step 3: DSP kernel control chip writes principal function, control system flow process;
Fixed point, floating-point operation ability in conjunction with DSP kernel control chip are strong, the simple feature of code development, for the practical application index request of native system, for the bookbinding comparison of pre-deposit data, all complete in DSP kernel control chip receiving the operational analysis work of data; Compare and fpga core control chip, complete this function make the readability of calling program stronger by DSP kernel control chip, system modification, upgrading, applicability are more extensive;
DSP kernel control chip major function is to realize communicating by letter with PC, detects PC end TT&C software the corresponding command;
The workflow of measurement and control unit DSP kernel control chip program is roughly as follows:
A. electrifying startup DSP kernel control chip;
B. initialization DSP kernel control chip and each register of fpga core control chip, search FLASH data tail address, as the start address of this data writing;
C. enter principal function circulation, whether cycle detection has the order issuing from PC and the instruction being sent by SCI mouth;
D. detect after PC sends and to search latest position order, inquire about the first address of up-to-date write-once FLASH and this information is uploaded to PC;
E., after the order of PC transmission reading out data being detected, read the data of appropriate address in FLASH chip and be uploaded to PC;
F. detect after PC sends and to wipe FLASH order, wipe all data in FLASH chip, and data start address is made as to FLASH chip first address, to PC transmission, wipe complete order after completing erase operation;
Whether have data, if having, obtain data if g. inquiring about SCI interface;
H. process frames of data is processed in the Frame command word classification sending according to SCI, extracts wherein valid data and is stored in FLASH chip;
I. measurement and control unit power-off, jumps out major cycle, EOP (end of program);
First, principal function completes the initial configuration to DSP kernel control chip inside and external device thereof, comprise FLASH, GPS and SCI interface device, when wherein DSP kernel control chip has just powered on, FLASH storage chip is first once traveled through, inquiry obtains the end of data record, as the start address of follow-up data writing, reads defect block addresses record simultaneously; By gps data zero clearing, and the GPS sign of resetting, read outside dial-up setting respective settings GPS renewal frequency; Initialization SCI interface comprises and data position of rest and Asynchronous Transfer Mode are set, read outside dial-up setting relative set data transmission bauds;
Step 4: fpga core control chip is controlled FLASH storage chip and realized data storage;
FLASH storage chip is controlled in the FLASH module of PFGA kernel control chip end and realizes; In this module, FLASH control function mainly comprises and reads FLASH function, writes FLASH function, wipes FLASH function and search the bad piece function of FLASH; In principal function, by calling these functions, complete corresponding function;
Wherein read FLASH function and write FLASH function respectively by data being read or write in FLASH storage chip after configuration FLASH read-write register; Wipe FLASH function and complete the function that the data of specifying block address in FLASH storage chip are wiped; Searching the bad piece function of FLASH is searched in FLASH bad piece and is recorded its address by the bad block mark of traversal FLASH storage chip;
Step 5: PC end TT&C software realizes data and reads analysis;
Digital data recording system completes data recording in the situation that not connecting PC, is connected afterwards by USB interface with PC, by PC, holds TT&C software data to be stored as to the form of Excel form, is convenient to data analysis.
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