CN103648378B - 用于使用竖直互连的混合堆叠图像传感器的子列并行数字转换器的系统和方法 - Google Patents

用于使用竖直互连的混合堆叠图像传感器的子列并行数字转换器的系统和方法 Download PDF

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CN103648378B
CN103648378B CN201280033746.1A CN201280033746A CN103648378B CN 103648378 B CN103648378 B CN 103648378B CN 201280033746 A CN201280033746 A CN 201280033746A CN 103648378 B CN103648378 B CN 103648378B
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pixel
row
circuit
substrate
interconnection
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CN103648378A (zh
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洛朗·布朗卡尔
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    • H01L31/0264—Inorganic materials
    • H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/555—Constructional details for picking-up images in sites, inaccessible due to their dimensions or hazardous conditions, e.g. endoscopes or borescopes

Abstract

从像素阵列内读取用于像素子列的混合成像传感器和方法的实施方式。混合成像传感器和方法对像素阵列区域进行优化并且使用在基板之间具有最小竖直互连的混合图形传感器堆积方案。

Description

用于使用竖直互连的混合堆叠图像传感器的子列并行数字转 换器的系统和方法
技术领域
本公开通常涉及电磁感测和传感器，并且还涉及低能量电磁输入的条件以及低能量电磁吞吐量的情况。本公开更具体地但非必要完全涉及优化像素阵列区域，以及对在基板之间具有最小竖直互连的混合图像传感器使用堆叠方案，以及也包括最小化像素阵列尺寸/裸片尺寸（区域最优化）的相关系统、方法和特征。
背景技术
大体上，利用和包括成像/摄像技术的使用的电子装置的数量已经普及。例如，智能电话、平板电脑、或其他手持计算装置都包括和利用成像/摄像技术。成像/摄像技术的使用不限于消费者电子产业。各种其他使用领域也利用成像/摄像技术，包括各种工业应用、医学医用、家庭和商业安全/监督应用以及更多。事实上，成像/摄像技术在邻近的所有工业中均被利用。
由于成像传感器非常普及，市场中对于越来越小的高清晰度的成像传感器的需求显著地增加。本公开的装置、系统和方法可以用于考虑尺寸和形状因素的任何成像应用中。本公开可以利用多种不同类型的成像传感器，例如，电荷耦合装置（CCD）或者互补金属氧化物半导体（CMOS）、或者目前已知的或可以在将来变得已知的任何其它图像传感器。
CMOS图像传感器典型地将整个像素阵列和有关的电路（例如，模数转换器和/或放大器）安装在单个芯片上。因为芯片自身的尺寸的物理约束和常规CMOS图像传感器中涉及的相关电路所占用的物理空间，所以像素阵列在芯片上可能占用的面积经常是有限的。因此，即使在还包括相关电路的基板上将像素阵列最大化，由于与用于信号处理和其他功能的有关电路的物理区域和空间的总量占用了芯片，那么像素阵列的面积在物理上是受到限制的。
进一步，CMOS图像传感器可用于的应用或使用领域经常要求CMOS图像传感器被限制为特定尺寸，该特定尺寸还限制在像素阵列可能占用的物理区域。由于 CMOS图像传感器的设计和制造中必须解决的多个考虑，CMOS图像传感器的尺寸限制经常要求图像质量和其它重要功能（例如信号处理）之间的折中。因此，例如，由于有关电路可能占据的区域被减少，所以增加像素阵列区域可能伴随其他区域中的折中（例如，A/D转换或其他信号处理功能）。
本公开通过使在第一基板上的像素阵列以及后续基板上的堆叠的相的电路最优化及最大化，在没有牺牲数据处理质量的情况下，使像素阵列最优化及最大化。本公开利用背面照明和其他领域中的进步来使基板上的像素阵列的区域最优化。堆叠方案和结构允许更高功能的、大型电路能够被利用而同时保持小的芯片尺寸。
本公开的特征和优势将在如下的描述中陈述，并且部分地从描述中变得显而易见，或者可在无需过度的试验的情况下通过本公开的实践了解到。可以通过在所附权利要求中具体地指出的仪器和组合来实现并且获得本公开的特征和优势。
附图说明
通过考虑结合附图给出的后续详细描述，本公开的特征和优势将变得显而易见，其中：
图1示出根据本公开的教导和原则的、在多个基板上建立的成像传感器的实施方式，并且还示出支持电路的特定设置的实施方式；
图2示出根据本公开的教导和原理的像素阵列的实施例，其中，在像素阵列内相对于像素隔开互连；
图3示出根据本公开的教导和原理的像素阵列的实施例，其中，在像素阵列内相对于列隔开互连；
图4示出根据本公开的教导和原理的像素阵列的实施例，其中，在像素阵列内相对于区域隔开互连；
图5示出根据本公开的教导和原则在多个基板上建立的成像传感器的实施方式的透视图，其中形成像素阵列的多个像素列位于第一基板上并且多个电路列位于第二基板上，并且显示一个像素列与它的相关的或对应的电路列之间经由互连的电连接和通信，其中，互连可以与像素阵列内的所限定的像素区域间隔开；
图6-10示出根据本公开的教导和原则在多个基板上建立的成像传感器的不同实施方式的俯视图，其中形成像素阵列的多个像素列位于第一基板上并且多个电路列位于第二基板上，并且显示一个像素列与它的相关的或对应的电路列之间经由互 连的电连接和通信，其中，互连可以与像素阵列内的所限定的像素区域间隔开；
图11示出在多个基板上建立的成像传感器的实施例的俯视图，其中，形成像素阵列的多个像素列和子列位于第一基板上并且多个电路列位于第二基板上，并且显示一个像素列和与该像素列相关的或对应的电路列之间的电连接和通信；
图12示出根据本公开的教导和原理的用于一起形成位于第一基板上的像素阵列和位于第二基板上的多个电路列的多个列和子列的实施例的透视图，并且显示一个像素子列和与该像素子列相关的或对应的电路列之间的电连接和通信。
图12a-图12c分别示出已经分成两个单独的像素子列的单个像素列的透视图、正视图和侧视图，其中，每个像素子列附接到不同的像素列读取总线，并且示出从图12中取出的两个电路列，示出两个像素子列和两个电路列之间的电连接；
图13示出根据本公开的教导和原理的用于一起形成位于第一基板上的像素阵的和专用于位于第二基板上的一个或多个像素子列的多个电路列的多个列和子列的实施例的透视图，并且显示一个像素子列和与该像素子列相关的或对应的电路列之间的电连接和通信；
图13a示出已经分成两个单独的像素子列的单个像素列的透视图，其中，两个像素子列都附接到不同的像素列读取总线，并且示出读取总线到从图13中取出的电路列之间的电连接；
图14示出根据本公开的教导和原理的用于一起形成位于第一基板上的像素阵列和位于第二基板上的多个电路列的多个列和子列的实施例的透视图，并且示出每个像素子列和与该像素子列相关的或对应的电路列之间的电连接和通信；
图14a-图14c分别示出已经分成两个单独的像素子列的单个像素列的透视图、正视图和侧视图，其中，每个像素子列附加到不同的像素列读取总线，并且示出从图14中取出的两个电路列，示出两个像素子列和两个电路列之间的电连接；并且
图15-图18示出根据本公开的教导和原理的用于一起形成位于第一基板上的像素阵列和位于第二基板上的多个电路列的多个列和子列的多个实施例的透视图，并且示出每个像素子列和与该像素子列相关的或对应的电路列之间的电连接和通信。
具体实施方式
出于促进理解根据本公开的原理的目的，现在参考附图中所示出的实施例，并且使用特定语言来描述所述实施例。然而，应当理解的是，这并不用于由此限制本 公开的范围。对如本文中所描述的发明特征的任何变换和进一步修改，以及对本文所示出的本公开的原理的任何额外应用（通常被相关领域的并且拥有本公开的技术人员想到）都将被认为是在所要求的本公开的范围之内。
在公开并且描述通过使用纵向互连来在列或子列混合图像传感器中错开ADC或列电路凸块的装置、系统、方法和过程之前，应当理解的是，本公开不限于本文所公开的特定结构、构造、处理步骤和材料，因为这些结构、构造、处理步骤和材料可以稍有变化。还应当理解的是，本文中采用的术语仅被用来描述特定的实施例而不旨在限制，这是因为本公开的范围将仅由所附权利要求及其等同体来限制。
必须注意的是，如在该说明书和所附权利要求中所使用的那样，除非上下文中清楚地做出相反指示之外，单数形式的"一"、"一个"、和"该"也包括复数指示物。
当描述和要求本公开的主题时，将根据下面所作的限定使用以下术语。
如在本文中所使用的那样，术语"包括"、"包含"、"含有"、"具有……的特征"以及其语法等同体是不排除额外的、未叙述的元件或方法步骤的包含型的或开放型的术语。
如在本文中所使用的那样，短语"由……组成"以及其语法等同体排除在权利要求书中没有指定的任何元件或步骤。
如在本文中所使用的那样，短语"主要由……组成"以及其语法等同体将权利要求书的范围限制为指定的物质或步骤以及那些不会实质上影响所要求的公开的基础和新颖性特点的物质或步骤。
本文中所使用的术语"近侧的"应当广泛地指代最接近原点的部分的概念。
本文中所使用的术语"远侧的"应当通常指代近侧的相反，并且因此取决于上下文而指代离原点更远的部分或者最远的部分的概念。
数字成像，无论是静止的还是电影的，对于用于记录图像数据的装置来说都受到许多约束。如本文所讨论的，成像传感器可以包括设置在至少一个基板上的像素阵列和支持电路。装置通常取决于应用而具有在成像传感器的形状因素上的实用的和最佳的约束。通常，对于设备来说，像素阵列不是唯一的考虑因素，而且也需要容纳支持电路。支持电路可以是但不必限于模数转换器、电力电路、电力采集器、放大器电路、专用信号处理器和滤波器、用于数据传输的串行器等。除了这些电路之外，还可以需要物理性能元件，例如滤光器和镜头。每个像素必须从像素阵列读取并且具有由支持电路处理的数据。随着阵列中的像素的数量的增加，必须处理更 多的数据。关于电影数据，传感器必须转出它的数据并且随时准备在短期内再次操作。
如上所述，虽然尺寸是一个问题，但是，在整个行业中不管对于什么具体应用，像素计数数量都持续上升，且通常遮蔽了用于在已经记录图像之后实际观看图像的媒体（例如计算机显示器或电视机）。然而，应当理解的是，所有的像素被创建得一模一样。在上述的实例中，观察仪器配置可以用于有限的光应用中。
随着在给定的空间中像素计数持续上升，像素间距下降，由此对于互连电接触需要更大精度。因此，因为针对增加的像素间距对数据处理要求更大精度的需要，所以图像传感器生产的成本可能增加。现有技术可以用于实现具有增加的能力的图像传感器，但是由于在制造期间产量下降而增加成本。
上述问题描述了关于行业内几个需求的现有技术。需要这样一种图像传感器，其中，该图像传感器具有通过像素计数的足够分辨率、纵向架构和形状因素、以及尽可能大的像素尺寸，所有的这些同时约束在有限的空间中。本公开考虑并且将讨论这样一种实施例和设计方法，其中，该实施例和设计方法通过优化基板/芯片上的像素阵列的尺寸、并且以大体纵向配置方式将支持电路远距离地放置在一个或多个支持基板/芯片上，来解决这些问题以及潜在的其他问题。
使用片上模数转换器（ADC）、片上模数算法、片上复杂时序和片上复杂模拟功能的高性能图像传感器提供了高质量图像是由于下面理由（下面的列表不是完整的列表，而是仅仅为了示例性目的给出）：
由于长的片外模拟数据线而没有拾音器噪音（如果没有片上ADC，则模拟信号需要能够被片外发送）；
因为在数据路径中早期实施数字转换而时间噪音较低（没有额外放大器、缓冲器增加额外噪音）；
使用复杂的片上时序发生器的局部时序最优化。由于垫片计数限制，可以使用外部系统来仅执行简单的时序；
由IO生成的较低噪音。片上系统允许减少的垫片计数；并且
可以实现较快的操作（更多的串行片上操作，减少的寄生电容和电阻）。随着越来越大的阵列，读取和处理其中创建的数据的需要是非常重要的。
本公开还设想一种图像传感器，该图像传感器可以另外地与其像素阵列和支持电路一起被制造在单独的、单片基板/芯片上并且将像素阵列与所有或大部分支持电 路分离。本公开可以使用至少两个基板/芯片，将使用三维堆叠技术来将该至少两个基板/芯片堆叠在一起。可以使用图像CMOS工艺来处理两个基板/芯片中的第一基板/芯片。第一基板/芯片可以唯一地包括像素阵列或者包括由限制电路包围的像素阵列。可以使用任何工艺进行处理第二或后续基板/芯片，并且不必是来自图像CMOS工艺。第二基板/芯片可以是但不限于高密度数字处理以在基板/芯片上的很有限的空间或区域中集成各种及许多功能，或者可以是但不限于混合模式或模拟处理以集成例如精确的模拟功能，或者可以是但不限于RF处理以实现无线能力，或者可以是但不限于MEMS（微型机电系统）以集成MEMS装置。图像CMOS基板/芯片可以使用任何三维技术来与第二或后续基板/芯片进行堆叠。第二基板/芯片可以支持大多数或大部分电路，否则该电路将作为外围电路经被实现在第一图像CMOS芯片中（假设被实现在单片基板/芯片上）并且因此增加了整个系统区域，同时保持像素阵列尺寸恒定并尽可能最大限度地被优化。可以通过互连（该互连可以为焊线、凸块和/或TSV（硅通孔））来实行两个基板/芯片之间的电连接。
现在参照图1，示出使用背面照明在多个基板上建立的具有图像传感器像素阵列和支持电路的图像传感器实施例。如图所示，像素阵列450可以设置在第一基板452上。该第一基板452可以由硅树脂或者另一种材料制成以控制光传输特性。焊锡球、凸块或过孔421可以用于将一个基板电连接到另一个基板。堆叠的图像传感器的实施例可以包括第一基板452上的像素阵列450。像素阵列450可以覆盖第一基板452的第一表面451的至少40%。在背面照明的配置中，像素阵列可以被设置在所述第一基板的背面上。此外，在背面照明结构中，基板452可以是薄的以用于控制光传输通过该基板。在利用背面照明的实施例中，第一基板可以主要由硅材料制成，或者第一基板可以主要由“高阻抗”半导体材料（例如，碲化镉）制成，或者第一基板可以主要由III-V半导体材料（例如，砷化镓）制成。
在一个实施例中，像素阵列450可以覆盖第一基板452的第一表面451的大部分。在该实施例中，像素阵列450可以处于或者位于所述第一表面451的任何部分上。第一表面451上的剩余空间可以用于如果需要的次级电路的放置。可能出现次级电路的大小可能被设置为使得像素阵列的中心放置不可行的情况。
在使用期间，由像素阵列上的个体像素创建的数据必须由支持电路来处理，因而每个像素必须电连接至支持电路。能够同时理想地读取每个像素，从而创建全局快门。现参考图2，应当理解的是，从作为全局快门的成像装置读取数据的能力要 求每个像素1726一个互连1724，这由于制作公差期间的凸块间距而难以在实践中实现。图3示出在多个列如1728中形成像素1726的情况。使用像素阵列形式的像素列（1728）格式，通过使用卷帘式快门能够实现非常高的帧速率。应当理解的是，卷帘快门基本上同时在同一时间读取整行像素，并且之后从像素列的顶部至像素列的底部来读取或移动。换句话说，随着从多个像素列读取数据，可以读取第一行像素，后续跟着下一邻近行的像素，并且在像素列的顶部开始读取，然后每次逐个像素的向下滚动，并且以预定的和计算的模式在整个像素阵列上移动。在卷帘快门的情况中，每个像素列1728只需要存在一条读取总线1730，而每个电路列一条读取总线1740。由于分别在第一基板1752和第二基板1754上的读取总线1730和读取总线1740的重叠，每条像素列总线1730仅要求一个互连/块1724来将像素读取总线1730连接至电路读取总线1740，而不是如全局快门所要求的每个像素1726一个互连/块1724。
图2示出使用每个像素1726一个块1724的块配置或方案，近似于全局快门操作。在这个配置中，块间距等于或基本上等于在X和Y两轴线或方向中的像素间距。图3示出使用每像素列1728一个互连块的块1724的配置和方案。这个配置可以用在卷帘快门操作中。这个块间距配置或方案和仅仅竖直方向中的图2的块间距相比更宽松。然而，应当注意在这种配置中，块间距仍然要求为至少在一个方向或一个维度上和像素间距相同。图3示出多个列1728，其中每列由多个像素1726组成。每个像素列在Y方向（y轴）上延伸一段距离并且如所示的那样，可以在宽度上为一个像素。通过在每个列1728的一端的单个连接点可以读取每个像素列。尽管这种配置简化了芯片结构，但是必须仍然维持严格的公差，这是因为像素间的距离横向地（水平地）继续限制块（互连）间距，由于互连必须不能与邻居互连接触并且被相应地设置尺寸。
图4示出比图2或图3中所示的块配置甚至更宽松的块配置。在这个图中，块间距是宽松的（例如与图2和图3相比，块之间的距离增加）并且一半互连/块1724能够用于在像素阵列1710的每一侧处理数据。通过增加或引入关于列读取总线而交替并且在列读取总线的相反端处的第二互连集合1724的来实现（例如互连1724用于连接读取总线1730、1740并且可以位于像素阵列710的一侧上的每隔一条列读取总线处，并且可以在像素阵列710的另一侧上做出相反的配置）。如图4中能够看出的，第二互连集合1724b可以与第一互连集合1724a的结合使用，并且可以 用于允许在像素阵列的每一侧处理或读取一半的数据。与在至少一个维度中的像素间距相比，这种配置可以允许将近两倍的块间距尺寸（互连间距），这会极大的减少生产图像传感器1700的成本。在一个实施方式中，每条读取总线可以采用每个像素列1728多于一个的互连或块1724，使得可以从像素列1728的两端中的一端读取数据。
图5-图10示出具有位于基板/芯片上的错开的互连或凸块1824的像素阵列1810的实施例和配置。如上所示的，因为每个像素列1828有一个读取总线并且每个电路列有一个读取总线，并且因为读取总线1830和1840从列的顶部延伸到列的底部，互连/凸块1824可以位于在列之内沿着总线的叠加路径的任何地方。为了放宽凸块间距，可以从列到列通过在下一列中（在Y方向）或向上地或向下地移动下一列凸块1824来增加凸块距离。
例如，应当明白的是，像素间距可以为大约5μm并且像素列可以为任意长度，例如在大约2μm到大约15μm之间的长度。应当注意的是，凸块间距取决于像素间距，从而像素间距将决定理想的凸块间距。例如，假设期望的凸块间距大约100μm，然后可以通过在第一列的顶部开始并且将下一列互连或凸块向下移动100μm，完成放置第一互连或凸块1824。类似地放置所有其他凸块直到线路的第20列中的互连或凸块将位于像素列的底部为止。在此时，第21列中的互连或凸块1824可以再次位于像素列1828的顶部。然后可以重复该相同模式直到像素阵列1810的末端为止。可以由20列×5μm=100μm水平地分离互连或凸块1824。在该实例中，虽然像素间距为大约5μm，但是随后将由超过100μm分离所有的凸块。随后可以为了生产量的目的在像素列中引入冗余度。例如，可以将所有列中的凸块翻倍（即，两个读取总线由2个互连或凸块附接）。该技术将极大地增加堆叠的生产量并且降低整个工艺的成本。
如图5所示，可以经由第一互连1824a电气地接入像素1826的第一列1828。在一个实施例中，可以通过第二互连1824b电气地接入第二像素列1830，其中，该第二互连1824b在制造期间被放置成相对于所述第一互连1824a的错开的配置。如图所示，第二互连1824b的位置和定位可以在X和Y维度或方向都远离第一互连1824b（并且远离任何其他互连1824）的位置至少两个像素宽度。可以随后将第三互连1824c以类似的方式放置在第三像素列中，针对像素阵列1810上的N个数量的互连1824以此类推。该配置提供是像素间距的至少三倍的互连间距。应当明白 的是，在标准条件下，互连间距中的增加可以大于像素间距的三倍。然而，应当明白的是，互连间距中的增加可以是上文所示的像素间距的至少三倍。
同样地，可以用基于区域的间隔而不是基于逐列的连接来实现较大的互连增加（见图，该图示出像素列长宽比6/1和电路列长宽比6/1和3/2，和像素列长宽比8/1和电路列长宽比2/4）。这可以用附加更多总线结构或直接读取到后续基板的使用来实现。在任何一个配置中，互连间距可以因此被描述为如下：
Interconnect _ Pitch = ( N * PixelPitch x ) 2 + ( M * PixelPitch y ) 2
其中，N是在X方向中两个邻近的互连之间的像素的数量，并且M是在Y方向中两个邻近的互连之间的像素的数量。应当明白的是，多个互连中的每个互连可以是这样一种凸块，其中，该凸块的凸块到凸块的距离可以大于两个像素宽度或者大于四个像素宽度或者大于八个像素宽度。
在许多应用中，X方向中的N×像素间距将等于Y方向中的M×像素间距。如图6-10所示，通过额外的迭代来外推的上述过程，可以容纳或者设计较大的像素阵列1810。图6示出重叠的硅基板堆叠。在该附图中，包括像素阵列的第一基板1852被示出为覆盖在包括支持电路的支持基板1854的顶部上。为了简单和讨论起见，以虚线形式描述并且标记针对第一像素列1881的可用于放置支持电路的区域的轮廓。应当明白的是，电路列的实际区域不由虚线表示，而是可以大于、小于或等于像素列的区域。如上所讨论的，支持电路区域直接相互关联与支持电路区域对应的像素列区域。每个像素列可以为一个像素宽与六十四个像素长，并且可以具有从像素列的顶部延伸到底部的一个读取总线。在图6中，如图中的加粗的纵向线示出的可用于支持电路放置的区域可以等于一个像素单元宽乘以六十四个像素单元长。因此，图6中的基板之间的互连1824必须落入六十四个像素单元区域之内的某个地方，以便读取那个列，这是因为沿着六十四个像素的路径重叠像素列读取总线和电路列读取总线，从而可以沿着那些六十四个像素的任何地方放置互连1824以连接读取总线。
此外，因为互连可以仅发生在像素列读取总线和支持电路读取总线重叠的地方，所以为了读取对应的像素列，互连范围是1个像素宽和64个像素长（针对该实例），这是像素列和要连接的支持电路之间的交点。
应当注意的是，图6中的支持电路区域的示例性长宽比示出为1/64。在那个区域之内存在用于定位或者放置互连1824的多个选项，并且随后可以由设计者选择 最终的位置从而允许从互连到互连之间的期望间隔。例如，如图6-图10中最佳示出的，应当理解的是，在互连或凸块1824被错开的配置的实施例中，每个像素组1826可以有一个互连或凸块1824。
此外，应当注意的是，可以取决于期望的应用来利用各种读取总线架构。如上文所讨论的，可以使用较大的专用支持电路来处理通过每个互连1824所读取的数据。错开每个互连/凸块1824的位置还可以为支持电路提供相对于像素阵列1810之内每个区域或像素组的甚至更大的空间。
还应当注意的是，针对基于相同的传感器，已经用如图6到图10中所示出的不同支持电路的长宽比来找到多个最佳的错开配置。可以通过改变像素列和支持电路之间的交点的范围之内的互连的位置和支持电路到每个像素列的分配模式来找到最佳的配置。还应当注意的是，图6到图10中所示出的所有互连彼此距离超过7个像素。
在图7中，如图中的加粗的纵向线示出的可用于支持电路放置的区域可以等于两个像素单元宽乘以三十二个像素单元长。因此，基板1852和基板1854之间的互连必须落入六十四个像素单元区域中的某个地方，以便读取那个列。还应当注意的是，在该实例中的支持电路区域的长宽比为2/32。每个像素列是或者可以是一个像素宽和六十四个像素长并且可以具有从像素列的顶部延伸到底部的一个读取总线。互连的放置选择在该区域中具有多个选项并且可以被选择为使得允许从互连到互连的期望间隔。此外，因为互连可以仅位于像素列读取总线和支持电路读取总线重叠的地方，所以为了读取对应的像素列，互连范围可以是一个像素宽和三十二个像素长（针对该实例），这是连接的像素列和支持电路之间的交点。
在图8中，如图中的加粗的纵向线示出的可用于支持电路放置的区域可以等于四个像素单元宽乘以十六个像素单元长。因此，基板之间的互连必须落入六十四个像素单元区域中的某个地方，以便读取对应的像素列。应当注意的是，在该实例中的支持电路区域的长宽比为4/16。每个像素列是或者可以是一个像素宽和六十四个像素长并且可以具有从像素列的顶部延伸到底部的一个读取总线。互连的放置选择在该区域中具有多个选项并且可以被选择为使得允许从互连到互连的期望间隔。
此外，因为互连仅可以位于像素列读取总线和支持电路读取总线重叠的地方，为了读取对应的像素列，互连范围可以是一个像素宽和十六个像素长（针对该实例），这是连接的像素列和支持电路之间的交点。
在图9中，如图中的加粗的纵向线示出的可用于支持电路放置的区域可以等于八个像素单元宽乘以八个像素单元长。因此，基板1852和基板1854之间的互连1824必须落入六十四个像素单元区域中的某个地方，以便读取对应的像素列。应当注意的是，在该实例中的支持电路区域的长宽比为8/8。每个像素列是或者可以是一个像素宽和六十四个像素长并且可以具有从像素列的顶部延伸到底部的一个读取总线。互连的放置选择在该区域中具有多个选项并且可以被选择为使得允许从互连到互连的期望间隔。
此外，因为互连仅可以位于像素列读取总线和支持电路读取总线重叠的地方，为了读取对应的像素列，互连范围可以是一个像素宽和八个像素长（针对该实例），这是连接的像素列和支持电路之间的交点。
在图10中，如图中的加粗的纵向线示出的可用于支持电路放置的区域可以等于十六个像素单元宽乘以四个像素单元长。因此，基板之间的互连必须落入六十四个像素单元区域中的某个地方，以便读取对应的像素列。应当注意的是，在该实例中的支持电路区域的长宽比为16/4，该实例示出本文所公开的这些方法和装置可以提供的灵活性。每个像素列是或者可以是一个像素宽和六十四个像素长并且可以具有从像素列的顶部延伸到底部的一个读取总线。互连的放置选择在该区域中具有多个选项并且可以被选择为使得允许从互连到互连的期望间隔。
此外，因为互连仅可以位于像素列读取总线和支持电路读取总线重叠的地方，为了读取对应的像素列，互连范围可以是一个像素宽和四个像素长（针对该实例），这是连接的像素列和支持电路之间的交点。
还应当注意的是，支持电路关联到像素列的关联模式可以与图6到图10的支持电路到像素列的关联模式不同，并且该关联可以最终提供彼此远离的互连的最佳距离。例如，互连可以被最佳地放置为至少相距两个像素宽度、相距四个像素宽度、相距八个像素宽度或者彼此相距更多宽度。设计者可以基于下面的两个自由度来最佳确定互连可以被彼此远离地放置的距离：（1）每个列的像素数量，和（2）电路长宽比和位置。在图6-图10中所示出的实例中，互连1824可以被放置为彼此距离大约八个像素。然而，应当理解的是，可以在不脱离本公开的精神或范围的情况下实现其他设计。
例如，如图6所示，每个互连1824可以被放置为彼此在长度上距离八个像素并且在宽度上距离一个像素。因为每个电路列具有一个像素宽和六十四个像素长的 长宽比，然后可以如图6中所示出的，在邻近的列中彼此距离八个像素放置每个互连1824，直到达到电路1800的底部为止，在该情况中，随后将互连1824移动到下一列的顶部并且针对像素阵列1810的整个宽度继续。相反地，在图10中，互连1824仍然被放置为彼此在长度上距离八个像素并且在宽度是距离一个像素。然而，在该实例中，电路列长宽比现在是四个像素长度和十六个像素宽度。因此，对于彼此距离至少八个像素的互连1824来说，由于长宽比仅为四个像素长度，所以必须跳过一个电路列1856b，从而互连1824维持最佳的间隔。因此，例如，在图10中的像素阵列的左上角中（在第一列1828的第一个像素上）放置互连1824并且随后移动到下一个像素列1830并且向下计数八个像素长度，然后可以在第三个电路列1856c中放置下一个互连1824，总而言之，跳过第二个电路列1856b。可以遍及像素阵列使用该模式。然后通过位于第九像素列中的互连1824a将第二所跳过的电路列1856b连接到像素阵列，并且针对所有跳过的电路列重复该模式。因此，如所示出的，在不脱离本公开的范围的情况下可以实现最佳的互连间隔并且可以适应各种电路设计。
现在参照图11，将讨论具有列和子列的像素阵列1810。如图18所示，示出其中具有六列的像素阵列1810的一部分，每个列被示出从像素阵列的一部分的顶部延伸到像素阵列的底部。应当明白的是，新电路1800将具有像素阵列1810，其中，该像素阵列1810包括用于形成该阵列1810的更多的像素列（在附图中在Y方向延伸的多个像素）和行（在附图中在X方向延伸的多个像素）。为说明性目的和为了讨论和简单起见，本文仅示出有限数量的像素列和行。
像素阵列1810中的每个像素列1828可以被分成子列。子列可以被限定为小于整个像素列的列之内的多个像素并且子列电连接到像素子列总线。因此，每个像素列1828可以存在多个像素子列。每个子列可以具有如51、52、53和54所示出的接触垫片和/或互连以将第一基板上的每个子列总线电连接到位于支持基板上的相关联的或对应的电路列总线。
至少一个像素列总线可以用于提供列1828中的每个像素的电连接。列1828可以被分成多个子列，其中，每个像素子列存在至少一个像素子列总线。每个子列总线可以由分隔器62、63、64进行区分，分隔器可以是物理空间或间隙或者用于将像素子列和/或子列总线与另一个子列和/或子列总线电隔离的其他装置。在使用期间，可以以卷帘类型快门方式读取来自像素的数据，即从（如图11中的四个子列 所示出的）每个子列中的每个像素行基本上同时地。在该配置中，可以由于经由像素子列读取总线和电路列读取总线来连接到专用电路列的大量子列以及用于将总线电连接在一起的互连而基本上减少读取时间。因此，该大量子列总线理论上可以针对整个列（该列在图11中包括四个子列）减少所示出的实施例中的读取时间（即增加读取速度）。在图11中，存在四个子列和子列总线，从而读取时间减少了75%（速度增加了四倍）。应当明白的是，不论子列的数量或配置怎样，卷帘快门可以与其他子列同时地在每个子列的开始处逐行地进行操作，递增地读取子列中的每个像素直到该子列的末端（从位于51、52、53、54的像素行处开始同时读取像素行）。
在其他实施例中，列可以被分成任何数量的子列，列的每个划分（例如，增加子列）接近全局快门功能。如图所示，可以在每个列中错开接触垫片和互连位置。如图所示，来自标记为"A"的列的互连与来自标记为"B"的列中的互连。对于N个列来说，子列的迭代和互连错开是可能的。
现在参照图12到图14c，示出在具有子列读取功能和远距离放置的支持电路的多个基板上建立的成像传感器1200的实施例的各种视图。图12和图14示出在第一基板1210、1410上形成像素阵列1250、1450的多个像素列1252和1452和在第二基板1211、1411上的多个电路列1256、1456（该电路列表示支持电路1270、1470）。
如图12和图12c所示，像素阵列1250可以被分成多个列和子列1252。列和子列的尺寸例如可以基于相关联的电路1270和电路列1256的尺寸。例如，像素子列1252可以为一个像素宽和"N"个像素长（在图12-图12c中，像素子列被示出为一个像素宽和六个像素长）并且电路列1256被示出为具有一个像素宽乘以六个像素长的长宽比。应当理解的是，电路列1256的尺寸和面积规定并且指导像素子列1252的尺寸，因为像素子列1252应当具有基本上与电路列1256相同的面积。像素子列1252可以通过用于将像素读取总线1230电连接到电路读取总线1240的互连1212之间的电连接直接与电路列1256相关联。这些附图示出每个像素子列1252通过读取总线1230和1240连接到该像素子列在电路列1256中的关联电路1270的实例。
这些附图还示出每个子列1252有一个读取总线1230并且每个电路列1256有一个读取总线1240。在该实施例中，电路列1256中的相关联电路1270是一个像素宽和六个像素长，但是应当理解的是，本公开可以使用任何电路列长宽比。如图12-图12c所示，这些列都已经被分成两个子列1287、1288。因此，像素列读取总线1230可以被制造成对应的像素子列读取总线1230a和1230b。像素子列1287、1288 中的每一个可以首先连接到像素列总线1230a或1230b并且随后连接到支持电路1270和电路列1256，或者子列1287、1288中的每一个可以通过它们自己的互连1212a和1212b分别直接地连接到电路1270和电路列1256并且连接到相关联的电路总线1240a和1240b。
如上本文所示，每个像素子列3452可以电气地关联或者连接到一个像素子列总线1230，并且每个电路列1256可以电气地关联或者连接到一个电路列总线1240。图12a-图12c分别示出单个像素列1252的透视图、正视图和侧视图，其中，像素列1252已经分成与图12中示出的多个像素列1252和多个电路1256分离的子列1287、1288和两个相关联电路列1256。如图12a-图12c所示，每个像素列有两个读取总线1230a、1230b，其由此将列分成两个子列。两个支持电路（每个像素子列读取总线一个支持电路）。在该配置中，电路列的长宽比为6/1，像素子列的长宽比也为6/1，并且整个像素列的长宽比为12/1。
图12a-图12c还进一步示出在像素子列1287、1288的像素子列总线1230a和1230b与电路列1256之间对每个子列连接使用一个或多个互连1212的电连接。虽然可以使用一个或多个互连1212来电连接像素子总线1230a和1230b和总线1240a和1240b，但是这些附图示出互连1212可以在不脱离本公开的精神和范围的情况下位于沿着像素子总线1230a和1230b与总线1240的重叠路径的任何地方。
图13和图13a示出像素列已经被分成多个子列的可替选的实施例，每个子列具有它们自己的总线。然而，子列被示出为通过它们单个总线连接到单独的电路列。
类似于图12-图12c，图14-图14c示出被分成多个列和子列1452的像素阵列1450。列和子列的尺寸可以例如基于相关联电路1470和电路列1456的尺寸。例如，像素子列1452可以为一个像素宽和"N"个像素长（在图14-图14c中，像素子列被示出为一个像素宽和六个像素长，然而，整个列被示出为一个像素宽和十二个像素长）并且电路列1456被示出为具有两个像素宽乘以三个像素长的长宽比。应当理解的是，电路列1456的尺寸和面积可以规定并且指导像素子列1452的尺寸，因为像素子列1452应当具有基本上与电路列1456相同的面积。像素子列1452可以通过互连1412之间的电连接直接与电路列1456相关联，其中，互连1412将像素读取总线1430电连接到电路读取总线1440。这些附图示出每个像素子列1452通过读取总线1430和1440连接到该像素子列在电路列1456中关联电路1470的实例。
附图还示出每个像素子列1452有一个读取总线1430并且每个电路列1456有 一个读取总线1440。在该实施例中，电路列1456中的相关联电路1470是两个像素宽和三个像素长，但是应当理解的是，本公开可以使用任何电路列长宽比。如图14-图14c所示，这些列都已经被分成两个子列1487、1488。因此，像素列读取总线1430可以被制造成对应的像素子列读取总线1430a和1430b。每个像素子列1487、1488可以首先连接到像素列总线1430a或1430b并且随后连接到支持电路1470和电路列1456，或者每个子列1487、1488可以通过它们自己的互连1412a和1412b分别直接地连接到电路1470和电路列1456并且连接到相关联的电路总线1440a和1440b。
如上文所示，每个像素子列1452可以电气地关联或者连接到一个像素子列总线1430，并且每个电路列1456可以电气地关联或者连接到一个电路列总线1440。图14a-图14c分别示出单个像素列1452的透视图、正视图和侧视图，其中，像素列1452已经分成图14中示出多个像素列1452和多个电路1456分离的子列1487、1488和两个相关联电路列1456。如图14a-图14c所示，整个像素列存在两个读取总线。然而，如所示出的两个读取总线1430a、1430b的出现被示出为彼此不电连接的、分开并且不同的总线，从而存在将列隔成两个子列的间隔或分隔器（如上述涉及图11中讨论的）。因此，还可以存在两个支持电路和电路列读取总线（每个像素子列读取总线一个支持电路和电路列总线）。在该配置中，电路列的长宽比为3/2，像素子列的长宽比也为6/1，并且整个像素列的长宽比为12/1。
图14a-图14c进一步示出在像素子列1487、1488的像素子列总线1430a和1430b与电路列1456之间使用每个子列连接一个或多个互连1412的电连接。虽然可以使用一个或多个互连1412电连接像素子总线1430a和1430b和电路列总线1440a和1440b，但是附图示出互连1412可以在不脱离本公开的精神和范围的情况下位于沿着像素子总线1430a和1430b与电路列总线1440的重叠路径的任何地方。
图14-图14c还示出基板之间的长宽比不同可以如何允许总线接触点中的灵活性。在一个实施例中，列电路总线1440已经被设计成通用u形状，以更均匀地占据电路列1456的区域，由此提供遍及整个电路列1456用于连接互连1412的选项。注意像素列总线1430不是大体上U形的，但是电路列总线1440可以为大体上U形的，从而可以将相同的列电路1456用于两种邻近的、但不同的像素列配置。U形的电路列总线1440a和1440b的第一分叉可以被重叠到像素子列1487和1488的读取总线1430a和1430b（如图14a所示）。位于电路列总线1440a和1440b之间的 U形的电路列总线1442的第二分叉可以被重叠到下一个、邻近的像素列1452的读取总线1430（如图14中最佳所示出的）。图14a-图14c示出从图14的像素阵列1450中取出的单个像素子列集合1487和1488。应当注意的是，因为电路列1456的长宽比被示出为两个像素宽乘以三个像素长，其是对应的像素子列1487和1488的长度的一半，并且互连1412位置选项仅为可用于像素子列长度的部分。
图14b示出，对于复杂的总线形状，沿着电路列1456中的总线1440a和1440b可以存在两条互连位置路径选项，其中，电路列1456的宽度为电路列1456所支持的像素子列1487和1488宽度的两倍。图14b示出U形的电路列总线1440b的第一分叉到像素子列1488的读取总线1430b的重叠的正视图，并且与如图14和图14a所示的总线1440b的最内层部分相反，使用总线1440b的最外层部分来放置互连321，以便将互连321到放置到下一个相邻像素列1452。
图14示出位于图14a-图14c中所示出的像素子列1487和1488的左边并且相对于该像素子列1487和1488的下一个像素子列1452。图14中所示出的下一个像素子列1452的总线1430可以电连接到如所示出的可以位于电路总线1440a和1440b之间的不同的电路总线1442。应当注意的是，因为电路列1456的覆盖区具有2个像素宽乘以3个像素长的长宽比，所以将像素子列总线1430重叠到电路列总线1442需要大体上U形的电路列总线1442的第二分叉，以由此允许总线1442关于图14中示出的下一个像素子列1452和该像素子列对应的总线（关于子列1487）的自然匹配或者重叠。
图15示出在基板/芯片上具有错开的互连或凸块1824定位和子列的像素阵列1810的实施例和配置。如上所示，因为每个像素列1828（或子列）有一个读取总线并且每个电路列有一个读取总线，并且因为读取总线从列的顶部延伸到列的底部，并且因为像素列可以被分成子列，每个子列具有它们自己的像素列总线，所以互连/凸块1824可以位于沿着子列总线和电路列总线的重叠路径的任何地方。在附图中，分隔器1866可以是物理空间或间隙或者用于将像素子列和/或子列总线与另一个子列和/或子列总线电隔离的某些其他装置，该分隔器可以将像素列总线分成像素子列总线。
如图15所示，像素1826的第一子列1828a可以经由第一互连1824a电连接到该第一子列对应的电路列1856，其中，该第一互连1824a连接到总线1830和1840，并且第二子列1828b由第二互连1824b以类似的方式电连接。在一个实施例中，可 以通过第二子列互连集合电气地接入第二像素列，其中该第二子列互连集合已经在制造期间在子列配置中相对于所述第一列互连被定位。如所示出的，第二互连的位置或定位可以在X和Y维度或方向与第一互连的定位相距两个像素宽度。第三互连集合可以后续以类似方式定位在第三像素列中并且针对像素阵列1810上N个互连集合以此类推。
图16示出被配置为使得每个列分成两个子列并且随后错开的像素阵列。可用于放置第一像素列1881的支持电路的区域与上述所描述的像素子列配置相互关联。如上面进一步讨论的，支持电路区域直接地与该支持电路区域对应的像素列区域相互关联。在图16中，如图中的加粗的纵向线示出可用于支持电路放置的区域可以等于一个像素单元宽乘以六十四个像素单元长。此外，每个电路列可以与子列中的一个子列相互关联，或者可替选的，电路列还可以以与像素列对应的方式相互关联。
应当注意的是，图16中的支持电路区域的示例性的长宽比被示出为1/64。在那个区域之内存在定位或者放置子列的互连的多个选项，并且随后可以由设计者选择最终的位置从而允许从互连到互连之间的期望间隔。
图17示出显示本公开的教导和原理的可伸缩性的示意性地大的图像传感器。如图所示，可用于支持电路放置的区域可以等于四个像素单元宽乘以十六个像素单元长，其如图中的加粗的纵向线示出的。如所示出的，每个用于表示像素子列的像素列可以有多个互连2516和2518，从而允许用于大的阵列配置的更多子列功能。因此，基板之间的互连必须落入子列像素单元区域中的某个地方，以便读取对应的像素列。应当注意的是，在该实例中的支持电路区域的长宽比为4/16，子列长宽比为1/64并且像素列为1/128。因此，每个像素列存在像素子列。在该实例中，如果不划分该阵列，则帧读取时间（一个卷帘周期）是划分该阵列的帧读取时间的一半。同时存在两个行地址。整个像素阵列可以作为两个独立的、自我一致的子阵列。该实施例为自身适用于支持直接对应像素子列的支持电路。互连的放置选择在该区域中具有多个选项并且可以被选择为使得允许从互连到互连的期望间隔。如附图所示，通过重复本公开的方法，甚至可以将这些方法用于最新的成像传感器技术。
图18示出显示本公开的教导和原理的可伸缩性的示意性地大的图像传感器。每列多个互连2616、2618指示像素列已经被划分成子列。如图所示，可用于像素子列的支持电路放置的区域可以等于两个像素单元宽乘以三十二个像素单元长，其如图中的加粗的纵向线示出的。因此，基板之间的互连必须落入六十四个像素单元 区域中的某个地方，以便读取对应的像素子列。应当注意的是，支持电路区域的长宽比为2/32。互连的放置选择在该区域中具有多个选项并且可以被选择为使得允许从互连到互连的期望间隔。如附图所示，通过重复本公开的方法，甚至可以将这些方法用于最新的成像传感器技术。
应当明白的是，本文所公开的结构和设备仅仅是用于优化成像传感器的实例，并且应当明白的是，用于执行与本文所公开的那些相同或等同的功能的、用于优化图像传感器的结构、设备或系统，包括现在是已知的或者可以在将来变得可用的用于成像的那些结构、设备或者系统，旨在落入本公开的范围之内。与用于优化图像传感器的装置功能相同或等同的任何事物落入本公开的范围之内。
相关领域中的那些普通技术人员将理解由本公开的特征提供的优点。例如，本公开的潜在特征在于提供最优化成像传感器，这在设计和制造中是简单的。本公开的另一个潜在特征在于提供相对于全部尺寸来说具有较大像素的该成像传感器。
在前述详细说明中，为了简化公开，公开的多种特征被集合在单个实施例中。该公开的方法不被解释为反映意图使所要求的公开需要比每个权利要求中所目前地记载的特征更多的特征。相反，如所附权利要求所反映的、创造性的方案包括比单个前文所公开的实施方式的全部特征更少的特征，并且可以组合独立的实施方式中公开的各种创造性的特征以形成如所附权利要求中更完整地要求的它自己的实施方式。因此，通过参考的方式将所附权利要求并入说明书中，其中，每个权利要求自己代表本文的公开的独立的实施方式。
应当理解的是，以上描述的设置仅仅是对本文的公开原理的示例性应用。在不脱离本公开的精神和范围的情况下，本领域的那些技术人员可以设计多种改进和可替换的设置，并且本文的公开意欲覆盖这些改进和设置。因此，尽管已经在附图中示出了并且在上文利用特性和细节描述了对本文的公开，但是对于本领域普通技术人员来说，在不脱离本文中阐述的原理和概念的情况下，显然可以进行多种改进（包括但不限于尺寸、材料、形状、形式、功能和延伸方式、组装和使用上的变化）。

Claims (27)

1.一种成像传感器，包括：
多个基板；
像素阵列，所述像素阵列包括被形成为像素列的像素；
其中，所述像素列划分为像素子列，所述像素子列被配置为通过像素子列总线从一个子列到另一个子列而被独立读取；
多个支持电路，所述多个支持电路中的每个支持电路具有电路总线；
其中，所述多个基板中的第一基板包括像素阵列；
其中，所述多个支持电路设置在相对于所述第一基板远程地设置的支持基板上；
其中，所述多个支持电路中的一个支持电路与所述像素阵列的对应子列电连接并且电通信；以及
其中，由设置在所述第一基板和所述支持基板之间的互连提供所述电通信，
其中，所述像素子列被限定为小于整个像素列的列之内的多个像素。
2.根据权利要求1所述的成像传感器，其中，每个像素子列总线和每个电路总线重叠，使得每个像素子列总线和所述每个电路总线在所述子列的一部分内基本上对齐；并且
其中，至少一个互连提供在所述子列的对齐部分内的所述每个像素子列总线和所述每个电路总线之间的电连接。
3.根据权利要求2所述的成像传感器，其中，一个像素子列和一个电路总线之间的电连接由单个互连来实现。
4.根据权利要求2所述的成像传感器，其中，一个像素子列和一个电路总线之间的电连接由多个互连来实现，其中，所述多个互连中的每个互连设置在像素子列中。
5.根据权利要求1所述的成像传感器，其中，所述成像传感器是背面照明的。
6.根据权利要求1所述的成像传感器，其中，所述多个基板进一步包括多个后续支持基板。
7.根据权利要求1所述的成像传感器，其中，每个像素子列与其他像素子 列电隔离。
8.根据权利要求1所述的成像传感器，其中，所述像素子列电连接至与用于支持所述像素子列所位于的像素列的支持电路相同的支持电路。
9.根据权利要求1所述的成像传感器，其中，所述支持基板包括专用于且对应于像素阵列中的每个像素子列的支持电路。
10.根据权利要求1所述的成像传感器，其中，所述像素子列被电气地配置为在基本上相同的时刻被读取。
11.一种用于访问成像传感器上的数据的方法，包括：
将位于第一基板上的像素阵列中的像素电连接至第二基板上的支持电路；
其中，所述像素阵列被组织为像素列；
其中，所述像素列被划分为像素子列；
从每个像素子列中的第一像素开始读取多个像素子列，并且按顺序读取来自每个像素的像素数据直到读取了所述子列中的最后一个像素为止；
通过互连将所述像素数据传输至位于所述第二基板上并且包括多个电路列的多个对应的支持电路，
其中，来自一个像素子列的数据由对应于所述一个像素子列的一个电路列来处理，
将所述像素数据处理为图像，
其中，所述像素子列被限定为小于整个像素列的列之内的多个像素。
12.根据权利要求11所述的用于访问成像传感器上的数据的方法，进一步包括从每个像素子列同时读取像素数据。
13.根据权利要求11所述的用于访问成像传感器上的数据的方法，进一步包括将所述像素数据传输至与来自相同像素列内的多个像素子列相对应的支持电路。
14.一种成像传感器，包括：
多个基板，所述多个基板至少包括第一基板和第二基板；
像素阵列，所述像素阵列位于所述第一基板上并且包括多个像素列，其中，所述多个像素列中的每个像素列的宽度被限定为一个像素并且长度被限定为多个像素，以足以覆盖所述阵列的尺寸；
其中，所述像素列划分为像素子列，使得每个像素子列与其他像素子列电 隔离；
多个支持电路，所述多个支持电路位于所述第二基板上并且包括多个电路列，其中，一个电路列与一个像素子列对应，其中，所述多个电路列中的每个电路列被限定为具有与对应像素子列的面积对应的面积；
多个总线，其中，位于第一基板上的每至少一个像素子列有一个像素子列总线并且位于所述第二基板上的每个电路列有一个电路列总线；
其中，每个所述像素子列总线中的至少一部分与每个所述对应电路列总线中的至少一个部分重叠，并且至少一个互连提供一个像素子列总线和一个对应电路列总线之间的电通信；以及
其中，所述至少一个互连位于在一个像素子列总线和一个对应电路列总线之间的任何地方并且关于彼此重叠，
其中，所述像素子列被限定为小于整个像素列的列之内的多个像素。
15.根据权利要求14所述的成像传感器，进一步包括设置在所述基板之间的多个互连，并且其中，所述多个互连相对彼此间隔比所述像素阵列的像素间距更大的距离。
16.根据权利要求14所述的成像传感器，其中，所述第一基板和所述第二基板对齐。
17.根据权利要求14所述的成像传感器，其中，所述第一基板上的一个所述像素子列的面积基本上等于所述第二基板上的一个所述对应电路列的面积。
18.根据权利要求14所述的成像传感器，其中，所述第二基板和所述第一基板的尺寸基本上相同。
19.根据权利要求14所述的成像传感器，其中，所述第一基板上的一个所述像素子列的面积大于所述第二基板上的一个所述对应电路列的面积。
20.根据权利要求14所述的成像传感器，其中，所述第一基板上的一个所述像素子列的面积小于所述第二基板上的一个所述对应电路列的面积。
21.根据权利要求14所述的成像传感器，其中，一个所述像素子列的长宽比与一个所述电路列的长宽比相等。
22.根据权利要求14所述的成像传感器，其中，多个互连将像素子列总线连接至对应电路列总线。
23.根据权利要求14所述的成像传感器，其中，一个所述像素子列的长宽 比与一个所述电路列的长宽比不同。
24.根据权利要求14所述的成像传感器，其中，至少一个所述电路列的长宽比与一个所述像素子列的长宽比相比，宽度为“N”倍个像素并且长度为1/“M”倍个像素。
25.根据权利要求14所述的成像传感器，其中，至少一个所述电路列的长宽比与一个所述像素子列的长宽比相比，宽度为两倍并且长度为一半。
26.根据权利要求14所述的成像传感器，其中，至少一个所述电路列的长宽比与一个所述像素子列的长宽比相比，宽度为四倍并且长度为四分之一。
27.根据权利要求14所述的成像传感器，至少一个所述电路列的长宽比与一个所述像素子列的长宽比相比，宽度为八倍并且长度为八分之一。
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