CN103645886A

CN103645886A - Addition/subtraction, multiplication and division operation control unit for multiple floating-point operands

Info

Publication number: CN103645886A
Application number: CN201310681596.1A
Authority: CN
Inventors: 李克俭; 蔡启仲; 黄仕林; 任杰; 王鸣桃
Original assignee: Guangxi University of Science and Technology
Current assignee: Guangxi University of Science and Technology
Priority date: 2013-12-13
Filing date: 2013-12-13
Publication date: 2014-03-19
Anticipated expiration: 2033-12-13
Also published as: CN103645886B

Abstract

An addition/subtraction, multiplication and division operation control unit for multiple floating-point operands comprises a command word and operand write time sequence control module, an operand memory, an operand read time sequence control module and an operand configuration and operation control module. The control unit applies an FPGA (field programmable gate array) for designing a hard link control circuit, command words and floating-point operands of a write time sequence impulse control command generated in the control unit are continuously written in; a read time sequence impulse which is synchronous with a Clock signal is generated, and four mixed arithmetic operations are autonomously controlled; an operation period can be automatically adjusted according to an operational character of each operand; after the last operand is written in, the operation process is not controlled by a system, and the system can process other instruction programs; a middle operation result and a final operation result can be read while the operation process is executed; and each instruction can have 13 floating-point operands, and when one instruction is executed, equivalently, a microprocessor executes multiple instructions, so that operation processes of instruction fetch and decoding of the system, transmission of the floating-point operands and writing back of the operation results are reduced.

Description

Many floating-point operations number adds/subtracts, multiplication and division arithmetic and control unit

Technical field

The present invention relates to that a kind of many floating-point operations number adds/subtracts, multiplication and division arithmetic and control unit, relate in particular to that a kind of the hardwired many floating-point operations number of FPGA parallel work-flow circuit adds/subtracts based on adopting, multiplication and division arithmetic control circuit and sequential control method thereof.

Background technology

Floating number adds/subtracts, the four fundamental rules hybrid operation of multiplication and division is the very high arithmetical operation of high accuracy data computing applying frequency, and the arithmetical unit of each arithmetic type is realized 2 32 floating point arithmetics that meet IEEE754 standard; Arithmetical unit input participates in two floating-point operation numbers of computing, and one is that 1, one of operand is operand 2, carries out an operation result of once-through operation output, and in calculating process, operand 1 and operand 2 must remain stable; Operand 1 input end of arithmetical unit is connected with the output terminal of a working storage, and operand 2 is connected with the output terminal of another working storage; For the arithmetic operation instruction of most of microprocessors, the computing of 2 operands is carried out in every instruction; Four fundamental rules hybrid operation order for higher level lanquage is all to adopt natural ways of writing to express, four fundamental rules hybrid operation formula is converted into the instruction sequence of the binary code that microprocessor can identify in the compiling of higher level lanquage or translation system, the i.e. computing of 2 operands forms an operational order, and some operand transfer instructions and operation result transfer instruction; Microprocessor needs one by one sense order to carry out decoding, the operation that transmission operand, computing, result write back; Floating number adds/subtracts, in the four fundamental rules hybrid operation of multiplication and division, add/subtract computing cost time clock period minimum, multiplying is taken second place, division arithmetic is than adding/subtract computing, multiplying by the time cycle of cost several times, employing streamline execution floating number adds/subtracts, the instruction sequence of the four fundamental rules hybrid operation of multiplication and division, computing next time need to be applied last time during operation result, and it is that impact carries out that floating number adds/subtracts, the bottleneck of the four fundamental rules hybrid operation instruction sequence speed of multiplication and division that each cycle operation time and result write back arithmetical unit operand input end.

Summary of the invention

The object of the present invention is to provide that a kind of many floating-point operations number adds/subtracts, multiplication and division arithmetic and control unit, for realizing, a plurality of 32 floating numbers that meet IEEE754 standard add/subtract, the hybrid operation of multiplication and division; This controller application FPGA designs that many floating-point operations number adds/subtracts, the hard connecting circuit of multiplication and division arithmetic and control unit, for floating-point operation more than, count the command word of operational order and the method that many floating-point operations number takes to write continuously storage, it writes storing process and takies system bus; Controller is carrying out that many floating-point operations number adds/subtracts, in multiplication and division algorithm process, inner produce synchronize with system clock Clock signal read time sequential pulse signal, read independently to complete under time sequential pulse signal controlling read floating-point operation number carry out add/subtract, multiplication and division computing, the implementation of algorithm does not take system bus, writes many floating-point operations of storage number process and can walk abreast and carry out with the process of carrying out algorithm; Controller is in carrying out algorithm processing procedure, and system can be read intermediate operations result and the final operation result in fill order process.

The technical scheme solving the problems of the technologies described above is: a kind of many floating-point operations number adds/subtracts, multiplication and division arithmetic and control unit, for realizing, a plurality of 32 floating numbers that meet IEEE754 standard add/subtract, the hybrid operation of multiplication and division, comprise that command word and operand write time-sequence control module, operand store, operand and read time-sequence control module, operand configuration and s operation control module;

Described command word and operand are write time-sequence control module and operand store, operand and are read time-sequence control module, operand configuration and s operation control module and be connected;

Described operand store is also read time-sequence control module, operand configuration and s operation control module with operand and is connected;

Described operand is read time-sequence control module and is also connected with operand configuration and s operation control module;

Described command word and operand are write time-sequence control module and have been controlled writing and storing of instruction, need to take system bus; Article one, instruction comprises 32 order of the bit words and several operands, and operand mostly is 13 most; When described command word and operand are write time-sequence control module and chosen by system, startup command word and operand are write time-sequence control module work, inner produce synchronize with system WR signal write time sequential pulse sequence; Under the control of writing time sequential pulse, latch that many floating-point operations number adds/subtracts, the command word of multiplication and division operational order, write many floating-point operations number of instruction and stored; Last floating-point operation number is written into after storage, and described command word and operand are write time-sequence control module and quit work;

Described operand store is dual-ported memory, write port, and read port, for storing floating-point operation number (under be called operand); There is not the situation that needs arbitration in write and the reading of read port operand of the write port operand of described operand store; Write port is subject to command word and operand to write time-sequence control module to control, and the operand write operation of system data bus DB transmission is counted to storer; Read port is subject to operand to read time-sequence control module to control, and operand is read and is transferred to operand configuration and s operation control module;

Described operand is read time-sequence control module and in inside, is read, under the control of time sequential pulse, independently to complete floating-point operation number reading from operand store, does not need to take system bus; Described operand is read time-sequence control module and is write after time-sequence control module writes the 1st operand and be activated work at command word and operand, output busy signal Busy is by " 1 " → " 0 ", and according to the 1st operand type, inner produce synchronize with system clock Clock signal read time sequential pulse sequence, in order operand is read to participation computing, and automatically adjusted execution cycle according to the operational symbol of each operand; After last 1 operand of participation computing is read, then through an execution cycle, output busy signal Busy, by " 0 " → " 1 ", sends after the result latch pulse of a clock period Clock, and shut-down operation number is read the work of time-sequence control module;

The operational symbol that the configuration of described operand and s operation control module are write time-sequence control module output according to command word and operand selects the corresponding arithmetical unit of each operand to calculate, and according to the type gating configuration of the 1st operand of output, participates in adding/subtract or operand 1 and the operand 2 of multiplying; When the 1st operand is division arithmetic, also need to participate according to the 1st operand division arithmetic mode gating configuration operand a and the operand b of division arithmetic; Described operand configuration and s operation control module can latch the result of calculation of each computing, and judge that whether result of calculation is abnormal; System can be read the final operation result of intermediate operations result and command execution from operand configuration and s operation control module.

Its further technical scheme is: described command word and operand write time-sequence control module comprise controller identification, write address counter, write operation count pulse generation control module, mode type register, operational symbol shift register and with door I;

The input end of described controller identification and the A31 of system address bus AB are connected to A27 line, and CS signal output part is connected with the enabling signal input end that write operation is counted pulse generation control module, are also connected with operand configuration and s operation control module; Described controller identification input A31 identifies with controller the address value setting to the address value of A27 and equates, the CS signal output part of controller identification is " 0 ", otherwise CS signal output part is " 1 ";

The operand number input end of described write address counter is connected to D0 line with the D3 of system data bus DB, writing pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module with write operation is connected, writing pulse 3. _ 1 output terminal that count pulse input end counts pulse generation control module with write operation is connected, write address output terminal is connected with the write address input end AB_1 of operand store, writes to overflow output terminal and be connected with an input end of door I;

Described write address counter is in fact one and subtracts 1 counter, the D3 of system DB is that participation adds/subtracts, an operand numerical value of multiplication and division computing to D0 transmission, operand number that will input instruction under the control of writing presetting pulse is as 4 write address initial values of counting initial value and operand store, and juxtaposition writes that to overflow output terminal be one state; Often come one to write count pulse, write address value-1 of write address counter output, retouching operation is counted storer write port memory unit address value, until count value output terminal is " 0 ", be that AB_1 is " 0 ", now write spill over by " 1 " → " 0 ", writing spill over is the sign that operand ablation process finishes;

The clock terminal that described write operation is counted pulse generation control module is connected with system write signal WR line, the RESET input be connected with the output terminal of door I, pulse 1. _ 1 output terminal is also read time-sequence control module and is connected with latch signal input end, the latch signal input end of operational symbol shift register, the operand of mode type register, and pulse 2. _ 1 output terminal is read time-sequence control module with WR_1 input end, the operand of operand store write port and is connected;

When CS is " 0 ", described write operation is counted the startup work under the effect of the 1st WR signal of system of pulse generation control module, export in order pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, until reset signal input end is just quit work by " 1 " → " 0 ", putting pulse 1. _ 1, pulse 2. _ 1 and pulse 3. _ 1 output terminal is one state;

The input end of described mode type register is connected with D4 line with the D5 of system data bus DB, and class type output terminal is read time-sequence control module with operand and is connected, and mode output terminal is connected with operand configuration and s operation control module; Described mode type register is under the effect of pulse 1. _ 1 negative edge, by the status lock existing way type register of the mode of the 1st operand and type;

The input end of described operational symbol shift register is connected to D6 line with the D31 of system data bus DB, shift pulse input end is read time-sequence control module with operand and is connected, and operational symbol output terminal is read time-sequence control module with operand and is connected with operand configuration and s operation control module;

Describedly be connected with the configuration of systematic reset signal Rst line, operand and s operation control module respectively with another two input ends of door I.

Its further technical scheme is: described operand read time-sequence control module comprise read address counter, read operation count pulse generation control module, with door an II, with door III and with door IV;

The operand number input end of described read address counter and the D3 of system data bus DB are connected to D0 line, reading pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module with write operation is connected, read count pulse input end and be connected with the output terminal of door IV, read address output end and be connected with the address input end AB_2 that reads of operand store, read to overflow output terminal and read operation count pulse generation control module read overflow input end and be connected;

Described read address counter is in fact one and subtracts 1 counter, operand number using the D3 from system data bus DB to D0 under the effect of reading presetting pulse is read address initial value as counting initial value and operand store read port, and it is one state that juxtaposition reads to overflow output end signal; Often come one to read count pulse, read address counter output read address value-1, retouching operation is counted storer read port memory unit address value, until be " 0 ", read spill over by " 1 " → " 0 ", representing just at exectorial last operand, to read, is also the out-of-work sign of read address counter;

The clock terminal that pulse generation control module is counted in described read operation is connected with system clock Clock line, the RESET input be connected with the output terminal of door III, reading to start pulse 2. _ 1 output terminal that input end counts pulse generation control module with write operation is connected, type input end is connected with the class type output terminal of mode type register, and the operational symbol output terminal of operational symbol input end AND operator shift register connects; Pulse 1. _ 2 output terminals are connected with an input end, operand configuration and s operation control module with door II; Pulse 2. _ 2 output terminals are connected with an input end, operand configuration and s operation control module with door IV; Pulse 3. _ 2 output terminals be connected with another input end of door II; Pulse 4. _ 2 output terminals be connected with another input end of door IV; Pulse 5. _ 2 is connected with operand configuration and s operation control module with pulse 6. _ 2 output terminals; Busy output terminal is to system output Busy busy signal;

The pulse that pulse generation control module output is counted in described read operation is synchronizeed with system clock Clock, according to type input signal, be that " 0 " is still " 1 ", determines that control operation counts the pulse train of read operation number in storer; Read to start input end by " 1 " → " 0 ", Busy output terminal, by " 1 " → " 0 " state, starts the work that pulse generation control module is counted in read operation; When read address counter output read spill over by " 1 " → " 0 " time, put pulse 4. _ 2 output terminals for " 1 ", read operation is counted pulse generation control module through an execution cycle time, send latch result pulse 5. _ 2 controls in a system clock Clock cycle and latch operation result, output busy signal Busy is by " 0 " → " 1 ", stop read operation and count the work of pulse generation control module, putting all pulse output ends is one state; When the reset signal of input is " 0 ", pulse generation control module is counted in reset read operation, and putting all pulse output ends is one state, and Busy output terminal is one state;

Described read operation is counted pulse generation control module and is participated in the operand operational symbol of computing according to each, automatically adjusts the execution cycle time of corresponding each operand;

Describedly be connected with the door output terminal of II and the read signal input end RD_2 of operand store, the shift pulse input end of operational symbol shift register; From operand store, read an operand, the operational symbol data in operational symbol shift register move right two, make each operand AND operator that participates in computing corresponding one by one;

Describedly be connected with the configuration of systematic reset signal Rst line, operand and s operation control module respectively with two input ends of door III.

Its further technical scheme is: the configuration of described operand and s operation control module comprise that gate, result register, floating number add/subtract that arithmetical unit, floating number multiplication device, floating number division operation device, operand interchanger, computing abnormality mark are controlled, 32 triple gate groups, with a door V, with door VI or door I and or door II;

An input end of described gate is connected with the operand output terminal DB_2 of operand store, and another input end adds/subtracts arithmetical unit, floating number multiplication device and the operation result output terminal of floating number division operation device with floating number and is connected; Output terminal is connected with the input end of result register; Gating control input end be connected with the output terminal of door V;

The latch signal input end of described result register be connected with the output terminal of door VI, output terminal is connected with operand 1 input end that floating number adds/subtract arithmetical unit, floating number multiplication device, operand interchanger, is also connected with the input end of 32 triple gate groups;

Described floating number adds/subtract operand 2 input ends of arithmetical unit and the operand output terminal DB_2 of operand store is connected, the operational symbol output terminal of operational symbol input end AND operator shift register connects, and operation result output terminal is also connected with the operation result input end that computing abnormality mark is controlled;

Operand 2 input ends of described floating number multiplication device and the operand output terminal DB_2 of operand store are connected, the operational symbol output terminal of operational symbol input end AND operator shift register connects, and operation result output terminal is also connected with the operation result input end that computing abnormality mark is controlled;

The operand a of described floating number division operation device is connected with two output terminals of operand interchanger respectively with operand b input end; Operation result output terminal is also connected with the operation result input end that computing abnormality mark is controlled;

Operand 2 input ends of described operand interchanger and the operand output terminal DB_2 of operand store are connected, exchange control end and or the output terminal of I be connected;

Latch result pulse 5. _ 2 output terminals that the latch signal input end that described computing abnormality mark is controlled is counted pulse generation control module with read operation are connected; IRQ output terminal is with another input end with door I, is connected with another input end of door III, and IRQ output terminal is also exported interrupt request singal IRQ to system; When middle operation result or final operation result occur when abnormal, described computing abnormality mark is controlled and is sent interrupt request singal IRQ to system, and reset write operand pulse generation control module and read operation count pulse generation control module, cease and desist order word and operand are write the work that time-sequence control module and operand are read time-sequence control module;

The output terminal of described 32 triple gate groups is connected with system data bus DB, control input end with or door II output terminal be connected;

Described with door V two input ends count the pulse 1. _ 2 of pulse generation control module, the output terminal of pulse 2. _ 2 is connected with read operation respectively;

Described with door VI two input ends count the pulse 2. _ 2 of pulse generation control module, the output terminal of pulse 5. _ 2 is connected with read operation respectively;

The output terminal that two input ends described or door I are counted the pulse 6. _ 2 of pulse generation control module with mode output terminal, the read operation of mode type register is respectively connected;

Two input ends described or door II are connected with CS signal output part, the system read signal RD line of controller identification respectively; When CS is " 0 ", under the effect of system RD signal, read the final operation result of intermediate operations result or command execution.

Its further technical scheme is: the type of described mode type register output refers to the type of the 1st operand of reading from operand store, the mode of output refers to when type is " 0 ", the 1st operand participated in the processing mode of division arithmetic, and the operational symbol of operational symbol shift register output is the symbol that operand participates in computing;

Operational symbol is by two marking codes: 00: additive operation; 01: subtraction; 10: multiplying; 11: division arithmetic;

Type is identified by unitary code:

0: the 1 operand is as participating in adding/subtract or the operand 2 of multiplying, and operation result is as operand 1;

1: the 1 operand as participate in adding/subtract, take advantage of or 1, the 2 operand of operand of division arithmetic as operand 2;

2. _ 2 types in the output of mode type register of pulse 1. _ 2, pulse that pulse generation control module output is counted in described read operation produce during for " 1 "; When pulse 1. _ 2 or pulse 2. _ 2 are " 0 ", the gating control input end of gate is " 0 ", the 1st operand that gate output is read from operand store; When pulse 1. _ 2 and pulse 2. _ 2 are all " 1 ", gate output operation result;

The 1st operand reading from operand store participated in division arithmetic, and mode and type signal are just controlled the division mode at exectorial the 1st operand and operation result:

When mode is " 0 ", when type is " 0 ": what result register was exported is operation result, and operand 1 input end of operand interchanger is operation result, 1st operand of operand 2 input ends of operand interchanger for reading from operand store, when reading the 1st operand, now pulse 6. _ 2 is that " 0 " is effective, because mode is " 0 " state, the control end that makes operand interchanger is " 0 ", the operation result of operand 1 input end of operand interchanger is as the operand b of operand interchanger output, the 1st operand of operand 2 input ends of operand interchanger is as the operand a of operand interchanger output, 2 inputs and 2 outputs that are operand interchanger exchange transmission, the 1st operand is as the operand a of floating number division operation device, operation result is as operand b, carry out the division arithmetic of the 1st operand/operation result,

When mode is " 1 ", type is when " 0 ": when reading the 1st operand, although pulse 6. _ 2 be " 0 " effectively, mode is one state, making the control end of operand interchanger is " 1 ", and 2 inputs of operand interchanger and 2 outputs do not exchange transmission; Operation result is as the operand a of floating number division operation device, and the 1st operand, as operand b, carried out the division arithmetic of operation result/1st operand;

When type is " 1 ": pulse generation control module is counted in read operation can not produce pulse 6. _ 2 signals, pulse 6. _ 2 output terminals are one state, making the control end of operand interchanger is " 1 ", and 2 inputs of operand interchanger and 2 outputs do not exchange transmission; The mode status signal of the 1st operand and input is irrelevant, and the 1st operand is as the operand a of floating number division operation device, and the 2nd operand, as operand b, carried out the division arithmetic of the 1st operand/2nd operand.

Owing to adopting above structure, floating-point operation number adds/subtracts more than the present invention, multiplication and division arithmetic and control unit has following beneficial effect:

One, the command word of an instruction and many floating-point operations number thereof can write storage continuously

More than the present invention, floating-point operation number adds/subtracts, multiplication and division arithmetic and control unit inside is provided with an operand store, inner, count under the control of time sequential pulse with the floating-point operation of writing of system WR impulsive synchronization, after the command word of instruction is written into, the floating-point operation number of this instruction all can be write in order and is stored in operand store.

Two, from main control, complete that many floating-point operations number adds/subtracts, the four fundamental rules hybrid operation of multiplication and division

More than the present invention, floating-point operation number adds/subtracts, take advantage of, division operation controller is after receiving the command word and first operand of instruction, start the inner read operation of controller and count pulse generation control module, produce with the floating-point operation of reading of system clock Clock impulsive synchronization and count time sequential pulse, according to the operational symbol of each floating-point operation number, automatically adjust the time sequential pulse cycle, controller is counted under the control of time sequential pulse in read operation, independently complete the adding/subtract of all floating-point operation numbers of instruction, take advantage of, the four fundamental rules hybrid operation removing, the algorithm process that controller is carried out many floating-point operations number is not controlled by system.

Three, instruction completes the adding/subtract of a plurality of floating-point operation numbers, multiplication and division computing

More than the present invention floating-point operation number add/subtract, in multiplication and division arithmetic and control unit, every instruction can have 13individual floating-point operation number, such instruction is equivalent to identically to add/subtract, many instructions of multiplication and division computing, has reduced the operating process that system writes back the fetching of instruction and decoding, the transmission of floating-point operation number and operation result; On the other hand, controller can be applied and carry out the operation result of a upper instruction and carry out computing with the 1st the floating-point operation number that newly writes instruction.

Four, automatically select to carry out the 1st processing mode that division operation is counted in floating-point operation

More than the present invention, floating-point operation number adds/subtracts, multiplication and division arithmetic and control unit is when carrying out division arithmetic, to the 1st floating-point operation number, can there be three kinds of processing modes, one be the 1st floating-point operation number as dividend, implement the computing of a 1st floating-point operation number/2nd floating-point operation number; Two be the 1st floating-point operation number as dividend, implement the computing of the 1st floating-point operation number/operation result; Three be the 1st floating-point operation number as divisor, implement the computing of an operation result/1st floating-point operation number.

Five, controller cost performance is high

The hard connection control circuit that more than the present invention, floating-point operation number adds/subtracts, multiplication and division arithmetic and control unit be take FPGA is core, realizes that many floating-point operations number adds/subtracts, the four fundamental rules hybrid operation of multiplication and division, and calculating process is not controlled by system; In calculating process, can read intermediate operations result, instruction is carried out and is finished, and can read final operation result; The processing of an instruction has been equivalent to carry out to many instructions of identical operation, has improved processing speed, there is higher cost performance.

Below in conjunction with drawings and Examples to floating-point operation number more than the present invention add/subtract, the technical characterictic of multiplication and division arithmetic and control unit is further described.

Accompanying drawing explanation

Fig. 1: more than the present invention floating-point operation number add/subtract, the system architecture diagram of multiplication and division arithmetic and control unit;

Fig. 2: more than the present invention floating-point operation number add/subtract, the command word of multiplication and division arithmetic and control unit and the circuit connection diagram that operand is write time-sequence control module;

Fig. 3: more than the present invention, floating-point operation number adds/subtracts, the operand of multiplication and division arithmetic and control unit reads the circuit connection diagram of time-sequence control module;

Fig. 4: more than the present invention floating-point operation number add/subtract, the circuit connection diagram of the configuration of the operand of multiplication and division arithmetic and control unit and s operation control module;

Fig. 5: more than the present invention floating-point operation number add/subtract, write order word and the operand sequential chart of multiplication and division arithmetic and control unit;

Fig. 6: more than the present invention, floating-point operation number adds/subtracts, the type 0 of multiplication and division arithmetic and control unit reads multioperand and result latchs sequential chart;

Fig. 7: more than the present invention, floating-point operation number adds/subtracts, the Class1 of multiplication and division arithmetic and control unit reads multioperand and result latchs sequential chart;

Fig. 8: the embodiment of the present invention two more than floating-point operation numbers add/subtract, the operand of multiplication controller configures and the circuit connection diagram of s operation control module.

In figure:

I-command word and operand are write time-sequence control module, II-operand store, and III-operand is read time-sequence control module, the configuration of IV-operand and s operation control module;

The identification of 1-controller, 2-write address counter, 3-write operation is counted pulse generation control module, 4-mode type register, 5-operational symbol shift register, 6-with door an I, 7-read address counter, pulse generation control module is counted in 8-read operation, 9-with door an II, 10-with door an III, 11-with door an IV, 12-gate, 13-result register, 14-floating number adds/subtracts arithmetical unit, 15-floating number multiplication device, 16-floating number division operation device, 17-operand interchanger, 18-computing abnormality mark is controlled, 19-32 triple gate groups, 20-with door a V, 21-with door a VI, 22-or door I, 23-or door II.

Abbreviation explanation in literary composition:

FPGA-Field Programmable Gate Array, field programmable gate array;

DB-Data Bus, data bus;

AB-Address Bus, address bus;

CS-Chip Select, sheet selects or enables, CS representative " enable signal " in figure;

Clock-clock;

RD-Read, reads, representative " read signal " in figure;

WR-Write, writes, representative " write signal " in figure;

IRQ-Interrupt Request, interrupts application, representative " interrupt request singal " in figure;

Busy-busy signal;

Rst-Reset, resets.

Embodiment

Embodiment mono-:

A kind of many floating-point operations number adds/subtracts, multiplication and division arithmetic and control unit, as shown in Figure 1, for realizing, a plurality of 32 floating numbers that meet IEEE754 standard add/subtract, the hybrid operation of multiplication and division, and this controller comprises that command word and operand write time-sequence control module I, operand store II, operand and read time-sequence control module III, operand configuration and s operation control module IV;

Described command word and operand are write time-sequence control module I and operand store II, operand and are read time-sequence control module III, operand configuration and s operation control module IV and be connected;

Described operand store II is also read time-sequence control module III, operand configuration and s operation control module IV with operand and is connected;

Described operand is read time-sequence control module III and is also connected with operand configuration and s operation control module IV;

Described command word and operand are write time-sequence control module I and have been controlled writing and storing of instruction, need to take system bus; Article one, instruction comprises 32 order of the bit words and several operands, and operand mostly is 13 most; When described command word and operand are write time-sequence control module I and chosen by system, startup command word and operand are write the work of time-sequence control module I, inner produce synchronize with system WR signal write time sequential pulse sequence; Under the control of writing time sequential pulse, latch that many floating-point operations number adds/subtracts, the command word of multiplication and division operational order, write many floating-point operations number of instruction and stored; Last floating-point operation number is written into after storage, and described command word and operand are write time-sequence control module I and quit work;

Described operand store II is dual-ported memory, write port, and read port, for storing floating-point operation number (under be called operand); There is not the situation that needs arbitration in write and the reading of read port operand of the write port operand of described operand store II; Write port is subject to command word and operand to write time-sequence control module I to control, and the operand write operation of system data bus DB transmission is counted to storer II; Read port is subject to operand to read time-sequence control module III to control, and operand is read and is transferred to operand configuration and s operation control module IV;

Described operand is read time-sequence control module III and in inside, is read, under the control of time sequential pulse, independently to complete floating-point operation number reading from operand store II, does not need to take system bus; Described operand is read time-sequence control module III and is write after time-sequence control module I writes the 1st operand and be activated work at command word and operand, output busy signal Busy is by " 1 " → " 0 ", and according to the 1st operand type, inner produce synchronize with system clock Clock signal read time sequential pulse sequence, in order operand is read to participation computing, and automatically adjusted execution cycle according to the operational symbol of each operand; After last 1 operand of participation computing is read, then through an execution cycle, output busy signal Busy, by " 0 " → " 1 ", sends after the result latch pulse of a clock period Clock, and shut-down operation number is read the work of time-sequence control module III;

The operational symbol that the configuration of described operand and s operation control module IV are write the output of time-sequence control module I according to command word and operand selects the corresponding arithmetical unit of each operand to calculate, and according to the type gating configuration of the 1st operand of output, participates in adding/subtract or operand 1 and the operand 2 of multiplying; When the 1st operand is division arithmetic, also need to participate according to the 1st operand division arithmetic mode gating configuration operand a and the operand b of division arithmetic; Described operand configuration and s operation control module IV can latch the result of calculation of each computing, and judge that whether result of calculation is abnormal; System can be read the final operation result of intermediate operations result and command execution from operand configuration and s operation control module IV.

As shown in Figure 2, described command word and operand write time-sequence control module I comprise controller identification 1, write address counter 2, write operation count pulse generation control module 3, mode type register 4, operational symbol shift register 5 and with door I 6;

The input end of described controller identification 1 and the A31 of system address bus AB are connected to A27 line, and CS signal output part is connected with the enabling signal input end that write operation is counted pulse generation control module 3, are also connected with operand configuration and s operation control module IV; Described controller identification 1 input A31 identifies 1 address value setting to the address value of A27 with controller and equates, the CS signal output part of controller identification 1 is " 0 ", otherwise CS signal output part is " 1 ";

The operand number input end of described write address counter 2 is connected to D0 line with the D3 of system data bus DB, writing pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module 3 with write operation is connected, writing pulse 3. _ 1 output terminal that count pulse input end counts pulse generation control module 3 with write operation is connected, write address output terminal is connected with the write address input end AB_1 of operand store II, writes to overflow output terminal and be connected with an input end of door I 6;

Described write address counter 2 is in fact one and subtracts 1 counter, the D3 of system DB is that participation adds/subtracts, an operand numerical value of multiplication and division computing to D0 transmission, operand number that will input instruction under the control of writing presetting pulse is as 4 write address initial values of counting initial value and operand store II, and juxtaposition writes that to overflow output terminal be one state; Often come one to write count pulse, write address value-1 of write address counter 2 outputs, retouching operation is counted storer II write port memory unit address value, until count value output terminal is " 0 ", be that AB_1 is " 0 ", now write spill over by " 1 " → " 0 ", writing spill over is the sign that operand ablation process finishes;

The clock terminal that described write operation is counted pulse generation control module 3 is connected with system write signal WR line, the RESET input be connected with the output terminal of door I 6, pulse 1. _ 1 output terminal is also read time-sequence control module III with latch signal input end, the latch signal input end of operational symbol shift register 5, the operand of mode type register 4 and is connected, and pulse 2. _ 1 output terminal is read time-sequence control module III with WR_1 input end, the operand of operand store II write port and is connected;

When CS is " 0 ", described write operation is counted pulse generation control module 3 startup work under the effect of the 1st WR signal of system, export in order pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1(is referring to Fig. 5), until reset signal input end is just quit work by " 1 " → " 0 ", putting pulse 1. _ 1, pulse 2. _ 1 and pulse 3. _ 1 output terminal is one state;

The input end of described mode type register 4 is connected with D4 line with the D5 of system data bus DB, and class type output terminal is read time-sequence control module III with operand and is connected, and mode output terminal is connected with operand configuration and s operation control module IV; Described mode type register 4 is under the effect of pulse 1. _ 1 negative edge, by the status lock existing way type register 4 of the mode of the 1st operand and type;

The input end of described operational symbol shift register 5 is connected to D6 line with the D31 of system data bus DB, shift pulse input end is read time-sequence control module III with operand and is connected, and operational symbol output terminal is read time-sequence control module III with operand and is connected with operand configuration and s operation control module IV;

Describedly be connected with the configuration of systematic reset signal Rst line, operand and s operation control module IV respectively with another two input ends of door I 6.

As shown in Figure 3, described operand read time-sequence control module III comprise read address counter 7, read operation count pulse generation control module 8, with door an II 9, with door III 10 and with door IV 11;

The operand number input end of described read address counter 7 and the D3 of system data bus DB are connected to D0 line, reading pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module 3 with write operation is connected, read count pulse input end and be connected with the output terminal of door IV 11, read address output end and be connected with the address input end AB_2 that reads of operand store II, read to overflow output terminal and read operation count pulse generation control module 8 read overflow input end and be connected;

Described read address counter 7 is in fact one and subtracts 1 counter, operand number using the D3 from system data bus DB to D0 under the effect of reading presetting pulse is read address initial value as counting initial value and operand store II read port, and it is one state that juxtaposition reads to overflow output end signal; Often come one to read count pulse, read address counter 7 output read address value-1, retouching operation is counted storer II read port memory unit address value, until be " 0 ", read spill over by " 1 " → " 0 ", representing just at exectorial last operand, to read, is also the out-of-work sign of read address counter 7;

The clock terminal that pulse generation control module 8 is counted in described read operation is connected with system clock Clock line, the RESET input be connected with the output terminal of door III 10, reading to start pulse 2. _ 1 output terminal that input end counts pulse generation control module 3 with write operation is connected, type input end is connected with the class type output terminal of mode type register 4, and the operational symbol output terminal of operational symbol input end AND operator shift register 5 connects; Pulse 1. _ 2 output terminals are connected with an input end, operand configuration and s operation control module IV with door II 9; Pulse 2. _ 2 output terminals are connected with an input end, operand configuration and s operation control module IV with door IV 11; Pulse 3. _ 2 output terminals be connected with another input end of door II 9; Pulse 4. _ 2 output terminals be connected with another input end of door IV 11; Pulse 5. _ 2 is connected with operand configuration and s operation control module IV with pulse 6. _ 2 output terminals; Busy output terminal is to system output Busy busy signal;

The pulse that pulse generation control module 8 output is counted in described read operation is synchronizeed with system clock Clock, according to type input signal, be that " 0 " is still " 1 ", determines that control operation counts the pulse train of read operation number in storer II (referring to Fig. 6, Fig. 7); Read to start input end by " 1 " → " 0 ", Busy output terminal, by " 1 " → " 0 " state, starts the work that pulse generation control module 8 is counted in read operation; When read address counter 7 output read spill over by " 1 " → " 0 " time, put pulse 4. _ 2 output terminals for " 1 ", read operation is counted pulse generation control module 8 through an execution cycle time, send latch result pulse 5. _ 2 controls in a system clock Clock cycle and latch operation result, output busy signal Busy is by " 0 " → " 1 ", stop read operation and count the work of pulse generation control module 8, putting all pulse output ends is one state; When the reset signal of input is " 0 ", pulse generation control module 8 is counted in reset read operation, and putting all pulse output ends is one state, and Busy output terminal is one state;

Described read operation is counted pulse generation control module 8 and is participated in the operand operational symbol of computing according to each, automatically adjusts the execution cycle time of corresponding each operand;

Describedly be connected with the door output terminal of II 9 and the read signal input end RD_2 of operand store II, the shift pulse input end of operational symbol shift register 5; From operand store II, read an operand, the operational symbol data in operational symbol shift register 5 move right two, make each operand AND operator that participates in computing corresponding one by one;

Describedly be connected with the configuration of systematic reset signal Rst line, operand and s operation control module IV respectively with two input ends of door III 10.

As shown in Figure 4, the configuration of described operand and s operation control module IV comprise gate 12, result register 13, floating number add/subtract arithmetical unit 14, floating number multiplication device 15, floating number division operation device 16, operand interchanger 17, computing abnormality mark control 18,32 triple gate groups 19, with a door V 20, with door VI 21 or door I 22 and or door II 23;

An input end of described gate 12 is connected with the operand output terminal DB_2 of operand store II, and another input end adds/subtracts arithmetical unit 14, floating number multiplication device 15 and the operation result output terminal of floating number division operation device 16 with floating number and is connected; Output terminal is connected with the input end of result register 13; Gating control input end be connected with the output terminal of door V 20;

The latch signal input end of described result register 13 be connected with the output terminal of door VI 21, output terminal is connected with operand 1 input end that floating number adds/subtract arithmetical unit 14, floating number multiplication device 15, operand interchanger 17, is also connected with the input end of 32 triple gate groups 19;

Described floating number adds/subtract operand 2 input ends of arithmetical unit 14 and the operand output terminal DB_2 of operand store II is connected, the operational symbol output terminal of operational symbol input end AND operator shift register 5 connects, and operation result output terminal is also connected with the operation result input end of computing abnormality mark control 18;

Operand 2 input ends of described floating number multiplication device 15 and the operand output terminal DB_2 of operand store II are connected, the operational symbol output terminal of operational symbol input end AND operator shift register 5 connects, and operation result output terminal is also connected with the operation result input end of computing abnormality mark control 18;

The operand a of described floating number division operation device 16 is connected with two output terminals of operand interchanger 17 respectively with operand b input end; Operation result output terminal is also connected with the operation result input end of computing abnormality mark control 18;

Operand 2 input ends of described operand interchanger 17 and the operand output terminal DB_2 of operand store II are connected, exchange control end and or the output terminal of I 22 be connected;

Latch result pulse 5. _ 2 output terminals that the latch signal input end of described computing abnormality mark control 18 is counted pulse generation control module 8 with read operation are connected; IRQ output terminal is with another input end with door I 6, is connected with another input end of door III 10, and IRQ output terminal is also exported interrupt request singal IRQ to system; When middle operation result or final operation result occur when abnormal, described computing abnormality mark is controlled 18 and is sent interrupt request singal IRQ to system, and reset write operand pulse generation control module 3 and read operation count pulse generation control module 8, cease and desist order word and operand are write the work that time-sequence control module I and operand are read time-sequence control module III;

The output terminal of described 32 triple gate groups 19 is connected with system data bus DB, control input end with or door II 23 output terminal be connected;

Described with door V 20 two input ends count the pulse 1. _ 2 of pulse generation control module 8, the output terminal of pulse 2. _ 2 is connected with read operation respectively;

Described with door VI 21 two input ends count the pulse 2. _ 2 of pulse generation control module 8, the output terminal of pulse 5. _ 2 is connected with read operation respectively;

The output terminal that two input ends described or door I 22 are counted the pulse 6. _ 2 of pulse generation control module 8 with mode output terminal, the read operation of mode type register 4 is respectively connected;

Two input ends described or door II 23 are connected with CS signal output part, the system read signal RD line of controller identification 1 respectively; When CS is " 0 ", under the effect of system RD signal, read the final operation result of intermediate operations result or command execution.

As shown in Figure 2, Figure 3, Figure 4, the type of described mode type register 4 outputs refers to the type of the 1st operand of reading from operand store II, the mode of output refers to when type is " 0 ", the 1st operand participated in the processing mode of division arithmetic, and the operational symbol of operational symbol shift register 5 outputs is symbols that operand participates in computing;

Type is identified by unitary code:

2. _ 2 types in 4 outputs of mode type register of pulse 1. _ 2, pulse that pulse generation control module 8 output is counted in described read operation produce during for " 1 "; When pulse 1. _ 2 or pulse 2. _ 2 are " 0 ", the gating control input end of gate 12 is " 0 ", the 1st operand that gate 12 outputs are read from operand store II; When pulse 1. _ 2 and pulse 2. _ 2 are all " 1 ", gate 12 output operation results;

The 1st operand reading from operand store II participated in division arithmetic, and mode and type signal are just controlled the division mode at exectorial the 1st operand and operation result:

When mode is " 0 ", when type is " 0 ": what result register 13 was exported is operation result, operand 1 input end of operand interchanger 17 is operation result, 1st operand of operand 2 input ends of operand interchanger 17 for reading from operand store II, when reading the 1st operand, now pulse 6. _ 2 is that " 0 " is effective, because mode is " 0 " state, the control end that makes operand interchanger 17 is " 0 ", the operation result of operand 1 input end of operand interchanger 17 is as the operand b of operand interchanger 17 outputs, the operand of operand interchanger 17, the 1st operand of 2 input ends is as the operand a of operand interchanger 17 outputs, 2 inputs and 2 outputs that are operand interchanger 17 exchange transmission, the 1st operand is as the operand a of floating number division operation device 16, operation result is as operand b, carry out the division arithmetic of the 1st operand/operation result,

When mode is " 1 ", type is when " 0 ": when reading the 1st operand, although pulse 6. _ 2 be " 0 " effectively, mode is one state, making the control end of operand interchanger 17 is " 1 ", and 2 inputs of operand interchanger 17 and 2 outputs do not exchange transmission; Operation result is as the operand a of floating number division operation device 16, and the 1st operand, as operand b, carried out the division arithmetic of operation result/1st operand;

When type is " 1 ": pulse generation control module 8 is counted in read operation can not produce pulse 6. _ 2 signals, pulse 6. _ 2 output terminals are one state, making the control end of operand interchanger 17 is " 1 ", and 2 inputs of operand interchanger 17 and 2 outputs do not exchange transmission; The mode status signal of the 1st operand and input is irrelevant, and the 1st operand is as the operand a of floating number division operation device 16, and the 2nd operand, as operand b, carried out the division arithmetic of the 1st operand/2nd operand.

Embodiment bis-:

Many floating-point operations number adds/subtracts, multiplication controller;

Embodiment bis-is a kind of mapped structures of the embodiment of the present invention one, and this many floating-point operations number adds/subtracts, the basic structure of multiplication controller is with embodiment mono-; Institute's difference is: the mode output terminal that this many floating-point operations number adds/subtracts, multiplication controller is cancelled the mode type register 4 of embodiment mono-Fig. 2; Cancel the read operation of embodiment mono-Fig. 3 and count pulse 6. _ 2 output terminals of pulse generation control module 8; Cancel the squiggle of the pulse 6. _ 2 of embodiment mono-Fig. 6; Cancel embodiment mono-Fig. 4 floating number division operation device 16, operand interchanger 17 and or door I 22 and connecting line thereof, embodiment mono-Fig. 4 is converted to embodiment bis-Fig. 8.

Claims

Floating-point operation number more than one kind add/subtract, multiplication and division arithmetic and control unit, for realizing, a plurality of 32 floating numbers that meet IEEE754 standard add/subtract, the hybrid operation of multiplication and division, it is characterized in that: this controller comprises that command word and operand write time-sequence control module (I), operand store (II), operand and read time-sequence control module (III), operand configuration and s operation control module (IV);

Described command word and operand are write time-sequence control module (I) and operand store (II), operand and are read time-sequence control module (III), operand configuration and s operation control module (IV) and be connected;

Described operand store (II) is also read time-sequence control module (III), operand configuration and s operation control module (IV) with operand and is connected;

Described operand is read time-sequence control module (III) and is also connected with operand configuration and s operation control module (IV);

Described command word and operand are write time-sequence control module (I) and have been controlled writing and storing of instruction, need to take system bus; Article one, instruction comprises 32 order of the bit words and several operands, and operand mostly is 13 most; When described command word and operand are write time-sequence control module (I) and chosen by system, startup command word and operand are write time-sequence control module (I) work, inner produce synchronize with system WR signal write time sequential pulse sequence; Under the control of writing time sequential pulse, latch that many floating-point operations number adds/subtracts, the command word of multiplication and division operational order, write many floating-point operations number of instruction and stored; Last floating-point operation number is written into after storage, and described command word and operand are write time-sequence control module (I) and quit work;

Described operand store (II) is dual-ported memory, write port, and read port, for storing floating-point operation number (under be called operand); There is not the situation that needs arbitration in write and the reading of read port operand of the write port operand of described operand store (II); Write port is subject to command word and operand to write time-sequence control module (I) control, and the operand write operation of system data bus DB transmission is counted to storer (II); Read port is subject to operand to read time-sequence control module (III) control, and operand is read and is transferred to operand configuration and s operation control module (IV);

Described operand is read time-sequence control module (III) and in inside, is read under the control of time sequential pulse, independently completes floating-point operation number reading from operand store (II), does not need to take system bus; Described operand is read time-sequence control module (III) and is write after time-sequence control module (I) writes the 1st operand and be activated work at command word and operand, output busy signal Busy is by " 1 " → " 0 ", and according to the 1st operand type, inner produce synchronize with system clock Clock signal read time sequential pulse sequence, in order operand is read to participation computing, and automatically adjusted execution cycle according to the operational symbol of each operand; After last 1 operand of participation computing is read, then through an execution cycle, output busy signal Busy, by " 0 " → " 1 ", sends after the result latch pulse of a clock period Clock, and shut-down operation number is read the work of time-sequence control module (III);

The operational symbol that the configuration of described operand and s operation control module (IV) are write time-sequence control module (I) output according to command word and operand selects the corresponding arithmetical unit of each operand to calculate, and according to the type gating configuration of the 1st operand of output, participates in adding/subtract or operand 1 and the operand 2 of multiplying; When the 1st operand is division arithmetic, also need to participate according to the 1st operand division arithmetic mode gating configuration operand a and the operand b of division arithmetic; Described operand configuration and s operation control module (IV) can latch the result of calculation of each computing, and judge that whether result of calculation is abnormal; System can be read the final operation result of intermediate operations result and command execution from operand configuration and s operation control module (IV).
2. many floating-point operations number as claimed in claim 1 adds/subtracts, multiplication and division arithmetic and control unit, it is characterized in that: described command word and operand write time-sequence control module (I) comprise controller identification (1), write address counter (2), write operation count pulse generation control module (3), mode type register (4), operational symbol shift register (5) and with door I (6);

The input end of described controller identification (1) withthe A31 of system address bus AB connects to A27 line, and CS signal output part is connected with the enabling signal input end that write operation is counted pulse generation control module (3), is also connected with operand configuration and s operation control module (IV); Described controller identification (1) input A31 identifies to the address value of A27 and controller the address value that (1) set and equates, to identify the CS signal output part of (1) be " 0 " to controller, otherwise CS signal output part is " 1 ";

The operand number input end of described write address counter (2) is connected to D0 line with the D3 of system data bus DB, writing pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module (3) with write operation is connected, writing pulse 3. _ 1 output terminal that count pulse input end counts pulse generation control module (3) with write operation is connected, write address output terminal is connected with the write address input end AB_1 of operand store (II), writes to overflow output terminal and be connected with an input end of door I (6);

Described write address counter (2) is in fact one and subtracts 1 counter, the D3 of system DB is that participation adds/subtracts, an operand numerical value of multiplication and division computing to D0 transmission, operand number that will input instruction under the control of writing presetting pulse is as 4 write address initial values of counting initial value and operand store (II), and juxtaposition writes that to overflow output terminal be one state; Often come one to write count pulse, write address value-1 of write address counter (2) output, retouching operation is counted storer (II) write port memory unit address value, until count value output terminal is " 0 ", be that AB_1 is " 0 ", now write spill over by " 1 " → " 0 ", writing spill over is the sign that operand ablation process finishes;

The clock terminal that described write operation is counted pulse generation control module (3) is connected with system write signal WR line, the RESET input be connected with the output terminal of door I (6), pulse 1. _ 1 output terminal also with the latch signal input end of mode type register (4), latch signal input end, the operand of operational symbol shift register (5) are read time-sequence control module (III) is connected, pulse 2. _ 1 output terminal is read time-sequence control module (III) with WR_1 input end, the operand of operand store (II) write port and is connected;

When CS is " 0 ", described write operation is counted pulse generation control module (3) startup work under the effect of the 1st WR signal of system, export in order pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, until reset signal input end is just quit work by " 1 " → " 0 ", putting pulse 1. _ 1, pulse 2. _ 1 and pulse 3. _ 1 output terminal is one state;

The input end of described mode type register (4) is connected with D4 line with the D5 of system data bus DB, and class type output terminal is read time-sequence control module (III) with operand and is connected, and mode output terminal is connected with operand configuration and s operation control module (IV); Described mode type register (4) is under the effect of pulse 1. _ 1 negative edge, by the status lock existing way type register (4) of the mode of the 1st operand and type;

The input end of described operational symbol shift register (5) is connected to D6 line with the D31 of system data bus DB, shift pulse input end is read time-sequence control module (III) with operand and is connected, and operational symbol output terminal is read time-sequence control module (III) with operand and is connected with operand configuration and s operation control module (IV);

Describedly be connected with the configuration of systematic reset signal Rst line, operand and s operation control module (IV) respectively with another two input ends of door I (6).
3. many floating-point operations number as claimed in claim 1 adds/subtracts, multiplication and division arithmetic and control unit, it is characterized in that: described operand read time-sequence control module (III) comprise read address counter (7), read operation count pulse generation control module (8), with door an II (9), with door III (10) and with door IV (11);

The operand number input end of described read address counter (7) and the D3 of system data bus DB are connected to D0 line, reading pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module (3) with write operation is connected, read count pulse input end and be connected with the output terminal of door IV (11), read address output end and be connected with the address input end AB_2 that reads of operand store (II), read to overflow output terminal and read operation count pulse generation control module (8) read overflow input end and be connected;

Described read address counter (7) is in fact one and subtracts 1 counter, operand number using the D3 from system data bus DB to D0 under the effect of reading presetting pulse is read address initial value as counting initial value and operand store (II) read port, and it is one state that juxtaposition reads to overflow output end signal; Often come one to read count pulse, read address counter (7) output read address value-1, retouching operation is counted storer (II) read port memory unit address value, until be " 0 ", read spill over by " 1 " → " 0 ", representing just at exectorial last operand, to read, is also the out-of-work sign of read address counter (7);

The clock terminal that pulse generation control module (8) is counted in described read operation is connected with system clock Clock line, the RESET input be connected with the output terminal of door III (10), reading to start pulse 2. _ 1 output terminal that input end counts pulse generation control module (3) with write operation is connected, type input end is connected with the class type output terminal of mode type register (4), and the operational symbol output terminal of operational symbol input end AND operator shift register (5) connects; Pulse 1. _ 2 output terminals are connected with an input end, operand configuration and s operation control module (IV) with door II (9); Pulse 2. _ 2 output terminals are connected with an input end, operand configuration and s operation control module (IV) with door IV (11); Pulse 3. _ 2 output terminals be connected with another input end of door II (9); Pulse 4. _ 2 output terminals be connected with another input end of door IV (11); Pulse 5. _ 2 is connected with operand configuration and s operation control module (IV) with pulse 6. _ 2 output terminals; Busy output terminal is to system output Busy busy signal;

The pulse that pulse generation control module (8) output is counted in described read operation is synchronizeed with system clock Clock, according to type input signal, be " 0 " or be " 1 ", determines that control operation counts the pulse train of the middle read operation number of storer (II); Read to start input end by " 1 " → " 0 ", Busy output terminal, by " 1 " → " 0 " state, starts the work that pulse generation control module (8) are counted in read operation; When read address counter (7) output read spill over by " 1 " → " 0 " time, put pulse 4. _ 2 output terminals for " 1 ", read operation is counted pulse generation control module (8) through an execution cycle time, send latch result pulse 5. _ 2 controls in a system clock Clock cycle and latch operation result, output busy signal Busy is by " 0 " → " 1 ", stop read operation and count the work of pulse generation control module (8), putting all pulse output ends is one state; When the reset signal of input is " 0 ", pulse generation control module (8) is counted in reset read operation, and putting all pulse output ends is one state, and Busy output terminal is one state;

Described read operation is counted pulse generation control module (8) and is participated in the operand operational symbol of computing according to each, automatically adjusts the execution cycle time of corresponding each operand;

Described with door II (9) an output terminal be connected with the read signal input end RD_2 of operand store (II), the shift pulse input end of operational symbol shift register (5); From operand store (II), read an operand, the operational symbol data in operational symbol shift register (5) move right two, make each operand AND operator that participates in computing corresponding one by one;

Describedly be connected with the configuration of systematic reset signal Rst line, operand and s operation control module (IV) respectively with two input ends of door III (10).
4. many floating-point operations number as claimed in claim 1 adds/subtracts, multiplication and division arithmetic and control unit, it is characterized in that: the configuration of described operand and s operation control module (IV) comprise gate (12), result register (13), floating number add/subtract arithmetical unit (14), floating number multiplication device (15), floating number division operation device (16), operand interchanger (17), computing abnormality mark control (18), 32 triple gate groups (19), with a door V (20), with door VI (21) or door I (22) and or an II (23);

An input end of described gate (12) is connected with the operand output terminal DB_2 of operand store (II), and another input end adds/subtracts arithmetical unit (14), floating number multiplication device (15) and the operation result output terminal of floating number division operation device (16) with floating number and is connected; Output terminal is connected with the input end of result register (13); Gating control input end be connected with the output terminal of door V (20);

The latch signal input end of described result register (13) be connected with the output terminal of door VI (21), output terminal is connected with operand 1 input end that floating number adds/subtract arithmetical unit (14), floating number multiplication device (15), operand interchanger (17), is also connected with the input end of 32 triple gate groups (19);

Described floating number adds/subtract operand 2 input ends of arithmetical unit (14) and the operand output terminal DB_2 of operand store (II) is connected, the operational symbol output terminal of operational symbol input end AND operator shift register (5) connects, and operation result output terminal is also connected with the operation result input end of computing abnormality mark control (18);

Operand 2 input ends of described floating number multiplication device (15) are connected with the operand output terminal DB_2 of operand store (II), the operational symbol output terminal of operational symbol input end AND operator shift register (5) connects, and operation result output terminal is also connected with the operation result input end of computing abnormality mark control (18);

The operand a of described floating number division operation device (16) is connected with two output terminals of operand interchanger (17) respectively with operand b input end; Operation result output terminal is also connected with the operation result input end of computing abnormality mark control (18);

Operand 2 input ends of described operand interchanger (17) are connected with the operand output terminal DB_2 of operand store (II), exchange control end and or the output terminal of I (22) be connected;

Latch result pulse 5. _ 2 output terminals that the latch signal input end of described computing abnormality mark control (18) is counted pulse generation control module (8) with read operation are connected; IRQ output terminal is with another input end with door I (6), is connected with another input end of door III (10), and IRQ output terminal is also exported interrupt request singal IRQ to system; When middle operation result or final operation result occur when abnormal, described computing abnormality mark is controlled (18) and is sent interrupt request singal IRQ to system, and reset write operand pulse generation control module (3) and read operation count pulse generation control module (8), cease and desist order word and operand are write the work that time-sequence control module (I) and operand are read time-sequence control module (III);

The output terminal of described 32 triple gate groups (19) is connected with system data bus DB, control input end with or door II (23) output terminal be connected;

Described with door V (20) two input ends count the pulse 1. _ 2 of pulse generation control module (8), the output terminal of pulse 2. _ 2 is connected with read operation respectively;

Described with door VI (21) two input ends count the pulse 2. _ 2 of pulse generation control module (8), the output terminal of pulse 5. _ 2 is connected with read operation respectively;

The output terminal that two input ends described or door I (22) are counted the pulse 6. _ 2 of pulse generation control module (8) with mode output terminal, the read operation of mode type register (4) is respectively connected;

Two input ends described or door II (23) are connected with CS signal output part, the system read signal RD line of controller identification (1) respectively; When CS is " 0 ", under the effect of system RD signal, read the final operation result of intermediate operations result or command execution.
5. many floating-point operations number as claimed in claim 1 adds/subtracts, multiplication and division arithmetic and control unit, it is characterized in that: the type of described mode type register (4) output refers to the type of the 1st operand of reading from operand store (II), the mode of output refers to when type is " 0 ", the 1st operand participated in the processing mode of division arithmetic, and the operational symbol of operational symbol shift register (5) output is the symbol that operand participates in computing;

Operational symbol is comprised of two marking codes: 00: additive operation; 01: subtraction; 10: multiplying; 11: division arithmetic;

Operand type is comprised of unitary code sign: 0: operand type 0; 1: operand type 1;

When reading that the 1st operand participates in adding/subtracting or during multiplying, type signal is controlled the compute mode of the 1st operand;

0: the 1 operand of operand type is as participating in adding/subtract or the operand 2 of multiplying, and operation result, as operand 1, is carried out operation result and the 1st operand computing;

1: the 1 operand of operand type as participating in adding/subtract, 1, the 2 operand of operand of multiplying is as operand 2, carries out the computing of the 1st operand/2nd operand;

2. _ 2 types in mode type register (4) output of pulse 1. _ 2, pulse that pulse generation control module (8) output is counted in described read operation produce during for " 1 "; When pulse 1. _ 2 or pulse 2. _ 2 are " 0 ", the gating control input end of gate (12) is " 0 ", the 1st operand that gate (12) output is read from operand store (II); When pulse 1. _ 2 and pulse 2. _ 2 are all " 1 ", gate (12) output operation result;

When reading the 1st operand participation division arithmetic, mode and type signal are controlled the division mode of the 1st operand, operation result:

When mode is " 0 ", when operand type is " 0 ": what result register (13) was exported is operation result, operand 1 input end of operand interchanger (17) is operation result, 1st operand of operand 2 input ends of operand interchanger (17) for reading from operand store (II), when reading the 1st operand, pulse 6. _ 2 is that " 0 " is effective, because mode is " 0 " state, the control end that makes operand interchanger (17) is " 0 ", the operation result of operand 1 input end of operand interchanger (17) is as the operand b of operand interchanger (17) output, the 1st operand of operand 2 input ends of operand interchanger (17) is as the operand a of operand interchanger (17) output, 2 inputs and 2 outputs that are operand interchanger (17) exchange transmission, the 1st operand is as the operand a of floating number division operation device (16), operation result is as operand b, carry out the division arithmetic of the 1st operand/operation result,

When mode is " 1 ", when operand type is " 0 ": pulse 6. _ 2 is that " 0 " is effective, but mode is one state, making the control end of operand interchanger (17) is " 1 ", and 2 inputs of operand interchanger (17) and 2 outputs do not exchange transmission; Operation result is as the operand a of floating number division operation device (16), and the 1st operand, as operand b, carried out the division arithmetic of operation result/1st operand;

When operand type is " 1 ": the configuration of the 1st operand and the mode signal condition of input are irrelevant, pulse generation control module (8) is counted in read operation can not produce pulse 6. _ 2 signals, pulse 6. _ 2 output terminals are one state, making the control end of operand interchanger (17) is " 1 ", and 2 inputs of operand interchanger (17) and 2 outputs do not exchange transmission; The mode status signal of the 1st operand and input is irrelevant, and the 1st operand is as the operand a of floating number division operation device (16), and the 2nd operand, as operand b, carried out the division arithmetic of the 1st operand/2nd operand.