CN103579183A - Interposer system and method - Google Patents

Interposer system and method Download PDF

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Publication number
CN103579183A
CN103579183A CN201210592167.2A CN201210592167A CN103579183A CN 103579183 A CN103579183 A CN 103579183A CN 201210592167 A CN201210592167 A CN 201210592167A CN 103579183 A CN103579183 A CN 103579183A
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area
intermediary layer
region
semiconductor element
circuit
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CN201210592167.2A
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CN103579183B (en
Inventor
余振华
郑心圃
侯上勇
叶德强
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.

Description

Intermediary layer system and method
Technical field
Relate generally to technical field of semiconductors of the present invention, more specifically, relates to semiconductor device and manufacture method thereof.
Background technology
Semiconductor device is for various electronic application (such as personal computer, mobile phone, digital camera and other electronic equipments etc.).Semiconductor industry improves the integration density of various electronic units (for example, transistor, diode, resistor, capacitor etc.) continuously by the size of continuous minimizing minimal parts, thereby allows more component integration in appointed area.Because the shared volume of integrated component is to be positioned on the surface of semiconductor crystal wafer substantially, therefore, in fact to improve be substantially all two dimension (2D) for these integrated levels.Although significantly improving aspect photoetching caused that 2D integrated circuit structure significantly improves, also there is the physical limitation of the density aspect that can realize with two dimension.One in these limitation is to manufacture the minimum dimension that these parts need.And, when more device is placed in a chip, need more complicated design.Another limitation comes from along with the quantity of the cross tie part between the increase device of number of devices and length also significantly increase.When the quantity of cross tie part and length increase, circuit RC postpones and power consumption all can increase.
Therefore, in some applications, by diversion to than before packaging part use on the less packaging part of small size more.A kind of less packaging part of having developed is three-dimensional (3D) IC, and wherein, two tube cores or IC are bonded together, and electrical connector is used the contact pad on intermediary layer to be formed between each tube core.
In these cases, power line and holding wire can pass intermediary layer.These lines can be tube core from a side of intermediary layer to intermediary layer opposite side or the connector of other electrical connectors.
Summary of the invention
In order to solve existing defect in prior art, according to an aspect of the present invention, provide a kind of semiconductor device, comprising: intermediary layer, there is the first side and the second side, described intermediary layer comprises: first area, comprises the first circuit; Second area, comprises second circuit; With the 3rd region, between described first area and described second area, described the 3rd region does not have circuit and extends to described the second side from described the first side; And conductive path, between described first area and described second area, described conductive path extends above described the 3rd region.
In this semiconductor device, described the 3rd region is the scribe area between described first area and described second area.
In this semiconductor device, described the 3rd region comprises sealant.
In this semiconductor device, described conductive path is a part for the first semiconductor element.
This semiconductor device further comprises the second semiconductor element that is attached to described first area.
In this semiconductor device, described the first circuit and described second circuit have different patterns.
In this semiconductor device, described the first circuit is identical with described second circuit.
According to a further aspect in the invention, provide a kind of semiconductor device, having comprised: intermediary layer, has had between second area and the 3rd region and there is no the first area of functional circuit; The first contact, is arranged in described second area; The second contact, is arranged in described the 3rd region; And conductive path, above described first area, extending, described conductive path is electrically connected to described the first contact and described the second contact.
In this semiconductor device, described conductive path is a part that is positioned at the first semiconductor element of top, described first area.
This semiconductor device further comprises the second semiconductor element that is positioned at described second area top.
In this semiconductor device, described conductive path comprises cross tie part after the passivation that is positioned at top, described first area.
This semiconductor device further comprises the first semiconductor element contacting with cross tie part after described passivation.
This semiconductor device further comprises the sealing ring between described second area and described first area.
This semiconductor device further comprises the substrate through vias that extends through described second area.
According to another aspect of the invention, a kind of method of manufacturing semiconductor device is provided, described method comprises: use photoetching process in the first area of wafer, to form the first circuit, form second circuit in the second area of described wafer and form scribe area between described first area and described second area, wherein, described photoetching process is used and is had the patterned exposure energy of first size and the described first area of described wafer has described first size; The in the situation that of not separated described first area and described second area, by described first area and described second area and described wafer separate; And above described scribe area, described the first circuit is connected to described second circuit.
In the method, describedly by photoetching process, by making described scribe area not be exposed to described patterned exposure energy, form described scribe area.
In the method, described the first circuit being connected to described second circuit further comprises described the first circuit and described second circuit is connected to the semiconductor element that is positioned at described scribe area top.
In the method, described the first circuit being connected to described second circuit is further included in described scribe area top and forms cross tie part after passivation.
In the method, described the first circuit comprises substrate through vias.
The method is further included between described scribe area and described first area and forms sealing ring.
Accompanying drawing explanation
For more complete, understand the present embodiment and advantage thereof, the following description of now carrying out in connection with accompanying drawing as a reference, wherein,
Fig. 1 illustrates according to the first intermediary layer (interposer) region of embodiment and the second intermediary layer region;
Fig. 2 illustrates separated according to the first intermediary layer region of embodiment and the second intermediary layer region;
Fig. 3 A to Fig. 3 D illustrates the connection in the first semiconductor element, the second semiconductor element and the 3rd semiconductor element to the first intermediary layer region and the second intermediary layer region according to embodiment;
Fig. 4 illustrates according to the formation of cross tie part after the passivation in connection the first intermediary layer region of embodiment and the second intermediary layer region;
Fig. 5 illustrates the first semiconductor element, the second semiconductor element and the 3rd semiconductor element according to embodiment to the connection of cross tie part after passivation;
Fig. 6 illustrates the separation from the second intermediary layer region according to the first intermediary layer region of embodiment;
Fig. 7 illustrates according to the encapsulation in the region between the first intermediary layer region of embodiment and the second intermediary layer region; And
Fig. 8 illustrates the connection in the first semiconductor element, the second semiconductor element and the 3rd semiconductor element to the first intermediary layer region and the second intermediary layer region according to embodiment.
Except as otherwise noted, corresponding label and symbol otherwise in different accompanying drawing are commonly referred to as corresponding component.Drawing accompanying drawing needn't draw in proportion to be clearly shown that the related fields of embodiment.
Embodiment
Below, discuss manufacture and the use of the embodiment of the present invention in detail.Yet, should be appreciated that, the invention provides many applicable creative concepts that can realize in various specific environments.The specific embodiment of discussing only shows the concrete mode of manufacturing and using disclosed theme, and is not used in the scope of the different embodiment of restriction.
With reference to the concrete context intermediary layer of semiconductor chip (that is, for), embodiment is described.Yet, also other embodiment can be applied on the interface unit of other types.
With reference now to Fig. 1,, show intermediary layer wafer 100, this wafer has substrate 101, the first intermediary layer region 103, the second intermediary layer region 105, the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111.For example, for the substrate 101 of intermediary layer wafer 100, can be silicon substrate, doping or active layer plain or silicon-on-insulator (SOI) substrate, for providing support for intermediary layer wafer 100.Yet alternatively, substrate 101 can be that glass substrate, ceramic substrate, polymer substrate maybe can provide suitable protection and/or any other substrate of interconnect function.Alternatively, these and any other suitable material all can be for substrate 101.
Substrate 101 can be divided into the first intermediary layer region 103 and the second intermediary layer region 105.The first intermediary layer region 103 and the second intermediary layer region 105 are designed to be connected to semiconductor element, such as, processor and internal memory tube core are (not shown in Fig. 1, but below in conjunction with Fig. 3 A, illustrate and describe), and be designed to, once the first intermediary layer region 103 is separated from intermediary layer wafer 100 with the second intermediary layer region 105, provide support and the connection of semiconductor element.
The first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 be positioned at each intermediary layer region on intermediary layer wafer 100 (such as, the first intermediary layer region 103 as shown in Figure 1 and the second intermediary layer region 105) between and separate each intermediary layer is interregional.In one embodiment, the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 are the regions that are not formed with therein the intermediary layer wafer 100 of source circuit, or the region of the circuit not being used after intermediary layer wafer 100 forms.Similarly, while removing the first intermediary layer region 103 and the second intermediary layer region 105 on expecting therefrom interlayer wafer 100, in order not damage the circuit in the first intermediary layer region 103 and the second intermediary layer region 105, the first scribe area 107 and the 3rd scribe area 111 can be used as to the region that will remove.
In one embodiment, the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 form during the miscellaneous part on interlayer wafer 100 in the mill, and can have the first width w of between about 60 μ m and about 160 μ m (such as about 80 μ m) 1.For example, in an embodiment as herein described, the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 can form with together with the formation of substrate through vias (TSV) 113, the first metal layer 115, the first contact pad 117.The first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 can form with these structures that the following describes and other structures simultaneously.
Use particular instance, the part of the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 can form during manufacturing the first metal layer 115, for example, the first metal layer 115 can be used a series of mask and etch process, wherein, can apply many photoresists (for example the first photoresist (not illustrating separately)) in Fig. 1, and these photoresists are developed to come with the mask that acts on the layer below patterning.The first photoresist can be such as deep ultraviolet (DUV) photoresist, and can be by depositing the first photoresist with spin coating proceeding the first photoresist is placed to correct position in manufacturing process on intermediary layer wafer 100.
Once place the first photoresist, the first photoresist just can be exposed to the open air the energy (representing by being labeled as 106 arrow in Fig. 1) to for example light through patterning reticle mask (not illustrating separately in Fig. 1), to form, will affect the graticule region (reticule field) 108 of the first photoresist, thereby expose to the open air in those parts to energy and induce reaction at the first photoresist.Due to graticule region 108 (its second width w 2for example, between about 13mm and about 64mm (about 32mm), and its length (not shown in figure 1) is (for example about 26mm) between about 13mm and about 52mm) not even as big as cover intermediary layer wafer 100 in single exposure, therefore, a part by agency layer crystal circle 100 (for example, the first intermediary layer region 103) expose and another part (for example, the second intermediary layer region 105) of then moving to intermediary layer wafer 100 with the expose various piece of intermediary layer wafer 100 of mode progressively.By this way, can be by progressively moving and every part of the intermediary layer wafer 100 that exposes is carried out patterning intermediary layer wafer 100.
Use progressively exposure system, can to first area (for example pass through, the first intermediary layer region 103) expose and for example follow, with from first area transverse shifting one distance to next-door neighbour's second area (, the second intermediary layer region 105) expose, thereby leave unexposed area between the first intermediary layer region 103 and the second intermediary layer region 105, form the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111.Because the unexposed area between the first intermediary layer region 103 and the second intermediary layer region 105 does not carry out any processing, so this unexposed area will become the second scribe area 109, thereby make the second scribe area 109 without any functional circuit.Can form with similar step mode the first scribe area 107 and the 3rd scribe area 111.
Yet the progressively non-exposure of intermediary layer wafer 100 is not the unique method that can form the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111.For example, the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 can (for example be close to intermediary layer region accordingly with their, the first intermediary layer region 103 or the second intermediary layer region 105) be exposed together, but this exposure can make the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 there is no functional circuit.Alternatively, the embodiment that test circuit or other structures is placed in to the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 in expectation (still, once the first intermediary layer region 103 is separated from intermediary layer wafer 100 with the second intermediary layer region 105, just do not adopt this embodiment), can come patterning the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 by these structures.
In addition, identical patterns graticule in identical orientation can be used in each step of exposure, thereby form similar graticule region 108 for example, in every part (, the first intermediary layer region 103 and the second intermediary layer region 105) of intermediary layer wafer 100 upper with identical topology formation symmetrical structure.In another embodiment, if needed, can for example, with different directed (Rotate 180s °) identical patterns graticule be used for to different piece.By using by the graticule of identical patterns, make whole technique more cheaply and more effective.Yet, in other embodiments, can will for each, be exposed by the graticule of different pattern.By being formed for the combination of intermediary layer wafer 100, expose, can be at the interior formation of intermediary layer wafer 100 pattern more in detail more specifically.
As can be for above intermediary layer wafer 100 and the inner example that forms structure and be also used to form the manufacturing process of the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111, can form the substrate through vias (TSV) 113 through substrate 101, the first metal layer 115 and the first contact pad 117 can be above the first side of substrate 101, formed, the second metal layer 119 and the second contact pad 121 can be above the second side of substrate 101, formed.Can form the first joint outer part 123 in the mode contacting with the second contact pad 121, to help to provide electrical connection.Each in these structures will be discussed in more detail in following paragraph.
Can for example, by the suitable photoresist of application (, the first photoresist described above, not shown) and develop, then etch substrate 101, to generate TSV opening (as described below, to fill after a while), forms TSV 113.The opening for TSV in this stage can form to extend into substrate 101 to the degree of depth that is at least greater than the final Desired Height of finished product intermediary layer wafer 100.Therefore, although this degree of depth depends on the global design of intermediary layer wafer 100, this degree of depth can be in the lower face of substrate 101 between about 1 μ m and about 700 μ m, and wherein, preferred depth is about 50 μ m.The diameter that is used for the opening of TSV 113 can form between about 1 μ m and about 100 μ m, such as about 6 μ m.
For example, once form the opening of TSV 113, just can fill with barrier layer and electric conducting material the opening of TSV 113.Barrier layer can comprise the electric conducting material such as titanium nitride, but also can use alternatively other materials, such as tantalum nitride, titanium, dielectric etc.Can use such as, the CVD technique of PECVD forms this barrier layer.Yet, alternatively, can use other optional technique, such as, sputter or Organometallic Chemistry gas deposition (MOVCD).Can form this barrier layer to delineate the profile of shape below of the opening of TSV 113.
Electric conducting material can comprise copper, but can use alternatively other suitable materials, such as aluminium, alloy, doped polycrystalline silicon, their combination etc.Can pass through deposit seed, the opening that then electro-coppering on this crystal seed layer, filling and mistake are filled TSV 113 forms electric conducting material.Once fill the opening of TSV113, just can pass through grinding technics (such as, chemico-mechanical polishing (CMP)) removal and be positioned at the unnecessary barrier layer of TSV 113 opening outsides and unnecessary electric conducting material, still can use any suitable removal technique.
Once electric conducting material is positioned at TSV 113 openings, just can implement the second side of attenuate substrate 101, to expose TSV 113 openings and to form TSV113 by extending through the electric conducting material system of substrate 101.In one embodiment, the second side of attenuate substrate 101 can leave TSV 113.Can be by implement the attenuate of the second side of substrate 101 such as CMP or etched flatening process.
Yet as known to those skilled in the art, the technique of the above-mentioned TSV of being used to form 113 is only a kind of method that forms TSV 113, and additive method is also intended to be included in the scope of the present embodiment completely.For example, also can use form TSV 113 opening, with dielectric material, fill the opening of TSV113, the second side of attenuate substrate 101 exposes dielectric material, removes dielectric material and with the opening of conductor filled TSV 113.For the method and every other suitable method at the interior formation of substrate 101 TSV 113, be intended to be included in the scope of the present embodiment completely.
Alternatively, TSV 113 can form the multilayer that extends through the intermediary layer wafer 100 that is positioned at substrate 101 tops, such as the first metal layer 115 (further describing below).For example, can after forming the first metal layer 115 or even partly, form TSV113 with metal layer 115 simultaneously.For example, can in single processing step, form the opening through the TSV 113 of the first metal layer 115 and substrate 101.Alternatively, can be before forming the first metal layer 115, in substrate 101, form TSV 113 opening a part and fill, and, formation is the same separately with each first metal layer 115, can form and fill TSV 113 openings of subsequent layer.The technique any and that any other is suitable that can form in these techniques of TSV 113 is all intended to be included in the scope of the present embodiment completely.
The first metal layer 115 is formed on the first side top of substrate 101, and be designed to the first side of substrate 101 (for example to interconnect to external devices in substrate 101 second sides, the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305, it is shown in Figure 1 but below in conjunction with Fig. 3 A, illustrate and be described).Although Fig. 1 illustrates the individual layer of dielectric and cross tie part, but the first metal layer 115 is formed by the alternating layer of dielectric and electric conducting material, and can by any suitable technique (such as, deposit, inlay, dual damascene etc.) form the first metal layer 115.In one embodiment, can there is one or more metal layers, but the accurate quantity in the first metal layer 115 middle levels depends on the design of intermediary layer wafer 100 at least partly.
The first contact pad 117 can be formed on the first metal layer 115 tops and electrically contact with the first metal layer 115.The first contact pad 117 can comprise aluminium, but also can use alternatively other materials, such as copper.Can use such as the depositing operation of sputter form material layer (not shown) then can by suitable technique (such as, mask and etching) part of removal material layer forms the first contact pad 117 and forms the first contact pad 117.Yet, also can any other suitable technique form the first contact pad 117, such as form opening in dielectric, deposition is for the material of the first contact pad 117, then this material of planarization and dielectric.The thickness of the first contact pad 117 can form between approximately 0.5 μ m and approximately 4 μ m, all 1.45 μ m according to appointment.
The second metal layer 119 is formed on the second side top of substrate 101 and is designed to the second side of substrate 101 to interconnect to external contact part.Although Fig. 1 is depicted as the individual layer of dielectric and cross tie part, but the second metal layer 119 can be formed by the alternating layer of dielectric and electric conducting material, and can form the second metal layer 119 by any suitable technique (such as depositing, inlay, dual damascene etc.).In one embodiment, can there is one or more metal layers, but the accurate quantity in the second metal layer 119 middle levels depends on the design of intermediary layer wafer 100 at least partly.
The second contact pad 121 can be formed on the second metal layer 119 tops in the second side of substrate 101 and electrically contact with the second metal layer 119.The second contact pad 121 can comprise aluminium, but also can use alternatively other materials, such as copper.Can use such as the depositing operation of sputter to form material layer (not shown), then can by suitable technique (such as, mask and etching) part of removing material layer forms the second contact pad 121 to form the second contact pad 121.Yet, also can any other suitable technique form the second contact pad 121, such as form opening in dielectric, deposition is for the material of the second contact pad 121, then this material of planarization and dielectric.The thickness of the second contact pad 121 can form between approximately 0.5 μ m and approximately 4 μ m, all 1.45 μ m according to appointment.
Can form the first joint outer part 123 to provide the outside being arranged between the second contact pad 121 and external devices (Fig. 1 does not illustrate separately) to connect.The first joint outer part 123 can be contact tab, such as dimpling piece or controlled collapse chip connection (C4) projection, and can comprise such as the material of tin or such as other suitable material of silver or copper.At the first joint outer part 123, be in the embodiment of tin solder projection, can form the first joint outer part 123 by the preferred thickness that first makes tin layer form about 100 μ m by any suitable method (such as evaporation, plating, printing, solder transfer, plant ball etc.).Once structurally form tin layer, preferably implement refluxing and making forming materials is the projection shape of expectation.
Alternatively, can form in the first intermediary layer region 103 and the second intermediary layer region 105 sealing ring 125 around so that the first intermediary layer region 103 and the second intermediary layer region 105 and the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 are separated.Sealing ring 125 can be for helping the functor in protection the first intermediary layer region 103 and the second intermediary layer region 105.In addition,, if needed, sealing ring 125 can be electrically connected to the functional circuit elements in the first intermediary layer region 103 and the second intermediary layer region 105 to provide and being electrically connected to of these elements.Sealing ring 125 can comprise such as copper, aluminium, tungsten, their electric conducting material of alloy etc.Yet, alternatively, can use other materials, such as, multilayer conductive material and insulating material.The thickness of sealing ring 125 can form between about 5 μ m and about 300 μ m, such as about 10 μ m.
Fig. 2 shows and intermediary layer wafer 100 can be divided into the line of a plurality of independent intermediary layers.In one embodiment, for example use diamond coatings saw (diamond coated saw) 201 that these independent intermediary layers are separated with intermediary layer wafer 100, saw 201 for the line cutting intermediary layer wafer 100 along such as the first scribe area 107 and the 3rd scribe area 111.Yet, in optional embodiment, also can use other scribble methods, such as use laser scriber use a series of etching or other separating technologies intermediary layer wafer 100 is divided into a plurality of independent intermediary layers.
In addition, in one embodiment, although diamond coatings saws 201 for cutting intermediary layer wafers 100 along the first scribe area 107 and the 3rd scribe area 111, diamond aspect saw 201 is not used in cutting the second scribe area 109.By not cutting through the second scribe area 109, although the first intermediary layer region 103 and the second intermediary layer region 105 separate with the remainder of intermediary layer wafer 100, the first intermediary layer region and the second intermediary layer region keep being fixed to one another.By keeping the first intermediary layer region 103 and the second intermediary layer region 105 to be fixed to one another, can obtain the single intermediary layer 200 of the exposure area that is greater than photoetching process.For example, the first width of single intermediary layer 200 can be between about 32mm with approximately between 52mm, such as about 42mm.
Yet as known to those skilled in the art, the first intermediary layer region 103 in this stage is only exemplary with the separated of the second intermediary layer region 105, and and is not used in and limits.On the contrary, the first intermediary layer region 103 and the second intermediary layer region 105 can be during manufacturing process any desired stages separated, for example, after being included in semiconductor element (the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305, described below with reference to Fig. 3 A and 3B) attached.Can utilize the first intermediary layer region 103 any suitable time separated with the second intermediary layer region 105, and all such time is intended to comprise in the present embodiment completely.
Fig. 3 A shows being connected of single intermediary layer 200 and the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305.In one embodiment, for example, the first semiconductor element 301 can be the logic dice such as Graphics Processing Unit, and the second semiconductor element 303 and the 3rd semiconductor element 305 can be memory dice.Yet, alternatively, can use any suitable combined semiconductor tube core and any amount of semiconductor element, and all this quantity, combination and functionally be all intended to completely be included in the scope of the present embodiment.
Fig. 3 B shows the plane graph for an embodiment of repeatably Logic * 1+DRAM * 4 layout of the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305.In one embodiment, a plurality of can being arranged on around the first semiconductor element 301 that is positioned at center in the second semiconductor element 303 and the 3rd semiconductor element 305.In one embodiment, the 3rd width w of the first semiconductor element 301 (for example, logic dice) 3can be between about 11mm and about 33mm, all 22mm according to appointment, the second length l 2between about 16mm and about 36mm, all 26mm according to appointment.The second semiconductor element 303 (for example, the 4th width w DRAM) 4can be between about 7mm and about 14mm, all 7mm according to appointment, the 3rd length l 3can be between about 7mm and about 17mm, all 12mm according to appointment.Can on whole intermediary layer wafer 100, repeat this connection configuration.
Fig. 3 C shows the optional layout that can utilize Logic * 1+DRAM * 8 pattern.In this embodiment, 6 the second semiconductor elements 303 and the 3rd semiconductor element 305 are positioned at the first semiconductor element 301 around.For example, 2 the second semiconductor elements 303 can be positioned at each side of the first semiconductor element 301.
Fig. 3 D shows the multiple layout that can use the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305.In first area 310, the first semiconductor element 301 is positioned at the opposite side of two the second semiconductor elements 303.In second area 312, the single kernel of the first semiconductor element 301 is set to be close to the second semiconductor element 303 and the 3rd semiconductor element 305.In the 3rd region 314, two kernels of the first semiconductor element 301 are arranged to two the second semiconductor elements 303 of next-door neighbour.In the 4th region 316, changed the layout in the 3rd region 314.These and every other suitable layout are all intended to be included in the scope of the present embodiment completely.
Now, refer again to Fig. 3 A, in one embodiment, each in the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 comprises the second substrate 307, active device (not illustrating separately in Fig. 3 A), the 3rd metal layer 309, the 3rd contact pad 311 and the second joint outer part 313 respectively.The second substrate 307 can be the semi-conducting material with the crystal orientation of (110), such as silicon, germanium, diamond etc.Alternatively, also can use the composite material with other crystal orientations, such as SiGe, carborundum, GaAs, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, InGaP, their combination etc.In addition, the second substrate 307 can comprise silicon-on-insulator (SOI) substrate.Conventionally, SOI substrate comprises semiconductor material layer, such as epitaxial silicon, germanium, SiGe, SOI, sige-on-insulator (SGOI) or their combination.The second substrate 307 can be doped with p-type dopant, such as, boron, aluminium, germanium etc., but well known in the art, this substrate can be alternatively doped with N-shaped dopant.
Each in the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 all can have the active device being formed on their corresponding second substrates 307.As known to those skilled in the art, can use multiple active device and passive device, desired structure and functional requirement such as capacitor, resistor, inductor etc. with generation design.For example, can be used to form the memory cell in the second semiconductor element 303 and the 3rd semiconductor element 305 with the capacitor of transistors couple.Can use any suitable method in the surface of corresponding the second substrate 307 or on form active device.
The 3rd metal layer 309 can be formed on corresponding the second substrate 307 and active device top, and is designed to connect a plurality of the first active devices on their corresponding tube cores to form functional circuit.The 3rd metal layer 309 can be formed by the alternating layer of dielectric material and electric conducting material, and can form by any suitable technique (such as depositing, inlay, dual damascene etc.).In one embodiment, exist by least one interlayer dielectric layer (ILD) four metal layers separated with the second substrate 307, but the accurate quantity of the 3rd metal layer 309 is designs of depending on respectively the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305.
In addition, can carry out to the 3rd metal layer 309 in the first semiconductor element 301 patterning so that the first intermediary layer region 103 in single intermediary layer 200 and the connecting path 317 between the second intermediary layer region 105 to be provided.Can utilize connecting path 317 in the first semiconductor element 301 to using between the first intermediary layer region 103 and the second intermediary layer region 105 transmission of signal and/or power and replace as two separated different units as individual unit with the second intermediary layer region 105 with the first intermediary layer region 103.In one embodiment, can form connecting path 317, make when the first semiconductor element 301 is connected to single intermediary layer 200, connecting path 317 will cross the second scribe area 109 and sealing ring 125 is electrically connected to foundation between the first intermediary layer region 103 and the second intermediary layer region 105.
The 3rd contact pad 311 can be formed on the 3rd metal layer 309 tops that are positioned in respective dies and electrically contact with the 3rd metal layer.The 3rd contact pad 311 can comprise aluminium, but also can use alternatively the other materials such as copper.Can use such as the depositing operation of sputter to form material layer (not shown), then can to form the 3rd contact pad 311, form the 3rd contact pad 311 by a part for suitable technique (such as mask and etching) removal material layer.Yet, can form the 3rd contact pad 311 by any other suitable technique, such as, opening, deposition in dielectric, formed for the 3rd contact pad 311 materials, then this material of planarization and dielectric.The thickness of the 3rd contact pad 311 can form between approximately 0.5 μ m and approximately 4 μ m, all 1.45 μ m according to appointment.
Can form the second joint outer part 313 to provide the outside between the 3rd contact pad 311 and single intermediary layer 200 to connect.The second joint outer part 313 can be contact tab, such as dimpling piece or controlled collapse chip connection (C4) projection, and can comprise such as the material of tin or such as other suitable material of silver or copper.At the second joint outer part 313, be in the embodiment of tin welding projection, can form the second joint outer part 313 by the preferred thickness that first makes tin layer be formed to about 100 μ m by any suitable method (such as evaporation, plating, printing, solder transfer, plant ball etc.).Once structurally form tin layer, preferably, with regard to implementing to reflux, making forming materials is the projection shape of expectation.
In addition, pseudo-projection (not illustrating separately) can be between single intermediary layer 200 and any device, used in Fig. 3 A, such as single intermediary layer 200, the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 can be connected to.These pseudo-projections can be used to structure to provide support and reduce issuable stress.By this support is provided, can prevent the thermal cycle of the repetition that may occur in storage and use procedure and the infringement of environment cycle period.
The first semiconductor element 301, the second semiconductor element 303, the 3rd semiconductor element 305 can be placed on single intermediary layer 200.In one embodiment, can the first semiconductor element 301, the second semiconductor element 303, the 3rd semiconductor element 305 be placed on single intermediary layer 200 in the face of the second joint outer part 313 mode of aiming at this second joint outer part 313 with the first contact pad 117.Once aim at, just can contact and implement backflow with the first contact pad 117 by the second joint outer part 313 with by the material reflow of the second joint outer part 313 and be engaged to the first contact pad 117 the second joint outer part 313 and the first contact pad 117 are bonded together.Yet, can use alternatively any suitable joint method, such as copper-copper, engage, so that the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 are engaged to single intermediary layer 200.
Can in the space between the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 and single intermediary layer 200, inject or form underfill 315 with diverse ways.For example, this underfill 315 can comprise liquid-state epoxy resin, liquid-state epoxy resin is dispersed between the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 and single intermediary layer 200, is then cured to be hardened.This underfill 315 can form crack for preventing in the second joint outer part 313, and wherein, this crack is caused by thermal stress conventionally.
Alternatively, in order to prevent producing crack in the second joint outer part 313, can between the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 and single intermediary layer 200, form deformable gel or silicon rubber.Can or otherwise place this gel or rubber forms this gel or silicon rubber by injection between the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 and single intermediary layer 200.This deformable gel or silicon rubber also can provide stress to eliminate during technique subsequently.
By keeping connection between the first intermediary layer region 103 and the second intermediary layer region 105 and by forming connecting path 317 with the first intermediary layer region 103 and the second intermediary layer region 105 of interconnecting above the second scribe area 109, can overcoming the size restrictions on the single intermediary layer of setting by photoetching process.This makes in the design and use of intermediary layer and is more flexible in the quantity of connector and type, and wherein, this connector can be connected to intermediary layer semiconductor element and other device.
Fig. 4 shows another embodiment, wherein, replace the first intermediary layer region 103 to be connected to 105, the first intermediary layer regions 103, the second intermediary layer region by the first semiconductor element 301 and be connected to the second intermediary layer region 105 by cross tie part (PPI) 407 after being formed on the passivation of the first intermediary layer region 103, the second intermediary layer region 105 and the second scribe area 109 tops.Yet, due to the photolithographic exposure region for PPI407 limited unlike the photolithographic exposure region for the first intermediary layer region 103 and the second intermediary layer region 105, can be for while patterning the first intermediary layer region 103 and the second intermediary layer region 105 so be used to form mask and the etch process of PPI 407.
In one embodiment, can above the first metal layer 115 and the first contact pad 117, form PPI 407 by first form the first passivation layer 401 on substrate 101.The first passivation layer 401 can be made by one or more suitable dielectric materials, such as silicon dioxide, silicon nitride, such as the low K dielectrics of carbon-doped oxide, such as mixing the super low K dielectrics of the silicon dioxide of porous carbon, their combination etc.The first passivation layer 401 can be by forming such as the technique of chemical vapor deposition (CVD), but can use other suitable technique, and the thickness of the first passivation layer 401 can be between 0.5 μ m and approximately 5 μ m, according to appointment all
Figure BDA00002674494700151
After forming the first passivation layer 401, can to expose at least a portion of the first contact pad 117 below, make the opening through the first passivation layer 401 by removing first passivation layer 401 parts.This opening allows the contact between the first contact pad 117 and PPI 407 (being further described below).Can use suitable mask and etch process to form this opening, but can use any suitable technique to expose a part for the first contact pad 117.
After exposing the first contact pad 117, can form the PPI 407 extending along the first passivation layer 401.PPI 407 can be as redistributing layer to allow the first intermediary layer region 103 and the second intermediary layer region 105 mutually be electrically connected to by PPI 407, and for signal between the first semiconductor element 301, the second semiconductor element 303, the 3rd semiconductor element 305 and single intermediary layer 200 and the additional flexibility of power routes are provided.The crystal seed layer (not shown) that in one embodiment, can form at first CTB alloy by suitable formation technique (such as CVD or sputter) forms PPI 407.Then form photoresist (not shown) to cover crystal seed layer, then patterning photoresist is to expose those parts of the position that is positioned at expectation PPI 407 location of crystal seed layer.
Once form and patterning photoresist, just can form the electric conducting material such as copper on crystal seed layer by the depositing operation such as electroplating.The thickness of this electric conducting material can form between approximately 1 μ m and approximately 10 μ m, all 5 μ m according to appointment, and its width along substrate 101 is between approximately 5 μ m and approximately 300 μ m, such as 15 μ m.Yet although described materials and methods is suitable for forming electric conducting material, these materials are only exemplary.Alternatively, can use such as any other suitable material of AlCu or Au and such as any other suitable formation technique of CVD or PVD to form PPI407.
Once formation electric conducting material, just can remove photoresist by the suitable removal technique such as ashing.And, after removing photoresist, for example, can be by using electric conducting material to remove crystal seed layer those parts covered by photoresist as the suitable etch process of mask.
Once form PPI 407, just can form the second passivation layer 405 with protection PPI 407 and the structure below other.The second passivation layer 405 can be formed by the polymer such as polyimides, or alternatively, can be by for example, forming with the similar material of the first passivation layer 401 (, silicon dioxide, silicon nitride, low K dielectrics, super low K dielectrics, their combination etc.).The thickness of the second passivation layer 405 can form between approximately 2 μ m and approximately 15 μ m, all 5 μ m according to appointment, and the second passivation layer 405 can be flattened by the technique such as CMP together with PPI 407.
Fig. 5 shows the layout of the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 that the first intermediary layer region 103 is connected with single intermediary layer 200 by PPI 407 with intermediary layer wafer 100 after separatings with the second intermediary layer region 105.In one embodiment, the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 can be placed on single intermediary layer in the face of PPI 407 mode of aiming at PPI 407 with the first contact pad 117.Once aim at, then the second joint outer part 313 just can be bonded together by the second joint outer part 313 being contacted with PPI 407 and implementing backflow with the material of second joint outer part 313 that refluxes and be engaged to PPI 407 with PPI 407.Yet, alternatively, can use any suitable joint method, such as, copper-copper engages so that the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 are engaged to PPI 407.
By form PPI 407 above the second scribe area 109, PPI 407 contributes to electrical interconnection the first intermediary layer region 103 and the second intermediary layer region 105.It is only a plurality of intermediary layers that are physically attached to each other as single intermediary layer to replace that the interconnection in the first intermediary layer region 103 and the second intermediary layer region 105 contributes to the first intermediary layer region 103 and the second intermediary layer region 105.This is integrated make single intermediary layer 200 more effectively and integrated level higher.
Fig. 6 shows the starting point for another embodiment, wherein, for example utilize diamond aspect saw 201 to cut apart the first intermediary layer region 103 via the first scribe area 107, the second scribe area 109 and the 3rd scribe area 111 separated with intermediary layer wafer 100 with the second intermediary layer region 105 and be separated from each other.Yet, after the first intermediary layer region 103 and the second intermediary layer region 105 are separated from each other, together with can rejoining with the second intermediary layer region 105 in the first intermediary layer region 103.
In one embodiment, for example, the first intermediary layer region 103 and the second intermediary layer region 105 can be used shaped device (not shown) to be bonded together.For example, the first intermediary layer region 103 and the second intermediary layer region 105 can be placed in the cavity of shaped device, and this cavity can hermetic be sealed.Can hermetic before seal chamber, sealant 701 be placed in cavity, or by injection port, sealant be expelled in cavity.In one embodiment, sealant 701 can be molding compound resins, for example, and polyimides, PPS, PEEK, PES, heat-resisting crystal resin, their combination etc.
Once sealant 701 is placed in to cavity, make the region between sealant 701 sealing the first intermediary layer regions 103 and the second intermediary layer region 105, can with sclerosis, be used for providing the sealant 701 of best protection by curing sealant 701.Although strict curing process depends on the certain material of selecting for sealant 701 at least partly, but moulding compound is being elected as in the embodiment of sealant 701, can be by the technique of (such as being heated to approximately 125 ℃ and heat approximately 60 seconds to approximately 3000 seconds, such as 600 seconds) is cured such as sealant 701 being heated between approximately 100 ℃ and approximately 130 ℃.In addition, in sealant 701, can comprise that initator and/or catalyst are to control better curing process.
Yet as known to those skilled in the art, above-mentioned curing process is only exemplary technique, and do not mean that restriction the present embodiment.Alternatively, also can use other curing process, such as, irradiate and even allow the sealing agent 701 of hardening at ambient temperature.Can use any suitable curing process, and all such technique is all intended to be included in the scope of the embodiment discussing completely herein.
By sealing the region between the first intermediary layer region 103 and the second intermediary layer region 105, sealant 701 is as the bridge to single intermediary layer 200 by the first intermediary layer region 103 and the second intermediary layer region 105 physical connections.Second scribe area 109 of not rule of this bridge for replacing above-described embodiment to discuss, and due to the first intermediary layer region 103 and the second intermediary layer region 105 is separated and (if need) be re-engaged for more effective technique integrated, so this bridge provides more flexibility.
Fig. 8 shows the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 and places and be engaged on single intermediary layer 200.In one embodiment, the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 can be placed on single intermediary layer in the face of the second joint outer part 313 mode of aiming at the second joint outer part 313 with the first contact pad 117.Once aim at, the second joint outer part 313 just can be bonded together by the second joint outer part 313 being contacted with the first contact pad 117 and implementing backflow with the material of second joint outer part 313 that refluxes and be engaged to the first contact pad 117 with the first contact pad 117.Yet, alternatively, can use any suitable joint method, such as, copper-copper engages, so that the first semiconductor element 301, the second semiconductor element 303 and the 3rd semiconductor element 305 are engaged to single intermediary layer 200.
According to an embodiment, provide a kind of semiconductor device that comprises the intermediary layer with the first side and the second side.This intermediary layer comprise have the first circuit first area, there is the second area of second circuit and the 3rd region between first area and second area, the 3rd region does not have circuit and extends to the second side from the first side.Conductive path is between first area and second area, and this conductive path extends above the 3rd region.
According to another embodiment, a kind of semiconductor device that comprises intermediary layer is provided, wherein, scribe area is between first area and second area.The first contact is arranged in first area, and the second contact is arranged in second area.Conductive path extends above scribe area, and this conductive path is electrically connected to the first contact and the second contact.
According to another embodiment, a kind of method of manufacturing semiconductor device is provided, the method comprises: use photoetching process to form the first circuit in the first area of wafer, form second circuit in the second area of wafer and form scribe area between first area and second area, wherein, photoetching process is used by the exposure energy being patterned of first size, and the first area with first size wafer is provided.In first area and the unseparated situation of second area, by first area and second area and wafer separate, and the first circuit is connected above scribe area with second circuit.
Although described the present embodiment and advantage thereof in detail, should be appreciated that, can in the situation that do not deviate from the spirit and scope of the present invention that claims limit, make various change, replacement and change.For example, can change or change and manufacture definite materials and methods, also can reset the order of processing step, but this still remain in the scope of the present embodiment.
And the application's scope is not limited in the specific embodiment of technique, machine, manufacture, material component, device, method and the step described in this specification.As those of ordinary skills, should understand, by the present invention, existing or Future Development for carrying out and can being used according to the present invention according to the essentially identical function of described corresponding embodiment of the present invention or the technique, machine, manufacture, material component, device, method or the step that obtain basic identical result.Therefore, claims should be included in the scope of such technique, machine, manufacture, material component, device, method or step.

Claims (10)

1. a semiconductor device, comprising:
Intermediary layer, has the first side and the second side, and described intermediary layer comprises:
First area, comprises the first circuit;
Second area, comprises second circuit; With
The 3rd region, between described first area and described second area, described the 3rd region does not have circuit and extends to described the second side from described the first side; And
Conductive path, between described first area and described second area, described conductive path extends above described the 3rd region.
2. semiconductor device according to claim 1, wherein, described the 3rd region is the scribe area between described first area and described second area.
3. semiconductor device according to claim 1, wherein, described the 3rd region comprises sealant.
4. semiconductor device according to claim 1, wherein, described conductive path is a part for the first semiconductor element.
5. semiconductor device according to claim 4, further comprises the second semiconductor element that is attached to described first area.
6. semiconductor device according to claim 1, wherein, described the first circuit and described second circuit have different patterns.
7. semiconductor device according to claim 1, wherein, described the first circuit is identical with described second circuit.
8. a semiconductor device, comprising:
Intermediary layer, has between second area and the 3rd region and there is no the first area of functional circuit;
The first contact, is arranged in described second area;
The second contact, is arranged in described the 3rd region; And
Conductive path extends above described first area, and described conductive path is electrically connected to described the first contact and described the second contact.
9. semiconductor device according to claim 8, wherein, described conductive path is a part that is positioned at the first semiconductor element of top, described first area.
10. manufacture a method for semiconductor device, described method comprises:
Use photoetching process in the first area of wafer, to form the first circuit, in the second area of described wafer, form second circuit and form scribe area between described first area and described second area, wherein, described photoetching process is used and is had the patterned exposure energy of first size and the described first area of described wafer has described first size;
The in the situation that of not separated described first area and described second area, by described first area and described second area and described wafer separate; And
Above described scribe area, described the first circuit is connected to described second circuit.
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