CN103579088A - Method for forming through silicon vias of semiconductor device - Google Patents
Method for forming through silicon vias of semiconductor device Download PDFInfo
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- CN103579088A CN103579088A CN201210261979.9A CN201210261979A CN103579088A CN 103579088 A CN103579088 A CN 103579088A CN 201210261979 A CN201210261979 A CN 201210261979A CN 103579088 A CN103579088 A CN 103579088A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Abstract
The invention relates to a method for forming through silicon vias of a semiconductor device. The method comprises the steps of providing an SOI substrate, wherein the substrate comprises a supporting substrate, an insulation oxide buried layer and a semiconductor material layer from bottom to top in sequence; depositing an insulation material layer on the SOI substrate; etching the insulation material layer and the semiconductor material layer to expose the insulation oxide buried layer; at least etching parts of the insulation oxide buried layer to form the through silicon vias; forming insulation medium layers at least on the exposed side wall of the semiconductor material layer in each through silicon via and the bottom of each through silicon via; forming a barrier layer in each through silicon via, and then filling each through silicon via with electrical conducting materials; bonding the front face of the SOI substrate and a supporting carrier; carrying out etching to remove the supporting substrate; removing the insulation medium layer on the bottom of each through silicon via to expose the barrier layer, and meanwhile at least reserving a part of the insulation oxide buried layer located on the semiconductor material layer. According to the method for forming the through silicon vias of the semiconductor device, control is easier, and efficiency is higher.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of preparation method of semiconductor device silicon through hole.
Background technology
In E-consumer field, multifunctional equipment is more and more subject to liking of consumer, than the simple equipment of function, multifunctional equipment manufacturing process will be more complicated, such as need to be in circuit version the chip of integrated a plurality of difference in functionalitys, thereby there is 3D IC technology, 3D IC is defined as a kind of system-level integrated morphology, a plurality of chips are stacking in vertical plane direction, thereby saving space, the marginal portion of each chip can be drawn a plurality of pins as required, utilize as required these pins, the chip that needs are interconnected is interconnected by metal wire, but still there are a lot of deficiencies in aforesaid way, such as stacked chips quantity is more, and the annexation more complicated between chip, will need so to utilize many metal line, final wire laying mode is more chaotic, and can cause volume to increase.
Therefore, in described 3D IC technology, mostly adopt at present silicon through hole (Through Silicon Via, TSV), silicon through hole is a kind of perpendicular interconnection that penetrates Silicon Wafer or chip, and TSV can storehouse multi-plate chip, (processing procedure can be divided into again first two kinds of boring and rear borings at chip, to get out duck eye, Via Fist, Via Last), from bottom, be packed into metal, on Silicon Wafer, with etching or laser mode, hole (via), then fill up as materials such as copper, polysilicon, tungsten with electric conducting material.Thereby realize interconnected between different silicon chips.
The preparation method of current described silicon through hole is: as shown in Figure 1a, first Semiconductor substrate 101 is provided, described substrate can be insulating barrier 103 for silicon base 101, described substrate excessively top, described in etching, substrate 101 and insulating barrier 103 form opening, then fill metal material, form silicon through hole 102, then depositing metal layers 104, are then connected with supporting carrier 105.Forming the laggard row metal interconnection process of silicon through hole shown in Fig. 1 a, in metal interconnection process, need described substrate to carry out planarization to expose described silicon through hole 102 metal materials, described chemical-mechanical planarization is generally applicable to thickness and/or the less lamination effect of difference in thickness is better, very large at substrate thickness described in this rear bore process, be difficult to reach required effect by chemical-mechanical planarization, therefore be generally first described substrate to be ground, polishing, obtain pattern as shown in Figure 1 b, then described silicon substrate was carried out to etching, to expose described metallic silicon through hole 102, as shown in Fig. 1 c, and then the less dielectric medium 106 of deposition a layer thickness, as shown in Figure 1 d, finally carry out chemical-mechanical planarization, obtain silicon through hole, as shown in Fig. 1 e.Therefore, in current preparation method, because chemical-mechanical planarization is wayward, cause the preparation process of silicon through hole more loaded down with trivial details, complicated, efficiency is very low.
Therefore, be badly in need of the preparation process of silicon through hole to improve, loaded down with trivial details to overcome process, wayward, the problem of inefficiency.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of preparation method of semiconductor device silicon through hole, comprising:
SOI substrate is provided, and described substrate comprises support substrates, insulation oxide buried regions and semiconductor material layer from the bottom up successively;
Deposition of insulative material layer on described SOI substrate;
Insulation material layer described in etching, forms opening, exposes described semiconductor material layer;
Take described insulation material layer as mask, and semiconductor material layer described in etching, to expose described insulation oxide buried regions;
At least insulation oxide buried regions described in etching part, forms silicon through hole;
Insulating medium layer is formed on the side of the semiconductor material layer at least exposing in described silicon through hole and the bottom of described silicon through hole;
In described silicon through hole, form barrier layer and then fill electric conduction material, and carry out planarization;
By the front of described SOI substrate and supporting carrier bonding;
Described support substrates is removed in etching, exposes the described insulating medium layer in described insulation oxide buried regions and described silicon via bottoms;
Remove the described insulating medium layer in described silicon via bottoms, expose described barrier layer, at least reserve part is positioned at the described insulation oxide buried regions on described semiconductor material layer simultaneously.
As preferably, at least the described insulation oxide buried regions of 1/3 thickness is removed in etching.
As preferably, before support substrates described in etching, comprise the step that grind at back.
As preferably, adopt wet etching to remove described support substrates.
As preferably, in described wet etching, select KOH, NH3H2O or TMAH.
As preferably, described insulation material layer is selected SiO2, SiN, SiON or low-K material.
As preferably, described barrier layer is one or more in TaN, Ta, TiN, Ti.
As preferably, described electric conduction material is copper, aluminium or tungsten.
As preferably, described insulating medium layer is oxide skin(coating).
As preferably, adopt the method for oxidation or deposition to form described insulating medium layer.
As preferably, form after insulating medium layer, the gross thickness of the thickness of the insulating medium layer of described silicon via bottoms or insulation oxide and insulating medium layer is greater than 100 dusts, is less than 3/4 of described insulation oxide buried regions original depth.
The invention provides a kind of method of preparing silicon through hole of novelty, in the present invention, in the process of preparing silicon through hole, by engraving method, remove described support substrates, overcome the problem of smooth wayward, the inefficiency of chemical machinery in prior art, make preparation process be more prone to control, efficiency is higher.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 a-e is that prior art is prepared silicon via process schematic diagram;
Fig. 2 is the method schematic diagram that the present invention prepares silicon through hole;
Fig. 3 a-j is that the present invention prepares silicon via process schematic diagram.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed description be proposed in following description, so that the preparation method of semiconductor device silicon through hole of the present invention to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
The present invention is in order to solve the problem existing in current semiconductor device silicon through hole preparation process, a kind of preparation method of semiconductor device silicon through hole is provided, Fig. 2 is for making the process chart of semiconductor device silicon through hole according to one embodiment of the present invention, Fig. 3 a-j is for making the cutaway view of the device that in semiconductor device silicon via process process, each step obtains according to one embodiment of the present invention.
Below in conjunction with Fig. 2 and Fig. 3 a-j, preparation method of the present invention is described in detail.
First, perform step 201 SOI substrate is provided, described substrate comprises support substrates, insulation oxide buried regions and semiconductor material layer from the bottom up successively;
Particularly, as shown in Figure 3 a, the semiconductor material layer 203 that described SOI substrate comprises support substrates 201, insulation oxide buried regions 202 and is positioned at insulation oxide buried regions top.Wherein, the thickness of described insulation oxide buried regions 202 is Tb.In one embodiment of this invention, described semiconductor material layer can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Particularly, deposition of insulative material layer 204 above described semiconductor material layer 203, as shown in Figure 3 b, as preferably, described insulation material layer 204 can be selected a kind of in SiO2, SiN, SiON or low-K material, but is not limited to described material; Insulation material layer 204 can be selected the material same with described insulation oxide buried regions 202, also can select different materials, as long as can play insulating effect, and not specific (special) requirements.
Described in etching, insulation material layer 204, form opening, particularly, can first on described insulation material layer, form photoresist material layer in an embodiment of the present invention, on described photoresist, apply resist, expose, then the pattern forming with photoresist as shown in Figure 3 b, the described photoetching agent pattern of take carries out etching to described insulation material layer 204 as mask, to form opening as shown in Figure 3 c, expose described semiconductor material layer 203, then remove described photoresist material layer, described removal method can be selected this area common method, such as high temperature ashing etc.
Particularly, the described insulation material layer 204 of take is mask, described in etching, semiconductor material layer 203, as preferably, in described support substrates, continuous insulation oxide buried regions 202 can play the effect of etching stopping layer, and this process only etching is positioned at the backing material of insulation oxide buried regions 202 tops, to expose described insulation oxide buried regions 202, as shown in Figure 3 c, as further preferred, described engraving method can be selected wet etching.
Particularly, insulation oxide buried regions 202 described in etching, the thickness that remains described insulation oxide buried regions 202 after etching is Tr, described 0≤Tr≤2/3Tb, the insulation oxide buried regions 202 described in etching part at least in this step, as preferably, at least will etch away 1/3 of original thickness, also described insulation oxide buried regions 202 all constantly can be fallen, or select any thickness between the two all can.In an embodiment of the present invention, by the whole etchings of described insulation oxide buried regions 202, obtain pattern as shown in Figure 3 d.
Insulating medium layer is formed on execution step 205 sides of the semiconductor material layer at least exposing in described silicon through hole and the bottom of described silicon through hole, as shown in Figure 3 e;
Particularly, in this step, there are two kinds of concrete execution modes, the first situation is in described step 204, the whole etchings of described insulation oxide buried regions 202 to be removed, expose described support substrates material, on the surface of exposed support substrates, comprise that upper surface and side form insulating medium layer 205, the thickness that forms insulating medium layer 205 in this step is Tf, described Tf is greater than 100 dusts, is less than 3/4 of described insulation oxide buried regions original depth, i.e. 100 dusts≤Tf≤3/4Tb.At insulating medium layer 205 described in concrete enforcement, there are two kinds of formation methods, the first can be at described support substrates upper surface and side deposition insulating medium layer, described insulating medium layer is oxide skin(coating), and described dielectric layer material can be selected a kind of in SiO2, SiON or low-K material; In addition, can also on described support substrates surface, form one deck oxide insulating layer by the method for high-temperature oxydation, those skilled in the art can select as required, are not limited to above-mentioned two kinds of methods;
Another execution mode in this step is to insulation oxide buried regions 202, to have carried out partially-etched in described step 205, in this step, in the side of described support substrates and above residue insulation oxide buried regions 202, form insulating medium layer 205, same described insulating medium layer 205 has above-mentioned two kinds of formation methods, does not repeat them here.In this step, forming insulating medium layer 205 forms after insulating medium layer, in described support substrates, the thickness of insulation oxide and insulating medium layer is greater than 100 dusts, be less than 3/4 of described insulation oxide buried regions original depth, the thickness that forms insulating medium layer 205 in this step is Tf, 100 dusts≤Tf≤3/4Tb.
Particularly, first in described silicon through hole, form barrier layer 207, as shown in Fig. 3 f, described barrier material can be for being selected from TaN, Ta, TiN, one or more in Ti, then at described barrier layer surface deposition electric conduction material 208, described electric conduction material 208 can be metal material, described electric conduction material can be copper in the present invention, aluminium or tungsten layer: the surface deposition electric conduction material on barrier layer in described through hole, deposition process can be selected deposition process conventional in prior art, can be for example by chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or ald (ALD) method, then described electric conduction material layer is carried out to planarization.
Particularly, the one side of described electric conduction material and the described electric combination of supporting carrier 206 are exposed in the front of described SOI substrate, obtain pattern as shown in Fig. 3 g-h.
Perform step 208 etchings and remove described support substrates, expose the described insulating medium layer in described insulation oxide buried regions and described silicon via bottoms, as shown in Fig. 3 i;
Particularly, the described engraving method of selecting is removed described support substrates, before etching, can also comprise chemical-mechanical planarization, one or more in grinding, as preferentially, before carrying out etching, can also comprise back grinding steps, in a kind of embodiment of the present invention, first-selection selects Ginding process to remove most of support substrates, when described substrate is thinner, then carrying out cmp, at insulation oxide buried regions 202 described in this process as planarization barrier layer, described silicon through hole is played a protective role, finally carry out etching step, preferably wet etching is removed remaining support substrates in the present invention, in order to remove thoroughly described support substrates, in the present invention, can controlled condition form etching, but guarantee to remove described insulation oxide buried regions 202 completely, as further preferred, in described wet etching, select KOH, NH
3h
2o or TMAH(Tetramethylammonium hydroxide), but described etching is only exemplary, is not limited to described method.
The described insulating medium layer that execution step 209 is removed in described silicon via bottoms, exposes described barrier layer, and at least reserve part is positioned at the described insulation oxide buried regions on described semiconductor material layer simultaneously, as shown in Fig. 3 j;
Particularly, described insulating medium layer is removed in etching, selects with described insulation oxide buried regions 202 and has the engraving method compared with high selectivity, to guarantee that at least reserve part is positioned at the described insulation oxide buried regions 202 on described semiconductor material layer in this step.
The invention provides a kind of method of preparing silicon through hole of novelty, in the present invention, in the process of preparing silicon through hole, by engraving method, remove described support substrates, overcome the problem of smooth wayward, the inefficiency of chemical machinery in prior art, make preparation process be more prone to control, efficiency is higher.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (11)
1. a preparation method for semiconductor device silicon through hole, comprising:
SOI substrate is provided, and described substrate comprises support substrates, insulation oxide buried regions and semiconductor material layer from the bottom up successively;
Deposition of insulative material layer on described SOI substrate;
Insulation material layer described in etching, forms opening, exposes described semiconductor material layer;
Take described insulation material layer as mask, and semiconductor material layer described in etching, to expose described insulation oxide buried regions;
At least insulation oxide buried regions described in etching part, forms silicon through hole;
Insulating medium layer is formed on the side of the semiconductor material layer at least exposing in described silicon through hole and the bottom of described silicon through hole;
In described silicon through hole, form barrier layer and then fill electric conduction material, and carry out planarization;
By the front of described SOI substrate and supporting carrier bonding;
Described support substrates is removed in etching, exposes the described insulating medium layer in described insulation oxide buried regions and described silicon via bottoms;
Remove the described insulating medium layer in described silicon via bottoms, expose described barrier layer, at least reserve part is positioned at the described insulation oxide buried regions on described semiconductor material layer simultaneously.
2. method according to claim 1, is characterized in that, at least the described insulation oxide buried regions of 1/3 thickness is removed in etching.
3. method according to claim 1, is characterized in that, comprises the step that grind at back before support substrates described in etching.
4. method according to claim 1, is characterized in that, adopts wet etching to remove described support substrates.
5. method according to claim 4, is characterized in that, selects KOH, NH3H2O or TMAH in described wet etching.
6. method according to claim 1, is characterized in that, described insulation material layer is selected SiO2, SiN, SiON or low-K material.
7. method according to claim 1, is characterized in that, described barrier layer is one or more in TaN, Ta, TiN, Ti.
8. method according to claim 1, is characterized in that, described electric conduction material is copper, aluminium or tungsten.
9. method according to claim 1, is characterized in that, described insulating medium layer is oxide skin(coating).
10. according to the method described in claim 1 or 9, it is characterized in that, adopt the method for oxidation or deposition to form described insulating medium layer.
11. methods according to claim 1, it is characterized in that, form after insulating medium layer, the gross thickness of the thickness of the insulating medium layer of described silicon via bottoms or insulation oxide and insulating medium layer is greater than 100 dusts, is less than 3/4 of described insulation oxide buried regions original depth.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5682062A (en) * | 1995-06-05 | 1997-10-28 | Harris Corporation | System for interconnecting stacked integrated circuits |
| CN101312161A (en) * | 2007-05-21 | 2008-11-26 | 国际商业机器公司 | Electronic structure and manufacturing method |
| CN101540295A (en) * | 2009-04-21 | 2009-09-23 | 北京大学 | Preparation method of insulation layer of TSV through hole |
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2012
- 2012-07-26 CN CN201210261979.9A patent/CN103579088B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5682062A (en) * | 1995-06-05 | 1997-10-28 | Harris Corporation | System for interconnecting stacked integrated circuits |
| CN101312161A (en) * | 2007-05-21 | 2008-11-26 | 国际商业机器公司 | Electronic structure and manufacturing method |
| CN101540295A (en) * | 2009-04-21 | 2009-09-23 | 北京大学 | Preparation method of insulation layer of TSV through hole |
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