CN103561008B - A kind of host-host protocol coding/decoding method, device and host-host protocol decoding chip - Google Patents
A kind of host-host protocol coding/decoding method, device and host-host protocol decoding chip Download PDFInfo
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Abstract
The present invention is applicable to the communications field, it is provided that a kind of host-host protocol coding/decoding method, device and host-host protocol decoding chip, and described method comprises the steps: to generate oscillator signal；Detection frame start signal, and when frame start signal being detected, export sampling control signal；After receiving sampling control signal, within the time cycle of frame start byte low level figure place, the cycle of oscillation of oscillator signal is counted, and count value is carried out division arithmetic, export quotient and the remainder；Determine the sampling period according to quotient and the remainder, to generate sampling pulse, and according to sampling pulse, data byte is decoded.The cycle of oscillation of oscillator signal was counted within the time cycle of frame start byte low level figure place by the present invention, and count value is carried out division arithmetic, obtain quotient and the remainder, it is decoded according to quotient and the remainder, do not have accumulated error to produce, substantially increase the accuracy rate of decoding, and realize simple, low cost, good stability.
Description
Technical field
The invention belongs to the communications field, particularly relate to a kind of host-host protocol coding/decoding method, device and host-host protocol decoding chip.
Background technology
Along with digital technology and the application of computer technology and universal, occur in that computer Control Console, and successively occur in that the simulations such as D54, AVAB, CMX, PMX, EMX and digital communication protocol.Due to the respective consensus standard of above consensus standard Shi Ge manufacturer, thus the compatibility between them is bad, the mutual general existing problems between equipment.Later, in order to solve the problem of each plant equipment versatility, theater technology association of the U.S. (United State Institute for Theatre Technology, USITT) has formulated DMX512 agreement in early 1980s.DMX512 agreement is a kind of digital multiplex (Digital Multiplex, DMX) agreement.After agreement is formulated, modified, USITT by DMX512 agreement more specification, defines DMX512-1990 in nineteen ninety.This control protocol is supported in current almost all of light and stage equipment factory commercial city, and as widely used digital light data protocol, DMX512-1990 also becomes the international standard of signal light control.
The unification of DMX512 agreement makes the equipment of each producer to be connected with each other, and compatibility is greatly improved.Simultaneously as DMX512 agreement uses serial mode to transmit digital signal, as long as a holding wire between control platform and equipment, enormously simplify the connecting line between control station and equipment.
DMX512 agreement can realize the brightness regulation to light units by sending packet in bus.The sequential of every part of packet has all been done the strictest regulation by agreement.Every byte has 11 bit data, 1 low level start bit, 8 bit data positions and 2 high level to stop position.One frame data comprise the brightness data of 1 address, and the 1st frame is the data of the 1st address, and the 2nd frame is the data of the 2nd address, and by that analogy, 512 frames can transmit the data of 512 addresses.DMX512 sequential chart is as shown in Figure 1.
It is described as follows table:
In the DMX512 agreement of standard, the data width of each bits is fixing, and for 4us, namely message transmission rate is 250Kbps (each second transmits 250Kbits data).
Existing protocol-decoding mode is:
By monitoring the start byte time width of every frame data, determine the time width of follow-up each byte.As a example by the DMX512 agreement of standard, consisting of of start byte :+2 end mark positions (2 " 1 ") of+8 byte data positions of 1 beginning flag position (" 0 ") (8 " 0 ").According to standard DMX512 agreement, the width of this start byte is 44us.Owing to 9 bits " 0 " in start byte are between frame beginning flag position (" 1 ") and 2 byte end mark positions (2 " 1 "), then the relatively good monitoring of time width of these 9 bits " 0 ".
The existing way first, according to sampled data, selects the mode in sampling period, such as, by internal oscillator, produce several sampling period T1, T2, T3, by the sampling to start byte, chooses optimal a kind of sampling period.The method is simple, but for selecting the identical default sampling period under multiple sampled data so that solve code error very big, particularly can not accomplish the sampling all standing after frequency upgrading.It is to say, can sample in some frequency range, can not sample in some frequency range, such as, can sample in 200～300Kbps, 400～500Kbps, but can not sample in 300～400Kbps.
Another way is to comprise a built-in agitator (cycle is T) in machine, and by 9 bits " 0 " time countings to start byte, such as, the time is T9bits, divided by 9, obtain the time width T of each bitbit.It is of course also possible to carry out division arithmetic in sampling process.And digital processing mode is generally used due to sampling, this time width TbitShould be the integral multiple N*T of cycle oscillator to avoid error to produce, and in practical situation, N is generally T9bits/ 9 obtain, it is difficult to control as aliquot, it is assumed that T9bits/ 9=8.6.
The most generally use the way retaining integer-bit, then above-mentioned data, choose N=8, when carrying out the decoding of each byte data, have accumulated error.As it is shown in figure 1, typically can sample in the center of data byte, sampling optimization is set to N (1/2+1) T, so, when decoding the start bit of each byte, has the error of [(8.6-8)/2] T=0.3T；When decoding the 1st data bit of each byte, have the error of [(8.6-8) × 1.5] T=0.9T；By that analogy, when decoding the 8th data bit of each byte, accumulated error is: the error of [(8.6-8) × 8.5] T=4.1T；Particularly, T is worked as in extreme circumstances9bits/ 9=8.99, when decoding the 8th data bit of each byte, accumulated error is about 8.5T, so can produce decoding error.The most typically choose sampling location for (N/2) T > 8.5T.To ensure when decoding the 8th data bit of each byte, will not sample in the 7th data bit.
But, in order to more accurately start byte time width be sampled, improve constantly from the frequency of machine agitator the highest more good.Because frequency is the highest, use the maximum accumulated error obtained by reservation rounding-off method, can be the least for the sampling period.In the above example, in standard DMX512 agreement, the time width of each bit is 4us, if N=16, then the cycle of internal oscillator would be 4us/16=0.25us, and frequency is 4MHz.
In actual applications, in the case of ensureing refresh rate, need to connect more from machine.It is to say, need to promote message transmission rate.If solving the code of higher frequency on the basis of above-mentioned internal oscillation frequency, such as decoding rate reaches 500Kbps, then maximum accumulated error remains as 8.5T, and if N=8, will decoding error.The most only by promoting the way of chip internal oscillator frequency.Oscillator frequency rises to 8MHz, such N=16 from 4MHz.By that analogy, if needing decoding rate to reach 1Mbps, then need the frequency of internal oscillator to be at least 16MHz.But on the basis of existing integrated circuit, the frequency reached megahertz, frequency is the biggest, and chip is more difficult to ensure in the stability that different times produces.
Therefore, existing host-host protocol coding/decoding method causes, due to the accumulated error in sampling period, the accuracy rate that is difficult to ensure that decoding, and promote data transmission rate by the way promoting chip internal oscillator frequency and solve code error cost height to reduce, it is achieved be complicated, poor stability.
Summary of the invention
The purpose of the embodiment of the present invention is to provide a kind of host-host protocol coding/decoding method, it is intended to solution current decoder method exists sampling period accumulated error and causes decoding inaccuracy, it is achieved complicated, cost height, the problem of poor stability.
The embodiment of the present invention is achieved in that a kind of host-host protocol coding/decoding method, and described method comprises the steps:
Generate oscillator signal；
Detection frame start signal, and when described frame start signal being detected, export sampling control signal；
After receiving described sampling control signal, within the time cycle of frame start byte low level figure place, the cycle of oscillation of described oscillator signal is counted, and described count value is carried out division arithmetic, export quotient and the remainder；
Determine the sampling period according to quotient and the remainder, to generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded.
The another object of the embodiment of the present invention is to provide a kind of host-host protocol decoding apparatus, and described device is connected with driver element, including:
Agitator, is used for generating oscillator signal；
Controller, is used for detecting frame start signal, and when described frame start signal being detected, exports sampling control signal, and the input of described controller receives transmission data；
Division arithmetic unit, for after receiving described sampling control signal, within the time cycle of frame start byte low level figure place, the cycle of oscillation of described oscillator signal is counted, and described count value is carried out division arithmetic, output quotient and the remainder, the end that controls of described division arithmetic unit is connected with the outfan of described controller, and the input of described division arithmetic unit is connected with the outfan of described agitator；
Decoding unit, for determining the sampling period according to described quotient and the remainder, to generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded, the first input end of described decoding unit is connected with the first outfan of described division arithmetic unit, second input of described decoding unit is connected with the second outfan of described division arithmetic unit, 3rd input of described decoding unit is connected with the input of described controller to receive transmission data, the clock end of described decoding unit is connected with the outfan of described agitator, the outfan of described decoding unit is connected with described driver element.
The another object of the embodiment of the present invention is to provide a kind of host-host protocol decoding chip using above-mentioned host-host protocol decoding apparatus.
The embodiment of the present invention is by counting the cycle of oscillation of oscillator signal within the time cycle of frame start byte low level figure place, and count value is carried out division arithmetic, obtain quotient and the remainder, it is decoded according to quotient and the remainder, does not has accumulated error to produce, it is not necessary to reduce solution code error by promoting data transmission rate, substantially increase the accuracy rate of decoding, and realize simple, low cost, good stability.
Accompanying drawing explanation
Fig. 1 is that DMX512 agreement sequential decodes schematic diagram；
The flow chart of the host-host protocol coding/decoding method that Fig. 2 provides for one embodiment of the invention；
The flow chart of the host-host protocol coding/decoding method that Fig. 3 provides for another embodiment of the present invention；
The structure chart of the host-host protocol decoding apparatus that Fig. 4 provides for the embodiment of the present invention；
In the host-host protocol decoding apparatus that Fig. 5 provides for the embodiment of the present invention, the one of division arithmetic unit realizes exemplary circuit figure；
Fig. 6 shows in the host-host protocol decoding apparatus that the embodiment of the present invention provides that the one of decoding unit realizes exemplary block diagram；
The flow chart being realized host-host protocol coding/decoding method by state machine that Fig. 7 provides for the embodiment of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The cycle of oscillation of oscillator signal was counted within the time cycle of frame start byte low level figure place by the embodiment of the present invention, and count value is carried out division arithmetic, is decoded according to quotient and the remainder, does not has accumulated error to produce, substantially increases the accuracy rate of decoding.
Fig. 2 shows the flow process of the host-host protocol coding/decoding method that one embodiment of the invention provides, and for convenience of description, illustrate only part related to the present invention.
In step S101, agitator generates oscillator signal OSC；
In step s 102, controller detection frame start signal, and when frame start signal being detected, export sampling control signal；
In embodiments of the present invention, this frame start signal is first low level of each frame in transmission data, see the numbering 1 in Fig. 1, the low level time width of the frame start signal in each frame of controller detection transmission data, when low level time is more than Preset Time width, controller confirms frame start signal to be detected, and export sampling control signal, such as, in standard DMX512 agreement, this frame start signal low level time width is more than 88us, and for class DMX512 agreement, controller can also detect Preset Time width according to the frame start signal low level time width setup of this agreement.
In step s 103, after division arithmetic unit receives sampling control signal, within the time cycle of frame start byte low level figure place, T cycle of oscillation of oscillator signal OSC is counted, and to count value NKbitsCarry out division arithmetic, export quotient and the remainder；
In embodiments of the present invention, frame start byte be transmission each frame of data frame start signal after first character joint (include 1 low level start bit, 8 bit data positions and 2 high level stop position), see the part that in Fig. 1, first numbering 3 is indicated, division arithmetic unit is after receiving sampling control signal, in units of cycle of oscillation, start using the trailing edge of frame start byte as counting, terminate using the rising edge of frame start byte as counting, in the Sampling time periods of frame start byte low level figure place, T cycle of oscillation is counted, obtain clock number (count value N corresponding with the Sampling time periods of frame start byte low level figure placeKbits), then the time width of start byte is NkbitsT, wherein T is cycle oscillator.
And then, division arithmetic unit is to this count value NKbitsDo division arithmetic, obtain business N and remainder M, i.e. N K+M=Nkbits.Wherein, K is the figure place of the low level correspondence of frame start byte.
As a example by standard DMX512 agreement, owing to this protocol frame start byte low level bit is 9 (with reference to Fig. 1 and Biao 1), division arithmetic unit is after receiving sampling control signal and cycle of oscillation T, start using the trailing edge of frame start byte as counting, by cycle of oscillation of agitator output in units of T, terminate as counting using the rising edge of start byte, the time width N of frame start byte detected9bitsT, to N9bitsDo except 9 computings, obtain business N and remainder M, wherein 9 N+M=N9bits。
Certainly, in class DMX512 agreement, can arbitrarily set frame start byte low level time width NkbitsT and figure place K corresponding to low level, it is also possible to arbitrarily set transmitted data byte figure place j.Accordingly, division arithmetic is Nkbits÷ K, it is made up of two parts, and wherein N is business, and M is remainder, and N K+M=Nkbits, wherein M is 0 to the arbitrary integer in (k-1).Owing to generally sampling in the center of data byte, the sampling period of follow-up start bit is (N/2) T, and the sampling period in data byte (having j position) is Tsamp=T N or Tsamp=T (N+1), wherein has (j-X) individual TsampN and X T of=Tsamp=T (N+1), wherein, X=M (j ÷ K).
In step S104, decoding unit determines the sampling period according to quotient and the remainder, to generate sampling pulse, and is decoded the data byte in transmission data according to this sampling pulse.
In embodiments of the present invention, decoding unit is according to business N and remainder M, determine the sampling period, this sampling period includes two kinds of sampling pulse intervals, and then samples the data byte in each frame according to both sampling pulses interval, is decoded, above-mentioned data byte refers to the multiple bytes after each frame first byte, as a example by standard DMX512 agreement, the figure place of frame start byte is 9, and the figure place of each data byte is also 9 (wherein the 1st is 1 ' b0).Corresponding 9 sampling pulses of each data byte, each interpulse time width, controlled by N and M.Wherein, in order to sample accurately, typically sample in the center of each bit, the i.e. sampled point of start bit is (N/2) T apart from this data byte start bit trailing edge width, 8 follow-up data bit sampling pulses are spaced apart (N+1) T or NT, wherein the number that number is M, NT of (N+1) T is (9-M), and can arrange sampling pulse by interpolation method and be spaced apart (N+1) T or NT.
As one embodiment of the invention, decoding unit can use multiple decoder, demultiplier, state machine and control module to realize, and such as, uses the first demultiplier decremented data byte figure place j, and the second demultiplier successively decreases remainder M, and the 3rd demultiplier successively decreases the sampling period.
The state transition graph of this state machine can be:
0000→0001→0010→0011→0100→0101→0110→0111→1000→0000……。
Such as, the time width sampling start byte is 176T, then after processing except 9, obtain N=19, M=5, with being represented in binary as N=5 ' b10011, M=4 ' b0101.
During sampling start bit, sampled point is set as 5 ' b01001.Thereafter the data bit sampling period is respectively 55 ' b10100,35 ' b10011.Further, when distribution, use the mode inserting distribution, such as from start bit to the sampling period of the 8th data bit as shown in Figure 7 as far as possible.
Concrete sampling process is: start using the trailing edge of each data byte as sampled data, the sampled point of start bit is (N/2) T, if M=3, by state machine, interpolation is set, such as, arrange the 2nd sampling pulse and the 1st sampling pulse is spaced apart (N+1) T, 3rd sampling pulse and the 2nd sampling pulse be spaced apart (N+1) T, 4th sampling pulse and the 3rd sampling pulse be spaced apart (N+1) T, 5th sampling pulse and the 4th sampling pulse be spaced apart NT, 6th sampling pulse and the 5th sampling pulse be spaced apart NT, 7th sampling pulse and the 6th sampling pulse be spaced apart NT, 8th sampling pulse and the 7th sampling pulse be spaced apart NT, 9th sampling pulse and the 8th sampling pulse be spaced apart NT.Understandably, the selection at above-mentioned each sampling pulse interval can change setting by changing the setting of the State Transferring value of state machine, such as the 3rd sampling pulse and the 2nd sampling pulse it is set to NT, 8th sampling pulse and the 7th sampling pulse be set to (N+1) T, and often sending a sampling pulse, the first demultiplier, the second demultiplier and the 3rd demultiplier should correspondingly decremented data byte figure place j, remainder M and sampling periods.
The embodiment of the present invention is by counting the cycle of oscillation of oscillator signal within the time cycle of frame start byte low level figure place, and count value is carried out division arithmetic, obtain quotient and the remainder, the sampling period (sampling pulse interval) is determined according to quotient and the remainder, and then according to this sampling period, the data byte in each frame is sampled, it is decoded, accumulated error is not had to produce, without by promoting data transmission rate reduction solution code error, substantially increase the accuracy rate of decoding, and realize simple, low cost, good stability.
Fig. 3 shows the flow process of the host-host protocol coding/decoding method that another embodiment of the present invention provides, and for convenience of description, illustrate only part related to the present invention.
In step s 201, agitator generates oscillator signal OSC；
In step S202, controller detection frame start signal, and when frame start signal being detected, export sampling control signal；
In step S203, after division arithmetic unit receives sampling control signal, within the time cycle of frame start byte low level figure place, T cycle of oscillation of oscillator signal OSC is counted, and to count value NKbitsCarry out division arithmetic, export quotient and the remainder；
In step S204, generate the first sampling period and the second sampling period according to business N；
In step S205, data byte figure place j is write the first demultiplier, remainder M is write the second demultiplier；
In step S206, according to the first demultiplier and the result of successively decreasing of the second demultiplier, the first sampling period or the second sampling period are write the 3rd demultiplier；
In step S207, generate sampling pulse according to the result of successively decreasing of the 3rd demultiplier；
In step S208, according to sampling pulse to the data byte sampling in each frame in transmission data, it is decoded.
nullIn embodiments of the present invention，Cycle according to business N and oscillator signal OSC generates initial samples cycle (N/2) T，Data byte figure place j (being 9 in this example) is write the first demultiplier，And this initial samples cycle (N/2) T is write the 3rd demultiplier，First demultiplier is according to the operation that starts to subtract 1 of the cycle of oscillator signal OSC，Now the 3rd demultiplier also enters program of successively decreasing under the periodic Control of oscillator signal OSC，And first sampling pulse is exported when being decremented to 0，Simultaneously，The first sampling period (N+1) T and the second sampling period NT is generated according to business N，And remainder M is write the second demultiplier，Under the control of state machine, the first sampling period (N+1) T or the second sampling period NT is write the 3rd demultiplier，When state machine controls the first sampling period (N+1) T write three demultiplier，Second demultiplier all successively decreases 1，And the 3rd demultiplier successively decreases after being written into the first sampling period (N+1) T or the second sampling period NT，Until being decremented to second sampling pulse of output when 0，The most again the first sampling period (N+1) T or the second sampling period NT is write in the 3rd demultiplier，Until the first demultiplier is decremented to zero，And each time when the first sampling period (N+1) T is written in the 3rd demultiplier，Second demultiplier all subtracts 1，Until the second demultiplier is decremented to zero，So circulation will be sequentially output j sampling pulse，Complete the sampling operation of whole data byte.
If not using state machine, first the 3rd demultiplier can also be write the first sampling period (N+1) T, and judge whether the second demultiplier is zero, if the second demultiplier is not zero, then continue to write the first sampling period (N+1) T to the 3rd demultiplier, until the second demultiplier is decremented to zero, then the second sampling period NT is write the 3rd demultiplier, until the first demultiplier is decremented to zero.When the first demultiplier is decremented to zero, then it represents that this data byte has been sampled.
The embodiment of the present invention is by counting the cycle of oscillation of oscillator signal within the time cycle of frame start byte low level figure place, and count value is carried out division arithmetic, obtain quotient and the remainder, the sampling period (sampling pulse interval) is determined according to quotient and the remainder, and then according to this sampling period, the data byte in each frame is sampled, it is decoded, accumulated error is not had to produce, without by promoting data transmission rate reduction solution code error, substantially increase the accuracy rate of decoding, and realize simple, low cost, good stability.
Fig. 4 shows the structure of the host-host protocol decoding apparatus that the embodiment of the present invention provides, and for convenience of description, illustrate only part related to the present invention.
As one embodiment of the invention, this host-host protocol decoding apparatus is connected with driver element 202, including:
Agitator 102, is used for generating oscillator signal OSC；
In embodiments of the present invention, can be used for providing the oscillator signal OSC of T default cycle of oscillation at the built-in agitator of core Embedded 102, it is also possible to there is the oscillator signal of T default cycle of oscillation from external reception.
Controller 101, is used for detecting frame start signal, and when frame start signal being detected, exports sampling control signal, and the input of controller 101 receives transmission data；
In embodiments of the present invention, this frame start signal is first low level of each frame in transmission data, see the numbering 1 in Fig. 1, the low level time width of the frame start signal in each frame of controller detection transmission data, when low level time is more than Preset Time width, controller 101 confirms frame start signal to be detected, and exports sampling control signal.
As one embodiment of the invention, controller 101 can use state machine or time detection device to realize.
Division arithmetic unit 103, for after receiving sampling control signal, counted T cycle of oscillation (pulse) of oscillator signal OSC within the time cycle of frame start byte low level figure place, and to count value NKbitsCarrying out division arithmetic, export quotient and the remainder, the end that controls of division arithmetic unit 103 is connected with the outfan of controller 101, and the input of division arithmetic unit 103 is connected with the outfan of agitator 102；
In embodiments of the present invention, frame start byte is first character joint after the frame start signal transmitting each frame of data, division arithmetic unit 103 is after receiving sampling control signal, in units of cycle of oscillation, start using the trailing edge of frame start byte as counting, terminate using the rising edge of frame start byte as counting, in the Sampling time periods of frame start byte low level figure place, T cycle of oscillation is counted, obtain clock number (count value N corresponding with the Sampling time periods of frame start byte low level figure placeKbits), and to this count value NKbitsDo division arithmetic, obtain business N and remainder M, i.e. N K+M=Nkbits.Wherein, K is the figure place of the low level correspondence of frame start byte.So time width of start byte is NkbitsT, wherein T is agitator 102 cycle.
As one embodiment of the invention, division arithmetic unit 103 can be realized by divider sum counter.
Decoding unit 104, for determining the sampling period according to quotient and the remainder, to generate sampling pulse, and according to this sampling pulse, the data byte in transmission data is decoded, the end that controls of decoding unit 104 is connected with the outfan of controller 101, the first input end of decoding unit 104 is connected with the first outfan of division arithmetic unit 103, second input of decoding unit 104 is connected with the second outfan of division arithmetic unit 103, 3rd input of decoding unit 104 is connected with the input of controller 101 to receive transmission data, the clock end of decoding unit 104 is connected with the outfan of agitator 102, the outfan of decoding unit 104 is connected with driver element 202.
In embodiments of the present invention, decoding unit 104 is according to business N and remainder M, determine the sampling period, this sampling period includes two kinds of sampling pulse intervals, and then samples the data byte in each frame according to both sampling pulses interval, is decoded, above-mentioned data byte refers to the multiple bytes after each frame first byte, as a example by standard DMX512 agreement, the figure place of frame start byte is 9, and the figure place of each data byte is also 9 (wherein the 1st is 1 ' b0).Corresponding 9 sampling pulses of each data byte, each interpulse time width, controlled by N and M.Wherein, in order to sample accurately, typically sample in the center of each bit, the i.e. sampled point of start bit is (N/2) T apart from this data byte start bit trailing edge width, 8 follow-up data bit sampling pulses are spaced apart (N+1) T or NT, wherein the number that number is M, NT of (N+1) T is (9-M), and can arrange sampling pulse by interpolation method and be spaced apart (N+1) T or NT.
The embodiment of the present invention is by counting the cycle of oscillation of oscillator signal within the time cycle of frame start byte low level figure place, and count value is carried out division arithmetic, obtain quotient and the remainder, it is decoded according to quotient and the remainder, does not has accumulated error to produce, it is not necessary to reduce solution code error by promoting data transmission rate, substantially increase the accuracy rate of decoding, and realize simple, low cost, good stability.
Fig. 5 shows in the host-host protocol decoding that the embodiment of the present invention provides that the one of division arithmetic unit realizes exemplary circuit, for convenience of description, illustrate only part related to the present invention.
As one embodiment of the invention, this division arithmetic unit 103 uses divider sum counter to realize, division circuit can be realized by trigger, other logical devices can also be used to realize, as a example by standard DMX512 agreement, can use that four d type flip flops realize except nine circuit, wherein d type flip flop DFF1 and d type flip flop DFF2 constitutes except 3 circuit, and the State Transferring of this circuit is: 00 → 01 → 10 → 00 ...
D type flip flop DFF3 and d type flip flop DFF4 also forms except 3 circuit, and then constitutes except 9 circuit.
This division arithmetic unit 103 includes:
First d type flip flop DFF1, the second d type flip flop DFF2,3d flip-flop DFF3, four d flip-flop DFF4, the first nor gate OR1, the second nor gate OR2, binary counter 131 and logical operation module 132；
nullThe reset terminal RD1 of the first d type flip flop DFF1、The reset terminal RD2 of the second d type flip flop DFF2、The reset terminal RD3 of 3d flip-flop DFF3、The reset terminal RD4 of four d flip-flop DFF4 is the control end of division arithmetic unit 13 simultaneously，The input end of clock CK1 of the first d type flip flop DFF1、The input that input end of clock CK2 is division arithmetic unit 13 of the second d type flip flop DFF2，The forward outfan Q0 of the triggering end D2 and the first d type flip flop DFF1 of the second d type flip flop DFF2 connects，The first input end of the first nor gate OR1 and the forward outfan Q0 of the first d type flip flop DFF1 connect，Second input of the first nor gate OR1 and the forward outfan Q1 of the second d type flip flop DFF2 connect，The outfan of the first nor gate OR1 simultaneously with the triggering end D1 of the first d type flip flop DFF1、The input end of clock CK3 of 3d flip-flop DFF3、The input end of clock CK4 of four d flip-flop DFF4 connects，The forward outfan Q2 of the triggering end D4 and 3d flip-flop DFF3 of four d flip-flop DFF4 connects，The first input end of the second nor gate OR2 and the forward outfan Q2 of 3d flip-flop DFF3 connect，Second input of the second nor gate OR2 and the forward outfan Q3 of four d flip-flop DFF4 connect，The outfan of the second nor gate OR2 is connected with the triggering end D3 of 3d flip-flop DFF3 and the input end of clock CK of binary counter 131 simultaneously，The outfan of binary counter 131 is the first outfan of division arithmetic unit 13，The forward outfan Q0 of the first d type flip flop DFF1、The forward outfan Q1 of the second d type flip flop DFF2、The forward outfan Q2 of 3d flip-flop DFF3、The forward outfan Q3 of four d flip-flop DFF4 is successively in the first input end of logical operation module 132、Second input、3rd input、Four-input terminal connects，The outfan of logical operation module 132 is the second outfan of division arithmetic unit 13.
In embodiments of the present invention, after the oscillator signal OSC of agitator 102 output carries out counting and remove nine computings by four d type flip flop DFF1-DFF4, business N is obtained by binary counter 131, and remainder M needs to obtain after the logical transition of logical operation module 132, M binary number representation is M3M2M1M0, its logical transition formula is:
Wherein, Q0-Q3It is respectively the logic state of d type flip flop DFF1-DFF4 forward outfan output, and is obtained following corresponding form by this logical transition formula:
In embodiments of the present invention, logical operation module 132 can be formed by connecting according to the logical expression of remainder M by multiple gates, and here is omitted.
Fig. 6 shows in the host-host protocol decoding that the embodiment of the present invention provides that the one of decoding unit realizes exemplary construction, for convenience of description, illustrate only part related to the present invention.
As one embodiment of the invention, decoding unit 104 includes:
First demultiplier the 141, second demultiplier the 142, the 3rd demultiplier 143, control module 144, state machine 145 and decoder 146；
nullThe first input end of control module 144 is the first input end of decoding unit 104，Second input that second input is decoding unit 104 of control module 144，First outfan of control module 144 and the input of the first demultiplier 141 connect，Second outfan of control module 144 and the input of the second demultiplier 142 connect，3rd outfan of control module 144 and the input of the 3rd demultiplier 143 connect，The outfan of state machine 145 is connected with the 3rd input of control module 144，The clock end that clock end is decoding unit of control module 144，The outfan of control module 144 is connected with the first input end of decoder 146，The 3rd input that second input is decoding unit 104 of decoder 146，The outfan of decoder 146 is the outfan of decoding unit 104.
In embodiments of the present invention, control module 144 generates the first sampling period and the second sampling period according to business N, and data byte figure place j is write the first demultiplier 141, the remainder M of reception is write the second demultiplier 142, control module 144 is according to the first demultiplier 141 and result of successively decreasing of the second demultiplier 142, first sampling period (N+1) T or the second sampling period NT is write the 3rd demultiplier 143, and generate sampling pulse according to the result of successively decreasing of the 3rd demultiplier 143, according to this sampling pulse decoder 146 to the data byte sampling in each frame in transmission data, it is decoded.
As one embodiment of the invention, can arrange the first sampling period (N+1) T or the interpolation of the second sampling period NT by state machine 145, the state transition graph of this state machine 145 can be:
0000→0001→0010→0011→0100→0101→0110→0111→1000→0000……。
Such as, the time width sampling start byte is 176T, then after processing except 9, obtain N=19, M=5, with being represented in binary as N=5 ' b10011, M=4 ' b0101.
During sampling start bit, sampled point is set as 5 ' b01001.Thereafter the data bit sampling period is respectively 55 ' b10100,35 ' b10011.Further, when distribution, use the mode inserting distribution, such as from start bit to the sampling period of the 8th data bit as shown in Figure 7 as far as possible.
Concrete sampling process is: start using the trailing edge of each data byte as sampled data, the sampled point of start bit is (N/2) T, if M=3, by state machine, interpolation is set, such as, arrange the 2nd sampling pulse and the 1st sampling pulse is spaced apart (N+1) T, 3rd sampling pulse and the 2nd sampling pulse be spaced apart (N+1) T, 4th sampling pulse and the 3rd sampling pulse be spaced apart (N+1) T, 5th sampling pulse and the 4th sampling pulse be spaced apart NT, 6th sampling pulse and the 5th sampling pulse be spaced apart NT, 7th sampling pulse and the 6th sampling pulse be spaced apart NT, 8th sampling pulse and the 7th sampling pulse be spaced apart NT, 9th sampling pulse and the 8th sampling pulse be spaced apart NT.Understandably, the selection at above-mentioned each sampling pulse interval can change setting by changing the setting of the State Transferring value of state machine, such as the 3rd sampling pulse and the 2nd sampling pulse it is set to NT, 8th sampling pulse and the 7th sampling pulse be set to (N+1) T, and often sending a sampling pulse, the first demultiplier, the second demultiplier and the 3rd demultiplier should correspondingly decremented data byte figure place j, remainder M and sampling periods.
Concrete decrementing procedure is:
nullControl module generates initial samples cycle (N/2) T according to the cycle of business N and oscillator signal OSC，Data byte figure place j (being 9 in this example) is write the first demultiplier 141，And this initial samples cycle (N/2) T is write the 3rd demultiplier 143，First demultiplier 141 is according to the operation that starts to subtract 1 of the cycle of oscillator signal OSC，Now the 3rd demultiplier 143 also enters program of successively decreasing under the periodic Control of oscillator signal OSC，And first sampling pulse is exported when being decremented to 0，Simultaneously，Control module 144 generates the first sampling period (N+1) T and the second sampling period NT according to business N，And remainder M is write the second demultiplier 142，Under the control of state machine 145, the first sampling period (N+1) T or the second sampling period NT is write the 3rd demultiplier 143 by control module 144，When state machine 145 controls the first sampling period (N+1) T write three demultiplier 143，Second demultiplier 142 all successively decreases 1，And the 3rd demultiplier 143 successively decreases after being written into the first sampling period (N+1) T or the second sampling period NT，Until being decremented to second sampling pulse of output when 0，The most again by control module 144, first sampling period (N+1) T or the second sampling period NT is write in the 3rd demultiplier 143，Until the first demultiplier 141 is decremented to zero，And each time when the first sampling period (N+1) T is written in the 3rd demultiplier 143，Second demultiplier 142 all subtracts 1，Until the second demultiplier 142 is decremented to zero，So circulation will be sequentially output j sampling pulse，Complete the sampling operation of whole data byte.
If not using state machine 145, first the 3rd demultiplier 143 can also be write the first sampling period (N+1) T, and judge whether the second demultiplier 142 is zero, if the second demultiplier 142 is not zero, then continue to write the first sampling period (N+1) T to the 3rd demultiplier 143, until the second demultiplier 142 is decremented to zero, then the second sampling period NT is write the 3rd demultiplier 143, until the first demultiplier 141 is decremented to zero.
When the first demultiplier 141 is decremented to zero, then it represents that this data byte has been sampled.
If it should be noted that last 1 of the binary system of N is 1, and M ≠ 0, then M can be subtracted 1, and the sampled point of start bit is [N/2]+1.Wherein [N/2] refers to its integer part.
The embodiment of the present invention is by counting the cycle of oscillation of oscillator signal within the time cycle of frame start byte low level figure place, and count value is carried out division arithmetic, obtain quotient and the remainder, it is decoded according to quotient and the remainder, does not has accumulated error to produce, it is not necessary to reduce solution code error by promoting data transmission rate, substantially increase the accuracy rate of decoding, and realize simple, low cost, good stability.
These are only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent and improvement etc. made within the spirit and principles in the present invention, should be included within the scope of the present invention.
Claims (7)
1. a host-host protocol coding/decoding method, it is characterised in that described method comprises the steps:
Generate oscillator signal；
Detection frame start signal, and when described frame start signal being detected, export sampling control signal；
After receiving described sampling control signal, to institute within the time cycle of frame start byte low level figure place
The cycle of oscillation stating oscillator signal counts, and described count value carries out division arithmetic, output business and remaining
Number N K+M=Nkbits, wherein N is business, and M is remainder, NKbitsFor count value, K is frame banner word
Save the figure place of low level correspondence；
Determine that sampling period, described sampling period include two kinds of sampling pulses interval (N+1) according to quotient and the remainder
T or NT, wherein the number that number is M, NT of (N+1) T is (K-M), according to both
Data byte in each frame is sampled by sampling pulse interval, is decoded, to generate sampling pulse, and root
According to described sampling pulse, the data byte in transmission data is decoded.
2. the method for claim 1, it is characterised in that described according to quotient and the remainder determine sampling week
Phase, to generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded
Step particularly as follows:
The first sampling period and the second sampling period is generated according to described business；
Data byte figure place is write the first demultiplier, described remainder is write the second demultiplier；
According to described first demultiplier and the result of successively decreasing of described second demultiplier, by described first sampling period
Or described second sampling period write the 3rd demultiplier；
Result of successively decreasing according to described 3rd demultiplier generates sampling pulse；
According to described sampling pulse to the data byte sampling in each frame in transmission data, it is decoded.
3. a host-host protocol decoding apparatus, described device is connected with driver element, including:
Agitator, is used for generating oscillator signal；
Controller, is used for detecting frame start signal, and when described frame start signal being detected, output sampling
Control signal, the input of described controller receives transmission data；
Division arithmetic unit, for after receiving described sampling control signal, in frame start byte low level
In the time cycle of figure place, the cycle of oscillation to described oscillator signal counts, and carries out described count value
Division arithmetic, exports quotient and the remainder N K+M=Nkbits, wherein N is business, and M is remainder, NKbits
For count value, K is the figure place of the low level correspondence of frame start byte, the control end of described division arithmetic unit
It is connected with the outfan of described controller, the input of described division arithmetic unit and the output of described agitator
End connects；
According to described quotient and the remainder, decoding unit, for determining that sampling period, described sampling period include two kinds
Sampling pulse interval (N+1) T or NT, wherein the number that number is M, NT of (N+1) T is
(K-M), according to both sampling pulses interval, the data byte in each frame is sampled, is decoded,
To generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded, institute
First outfan of the first input end and described division arithmetic unit of stating decoding unit is connected, and described decoding is single
Second input of unit is connected with the second outfan of described division arithmetic unit, the 3rd of described decoding unit
Input be connected with the input of described controller with receive transmission data, the clock end of described decoding unit with
The outfan of described agitator connects, and the outfan of described decoding unit is connected with described driver element.
4. device as claimed in claim 3, it is characterised in that described controller is state machine or time inspection
Survey device.
5. device as claimed in claim 3, it is characterised in that described division arithmetic unit includes:
First d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, first or
Not gate, the second nor gate, binary counter and logical operation module；
The reset terminal of described first d type flip flop, the reset terminal of described second d type flip flop, described 3rd D
The reset terminal of trigger, the reset terminal of described four d flip-flop are the control of described division arithmetic unit simultaneously
End, the input end of clock of described first d type flip flop, the input end of clock of described second d type flip flop are described
The input of division arithmetic unit, the triggering end of described second d type flip flop is with described first d type flip flop just
Connecting to outfan, the first input end of described first nor gate exports with the forward of described first d type flip flop
End connects, and the second input of described first nor gate is connected with the forward outfan of described second d type flip flop,
The outfan of described first nor gate triggers with the triggering end of described first d type flip flop, described 3rd D simultaneously
The input end of clock of device, the input end of clock of described four d flip-flop connect, described four d flip-flop
Trigger end to be connected with the forward outfan of described 3d flip-flop, the first input end of described second nor gate
Being connected with the forward outfan of described 3d flip-flop, the second input of described second nor gate is with described
The forward outfan of four d flip-flop connects, the outfan of described second nor gate simultaneously with described 3rd D
The input end of clock triggering end and described binary counter of trigger connects, described binary counter
Outfan is the first outfan of described division arithmetic unit, the forward outfan of described first d type flip flop,
The forward outfan of described second d type flip flop, the forward outfan of described 3d flip-flop, the described 4th
The forward outfan of d type flip flop successively in the first input end of described logical operation module, the second input,
3rd input, four-input terminal connect, and the outfan of described logical operation module is described division arithmetic list
Second outfan of unit.
6. device as claimed in claim 3, it is characterised in that described decoding unit includes:
First demultiplier, the second demultiplier, the 3rd demultiplier, control module, state machine and decoder；
The first input end of described control module is the first input end of described decoding unit, described control module
The second input that the second input is described decoding unit, the first outfan of described control module and institute
The input stating the first demultiplier connects, the second outfan of described control module and described second demultiplier
Input connects, and described 3rd outfan of described control module is connected with the input of described 3rd demultiplier,
The outfan of described state machine is connected with the 3rd input of described control module, the clock of described control module
The clock end that end is described decoding unit, the outfan of described control module inputs with the first of described decoder
End connects, the 3rd input that the second input is described decoding unit of described decoder, described decoder
The outfan that outfan is described decoding unit.
7. a host-host protocol decoding chip, it is characterised in that described chip includes such as claim 3 to 6
Host-host protocol decoding apparatus described in any one.
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| CN201310513788.1A CN103561008B (en) | 2013-10-25 | 2013-10-25 | A kind of host-host protocol coding/decoding method, device and host-host protocol decoding chip |
| US14/351,137 US9264215B2 (en) | 2013-10-25 | 2014-01-10 | Transmission protocol decoding method, device, and transmission protocol decoding chip |
| PCT/CN2014/070454 WO2015058473A1 (en) | 2013-10-25 | 2014-01-10 | Decoding method and apparatus of transmission protocol and transmission protocol decoding chip |
| EP14711903.6A EP2887616A4 (en) | 2013-10-25 | 2014-01-10 | Decoding method and apparatus of transmission protocol and transmission protocol decoding chip |
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| CN105549681A (en) * | 2015-12-22 | 2016-05-04 | 武汉华中数控股份有限公司 | Method and system for accurately outputting pulse number in clock domain crossing manner |
| CN107452309B (en) * | 2017-08-31 | 2023-04-25 | 深圳市明微电子股份有限公司 | Decoding circuit of self-adaptive data frequency |
| CN110635854A (en) * | 2019-10-24 | 2019-12-31 | 深圳市富满电子集团股份有限公司 | Transmission protocol self-adaptive decoding system and method |
| CN112737569B (en) * | 2020-12-24 | 2023-12-01 | 浙江大学 | Digital decoding circuit based on nine-system carry circuit |
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| CN1689266A (en) * | 2002-10-18 | 2005-10-26 | 皇家飞利浦电子股份有限公司 | Data processing apparatus that identifies a communication clock frequency |
| US7342984B1 (en) * | 2003-04-03 | 2008-03-11 | Zilog, Inc. | Counting clock cycles over the duration of a first character and using a remainder value to determine when to sample a bit of a second character |
| CN203645707U (en) * | 2013-10-25 | 2014-06-11 | 深圳市明微电子股份有限公司 | Transmission protocol decoding device and transmission protocol decoding chip |
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| FR2845783A1 (en) * | 2002-10-15 | 2004-04-16 | St Microelectronics Sa | Clock generator for dividing primary frequency by nominated decimal number, comprises a modulation circuit, a modulation distribution circuit and two divisors with down counters |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1689266A (en) * | 2002-10-18 | 2005-10-26 | 皇家飞利浦电子股份有限公司 | Data processing apparatus that identifies a communication clock frequency |
| US7342984B1 (en) * | 2003-04-03 | 2008-03-11 | Zilog, Inc. | Counting clock cycles over the duration of a first character and using a remainder value to determine when to sample a bit of a second character |
| CN203645707U (en) * | 2013-10-25 | 2014-06-11 | 深圳市明微电子股份有限公司 | Transmission protocol decoding device and transmission protocol decoding chip |
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