CN103561008A - Method and device for decoding transport protocol and transport protocol decoding chip - Google Patents
Method and device for decoding transport protocol and transport protocol decoding chip Download PDFInfo
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- CN103561008A CN103561008A CN201310513788.1A CN201310513788A CN103561008A CN 103561008 A CN103561008 A CN 103561008A CN 201310513788 A CN201310513788 A CN 201310513788A CN 103561008 A CN103561008 A CN 103561008A
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Abstract
The invention belongs to the field of communication, and provides a method and device for decoding a transport protocol and a transport protocol decoding chip. The method comprises the following steps that an oscillator signal is generated; a frame start signal is detected, and a sampling control signal is output when the frame start signal is detected; after the sampling control signal is received, the oscillation period of the oscillator signal is counted within the time period of a frame start byte low-level digit, a division operation is carried out on count values, and a quotient and a remainder are output; a sampling period is determined according to the quotient and the remainder to generate a sampling pulse, and a data byte is decoded according to the sampling pulse. The oscillation period of the oscillator signal is counted within the time period of the frame start byte low-level digit, the division operation is carried out on the count values to obtain the quotient and the remainder, decoding is carried out according to the quotient and the remainder, no accumulation error is generated, decoding accuracy is greatly improved, achievement is simple, cost is low, and stability is good.
Description
Technical field
The invention belongs to the communications field, relate in particular to a kind of host-host protocol coding/decoding method, device and host-host protocol decoding chip.
Background technology
Along with the application of digital technology and computer technology and universal, there is computer Control Console, and successively occurred simulation and the digital communication protocols such as D54, AVAB, CMX, PMX, EMX.Due to above consensus standard Shi Ge manufacturer consensus standard separately, thereby the compatibility between them is bad, the mutual general existing problems between equipment.Afterwards, in order to solve the problem of each producer's equipment interoperability, U.S. arenas technological associations (United State Institute for Theatre Technology, USITT) had formulated DMX512 agreement in early 1980s.DMX512 agreement is a kind of digital multiplex (Digital Multiplex, DMX) agreement.After agreement is formulated, through revising, USITT by DMX512 agreement standard more, has formed DMX512-1990 in nineteen ninety.This control protocol is supported in nearly all light and stage equipment factory commercial city at present, and as the digital light data protocol of extensive employing, DMX512-1990 also becomes the international standard that light is controlled.
The unification of DMX512 agreement can interconnect the equipment of each producer, and compatibility improves greatly.Meanwhile, because DMX512 agreement adopts serial mode, transmit digital signal, between control platform and equipment, need only a holding wire, greatly simplified the connecting line between control desk and equipment.
DMX512 agreement can realize the brightness regulation to light units by send packet in bus.Agreement has all been done very strict regulation to the sequential of every part of packet.Every byte has 11 bit data, 1 low level start bit, 8 bit data positions and 2 high level position of rests.The brightness data that one frame data comprise 1 address, the 1st frame is the data of the 1st address, and the 2nd frame is the data of the 2nd address, and by that analogy, 512 frames can transmit the data of 512 addresses.DMX512 sequential chart as shown in Figure 1.
Be described as follows table:
| Numbering | Explanation | Time slot requirement |
| 1 | Frame is initial or finish | |
| 2 | Frame beginning flag position | 8us |
| 3 | 1 complete bytes | 11bits data |
| 4 | Byte beginning flag position, must be " 0 " | 1bits data |
| 5 | The LSB of byte | 1bits data |
| 6 | The MSB of byte | 1bits data |
| 7 | Byte end mark position, must be " 1 " | 1bits data |
| 8 | Byte end mark position, must be " 1 " | 1bits data |
| 9 | Time width between adjacent byte, must be " 1 " | <1s |
| 10 | Consecutive frame time width, must be " 1 " | <1s |
| 11 | The start byte data of every frame data, must be complete " 0 " | 8bits data |
| 12 | 1 byte data, main frame sends, and slave receives | 8bits data |
| 13 | Complete 1 frame | - |
In the DMX512 agreement of standard, the data width of each bits is fixed, and is 4us, and namely message transmission rate is that 250Kbps(transmits 250Kbits data each second).
Existing protocol-decoding mode is:
By monitoring the start byte time width of every frame data, determine the time width of follow-up each byte.The DMX512 agreement of standard of take is example, the consisting of of start byte: 1 beginning flag position (" 0 ")+8 byte data positions (8 " 0 ")+2 end mark positions (2 " 1 ").According to standard DMX512 agreement, the width of this start byte is 44us.Because 9 bits " 0 " in start byte are between frame beginning flag position (" 1 ") and 2 byte end mark positions (2 " 1 "), the relatively good monitoring of time width of these 9 bits " 0 " so.
The existing way first, according to sampled data, is selected the mode in sampling period, for example, by internal oscillator, produces several sampling period T1, T2, and T3, by the sampling to start byte, chooses optimal a kind of sampling period.The method is simple, but for selecting the identical default sampling period under multiple sampled data, makes to separate code error very large, particularly can not accomplish the sampling all standing after frequency upgrading.That is to say, in some frequency range, can sample, in some frequency range, can not sample, for example, at 200～300Kbps, in 400～500Kbps, can sample, but can not sample in 300～400Kbps.
Another way is in slave, to comprise a built-in oscillator (cycle is T), and by 9 of start byte bits " 0 " time counting, for example, the time is T
9bits, divided by 9, obtain the time width T of each bit
bit.Certainly, also can in sampling process, carry out division arithmetic.And because sampling adopts digital processing mode, this time width T conventionally
bitshould be the integral multiple N*T of cycle oscillator to avoid error to produce, and in actual conditions, N is generally T
9bits/ 9 obtain, and are difficult to control as aliquot, suppose T
9bits/ 9=8.6.
Conventionally adopt at present the way that retains integer-bit, so above-mentioned data, choose N=8, when carrying out each byte data decoding, have accumulated error.As shown in Figure 1, generally can be in the sampling of the center of data byte, sample is set to N(1/2+1) T, like this, when the start bit of each byte of decoding, have the error of [(8.6-8)/2] T=0.3T; When the 1st data bit of each byte of decoding, have the error of [(8.6-8) * 1.5] T=0.9T; By that analogy, when the 8th data bit of each byte of decoding, accumulated error is: the error of [(8.6-8) * 8.5] T=4.1T; Especially, under extreme case, work as T
9bits/ 9=8.99, when the 8th data bit of each byte of decoding, accumulated error is about 8.5T, can produce decoding error like this.Therefore generally choose sampling location for (N/2) T>8.5T.With guarantee decoding each byte the 8th data bit time, can not sample in the 7th data bit.
Yet to the sampling of start byte time width, the frequency that improves constantly slave oscillator is more high better for more accurately.Because frequency is higher, adopt and retain the resulting maximum accumulated error of rounding-off method, can be less for the sampling period.In above-mentioned example, in standard DMX512 agreement, the time width of each bit is 4us, if N=16, the cycle of internal oscillator is 4us/16=0.25us so, and frequency is 4MHz.
In actual applications, guaranteeing, in refresh rate situation, need to connect more slave.That is to say, message transmission rate need to be promoted.If separate the code of higher frequency on above-mentioned internal oscillator frequency basis, such as decoding rate reaches 500Kbps, so maximum accumulated error is still 8.5T, and if N=8, will decoding error.Only have so by promoting the way of chip internal oscillator frequency.Oscillator frequency rises to 8MHz from 4MHz, like this N=16.By that analogy, if need decoding rate to reach 1Mbps, the frequency that needs so internal oscillator is at least 16MHz.But on existing integrated circuit basis, reach the frequency of megahertz, frequency is larger, the stability that chip is produced at different times is more difficult to ensure card.
Therefore, the accuracy rate that existing host-host protocol coding/decoding method causes being difficult to assurance decoding due to the accumulated error in sampling period, and by promoting the way of chip internal oscillator frequency, promote data transmission rate to separate code error cost high to reduce, realize complicated, poor stability.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of host-host protocol coding/decoding method, is intended to solve current decoder method and exists sampling period accumulated error to cause the inaccuracy of decoding, and realization is complicated, cost is high, the problem of poor stability.
The embodiment of the present invention is achieved in that a kind of host-host protocol coding/decoding method, and described method comprises the steps:
Generate oscillator signal;
Detect frame start signal, and when described frame start signal being detected, output sampling control signal;
Receive after described sampling control signal, within the time cycle of frame start byte low level figure place, to counting the cycle of oscillation of described oscillator signal, and described count value is carried out to division arithmetic, output quotient and the remainder;
According to quotient and the remainder, determine the sampling period, to generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded.
Another object of the embodiment of the present invention is to provide a kind of host-host protocol decoding device, and described device is connected with driver element, comprising:
Oscillator, for generating oscillator signal;
Controller, for detection of frame start signal, and when described frame start signal being detected, output sampling control signal, the input of described controller receives transmission data;
Division arithmetic unit, for after receiving described sampling control signal, within the time cycle of frame start byte low level figure place to counting the cycle of oscillation of described oscillator signal, and described count value is carried out to division arithmetic, output quotient and the remainder, the control end of described division arithmetic unit is connected with the output of described controller, and the input of described division arithmetic unit is connected with the output of described oscillator;
Decoding unit, for determining the sampling period according to described quotient and the remainder, to generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded, the first input end of described decoding unit is connected with the first output of described division arithmetic unit, the second input of described decoding unit is connected with the second output of described division arithmetic unit, the 3rd input of described decoding unit is connected to receive transmission data with the input of described controller, the clock end of described decoding unit is connected with the output of described oscillator, the output of described decoding unit is connected with described driver element.
Another object of the embodiment of the present invention is to provide a kind of host-host protocol decoding chip that adopts above-mentioned host-host protocol decoding device.
The embodiment of the present invention by the time cycle in frame start byte low level figure place to counting the cycle of oscillation of oscillator signal, and count value is carried out to division arithmetic, obtain quotient and the remainder, according to quotient and the remainder, decode, do not have accumulated error to produce, without reducing solution code error by promoting data transmission rate, greatly improved the accuracy rate of decoding, and realize simply, cost is low, good stability.
Accompanying drawing explanation
Fig. 1 is DMX512 agreement sequential decoding schematic diagram;
The flow chart of the host-host protocol coding/decoding method that Fig. 2 provides for one embodiment of the invention;
The flow chart of the host-host protocol coding/decoding method that Fig. 3 provides for another embodiment of the present invention;
The structure chart of the host-host protocol decoding device that Fig. 4 provides for the embodiment of the present invention;
A realization example circuit diagram of division arithmetic unit in the host-host protocol decoding device that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 shows a realization example structure chart of decoding unit in the host-host protocol decoding device that the embodiment of the present invention provides;
Fig. 7 realizes the flow chart of host-host protocol coding/decoding method for what the embodiment of the present invention provided by state machine.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The embodiment of the present invention within the time cycle of frame start byte low level figure place to counting the cycle of oscillation of oscillator signal, and count value is carried out to division arithmetic, according to quotient and the remainder, decode, do not have accumulated error to produce, greatly improved the accuracy rate of decoding.
Fig. 2 shows the flow process of the host-host protocol coding/decoding method that one embodiment of the invention provides, and for convenience of explanation, only shows part related to the present invention.
In step S101, oscillator generates oscillator signal OSC;
In step S102, controller detects frame start signal, and when frame start signal being detected, output sampling control signal;
In embodiments of the present invention, this frame start signal is first low level of each frame in transmission data, referring to the numbering 1 in Fig. 1, the low level time width of the frame start signal in each frame of controller detected transmission data, when low level time is greater than Preset Time width, controller confirms to detect frame start signal, and export sampling control signal, for example, in standard DMX512 agreement, this frame start signal low level time width is greater than 88us, and for class DMX512 agreement, controller also can be set and detect Preset Time width according to the frame start signal low level time width of this agreement.
In step S103, division arithmetic unit receives after sampling control signal, and T cycle of oscillation to oscillator signal OSC within the time cycle of frame start byte low level figure place counts, and to count value N
kbitscarry out division arithmetic, output quotient and the remainder;
In embodiments of the present invention, frame start byte for the frame start signal of transmission data each frame after first byte (comprise 1 low level start bit, 8 bit data positions and 2 high level position of rests), referring to first numbering 3 parts that indicate in Fig. 1, division arithmetic unit is after receiving sampling control signal, take cycle of oscillation as unit, the trailing edge of frame start byte of usining starts as counting, the rising edge of frame start byte of usining finishes as counting, within the cycle in sampling time of frame start byte low level figure place to cycle of oscillation T count, obtain clock number (the count value N corresponding with the cycle in sampling time of frame start byte low level figure place
kbits), the time width of start byte is N so
kbitst, wherein T is cycle oscillator.
And then division arithmetic unit is to this count value N
kbitsdo division arithmetic, obtain business N and remainder M, i.e. NK+M=N
kbits.Wherein, K is the figure place of the low level correspondence of frame start byte.
The standard DMX512 agreement of take is example, because this protocol frame start byte low level bit is 9 (with reference to figure 1 and tables 1), division arithmetic unit is after receiving sampling control signal and cycle of oscillation T, the trailing edge of frame start byte of usining starts as counting, T cycle of oscillation of the oscillator of take output is unit, the rising edge of start byte of usining finishes as counting, the time width N of frame start byte detected
9bitst, to N
9bitsdo except 9 computings, obtain business N and remainder M, wherein 9N+M=N
9bits.
Certainly, in class DMX512 agreement, can set arbitrarily the low level time width N of frame start byte
kbitsthe figure place K that T and low level are corresponding, also can set arbitrarily transmitted data byte figure place j.Accordingly, division arithmetic is N
kbits÷ K, it is comprised of two parts, and wherein N is business, and M is remainder, and NK+M=N
kbits, wherein M is 0 to the arbitrary integer in (k-1).Due to conventionally, in the sampling of the center of data byte, therefore the sampling period of follow-up start bit is (N/2) T, and the sampling period in data byte (having j position) is T
samp=TN or T
samp=T (N+1), wherein has (j-X) individual T
sampa=TN and X T
samp=T (N+1), wherein, X=M (j ÷ K).
In step S104, decoding unit is determined the sampling period according to quotient and the remainder, to generate sampling pulse, and according to this sampling pulse, the data byte in transmission data is decoded.
In embodiments of the present invention, decoding unit is according to business N and remainder M, determine the sampling period, this sampling period comprises two kinds of sampling pulse intervals, and then according to these two kinds of sampling pulse intervals, the data byte in each frame is sampled, and decodes, above-mentioned data byte refers to a plurality of bytes after each frame first byte, the standard DMX512 agreement of take is example, and the figure place of frame start byte is 9, the figure place of each data byte also for 9(wherein the 1st be 1 ' b0).Corresponding 9 sampling pulses of each data byte, the time width that each is interpulse, controls by N and M.Wherein, in order to sample accurately, generally in the sampling of the center of each bit, the sampled point that is start bit is (N/2) T apart from this data byte start bit trailing edge width, 8 follow-up data bit sampling pulses are spaced apart (N+1) T or NT, wherein the number of N+1 is M, and the number of N is (9-M), and can sampling pulse be set by interpolation method and be spaced apart (N+1) T or NT.
As one embodiment of the invention, decoding unit can adopt a plurality of decoders, demultiplier, state machine and control module to realize, and for example, adopts the first demultiplier data byte figure place j that successively decreases, the second demultiplier remainder M that successively decreases, and the 3rd demultiplier successively decreases the sampling period.
The state transition graph of this state machine can be:
0000→0001→0010→0011→0100→0101→0110→0111→1000→0000……。
For example, the time width that samples start byte is 176T, through except after 9 processing, obtains N=19 so, and M=5, is shown N=5 ' b10011 with binary form, M=4 ' b0101.
During sampling start bit, sampled point is set as to 5 ' b01001.Thereafter the data bit sampling period is respectively 5 ' b10100 5 times, 35 ' b10011.And, when distributing, adopt the mode distributing of inserting as far as possible, for example from sampling period of start bit to the 8 data bit as shown in Figure 7.
Concrete sampling process is: the trailing edge of each data byte of usining starts as sampled data, the sampled point of start bit is (N/2) T, if M=3, by state machine, interpolation is set, for example, what the 2nd sampling pulse and the 1st sampling pulse were set is spaced apart (N+1) T, the 3rd sampling pulse and the 2nd sampling pulse be spaced apart (N+1) T, the 4th sampling pulse and the 3rd sampling pulse be spaced apart (N+1) T, the 5th sampling pulse and the 4th sampling pulse be spaced apart NT, the 6th sampling pulse and the 5th sampling pulse be spaced apart NT, the 7th sampling pulse and the 6th sampling pulse be spaced apart NT, the 8th sampling pulse and the 7th sampling pulse be spaced apart NT, the 9th sampling pulse and the 8th sampling pulse be spaced apart NT.Understandably, the selection at above-mentioned each sampling pulse interval can change setting by changing the setting of the state conversion value of state machine, for example, by the NT that is set to of the 3rd sampling pulse and the 2nd sampling pulse, the 8th sampling pulse and the 7th sampling pulse be set to (N+1) T, and often sending sampling pulse one time, the first demultiplier, the second demultiplier and the 3rd demultiplier should correspondingly successively decrease data byte figure place j, remainder M and sampling period.
The embodiment of the present invention by the time cycle in frame start byte low level figure place to counting the cycle of oscillation of oscillator signal, and count value is carried out to division arithmetic, obtain quotient and the remainder, according to quotient and the remainder, determine the sampling period (sampling pulse interval), and then according to this sampling period to the data byte sampling in each frame, decode, do not have accumulated error to produce, without reducing solution code error by promoting data transmission rate, greatly improved the accuracy rate of decoding, and realize simply, cost is low, good stability.
Fig. 3 shows the flow process of the host-host protocol coding/decoding method that another embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
In step S201, oscillator generates oscillator signal OSC;
In step S202, controller detects frame start signal, and when frame start signal being detected, output sampling control signal;
In step S203, division arithmetic unit receives after sampling control signal, and T cycle of oscillation to oscillator signal OSC within the time cycle of frame start byte low level figure place counts, and to count value N
kbitscarry out division arithmetic, output quotient and the remainder;
In step S204, according to business N, generate the first sampling period and the second sampling period;
In step S205, data byte figure place j is write to the first demultiplier, remainder M is write to the second demultiplier;
In step S206, according to the result of successively decreasing of the first demultiplier and the second demultiplier, the first sampling period or the second sampling period are write to the 3rd demultiplier;
In step S207, according to the result of successively decreasing of the 3rd demultiplier, generate sampling pulse;
In step S208, according to sampling pulse, to the data byte sampling in each frame in transmission data, decode.
In embodiments of the present invention, generate (N/2) T of initial sampling period according to the cycle of business N and oscillator signal OSC, to in this example of data byte figure place j(, be 9) write the first demultiplier, and this initial sampling period (N/2) T is write to the 3rd demultiplier, the first demultiplier starts to subtract 1 operation according to the cycle of oscillator signal OSC, now the 3rd demultiplier also enters the program of successively decreasing under the periodic Control of oscillator signal OSC, and export first sampling pulse being decremented at 0 o'clock, simultaneously, according to business N, generate the first sampling period (N+1) T and the second sampling period NT, and remainder M is write to the second demultiplier, under the control of state machine, the first sampling period (N+1) T or the second sampling period NT are write to the 3rd demultiplier, when state machine controls that the first sampling period, (N+1) T write the 3rd demultiplier, the second demultiplier all successively decreases 1, and the 3rd demultiplier successively decreases after being written into the first sampling period (N+1) T or the second sampling period NT, until be decremented at 0 o'clock, export second sampling pulse, again the first sampling period (N+1) T or the second sampling period NT are write in the 3rd demultiplier simultaneously, until the first demultiplier is decremented to zero, and each time in the first sampling period, (N+1) T was written into the 3rd demultiplier time, the second demultiplier all subtracts 1, until the second demultiplier is decremented to zero, so circulation will be exported j sampling pulse successively, complete the sampling operation of whole data byte.
If do not adopt state machine, also can first to third state machine, write the first sampling period (N+1) T, and judge whether the second demultiplier is zero, if the second demultiplier is non-vanishing, continue to write the first sampling period (N+1) T to the 3rd demultiplier, until the second demultiplier is decremented to zero, then writes the 3rd demultiplier by the second sampling period NT, until the first demultiplier is decremented to zero.When the first demultiplier is decremented to zero, represent that this data byte sampled.
The embodiment of the present invention by the time cycle in frame start byte low level figure place to counting the cycle of oscillation of oscillator signal, and count value is carried out to division arithmetic, obtain quotient and the remainder, according to quotient and the remainder, determine the sampling period (sampling pulse interval), and then according to this sampling period to the data byte sampling in each frame, decode, do not have accumulated error to produce, without reducing solution code error by promoting data transmission rate, greatly improved the accuracy rate of decoding, and realize simply, cost is low, good stability.
Fig. 4 shows the structure of the host-host protocol decoding device that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
As one embodiment of the invention, this host-host protocol decoding device is connected with driver element 202, comprising:
In embodiments of the present invention, can be at the built-in oscillator 102 of core Embedded, be used to provide the oscillator signal OSC of default cycle of oscillation of T, also can receive from outside the oscillator signal with default cycle of oscillation of T.
In embodiments of the present invention, this frame start signal is first low level of each frame in transmission data, referring to the numbering 1 in Fig. 1, the low level time width of the frame start signal in each frame of controller detected transmission data, when low level time is greater than Preset Time width, controller 101 is confirmed frame start signal to be detected, and exports sampling control signal.
As one embodiment of the invention, controller 101 can adopt state machine or time detection device to realize.
In embodiments of the present invention, frame start byte for the frame start signal of transmission data each frame after first byte, division arithmetic unit 103 is after receiving sampling control signal, take cycle of oscillation as unit, the trailing edge of frame start byte of usining starts as counting, the rising edge of frame start byte of usining finishes as counting, within the cycle in sampling time of frame start byte low level figure place to cycle of oscillation T count, obtain clock number (the count value N corresponding with the cycle in sampling time of frame start byte low level figure place
kbits), and to this count value N
kbitsdo division arithmetic, obtain business N and remainder M, i.e. NK+M=N
kbits.Wherein, K is the figure place of the low level correspondence of frame start byte.The time width of start byte is N so
kbitst, wherein T is 102 cycles of oscillator.
As one embodiment of the invention, division arithmetic unit 103 can be realized by divider sum counter.
Decoding unit 104, for determining the sampling period according to quotient and the remainder, to generate sampling pulse, and according to this sampling pulse, the data byte in transmission data is decoded, the control end of decoding unit 104 is connected with the output of controller 101, the first input end of decoding unit 104 is connected with the first output of division arithmetic unit 103, the second input of decoding unit 104 is connected with the second output of division arithmetic unit 103, the 3rd input of decoding unit 104 is connected to receive transmission data with the input of controller 101, the clock end of decoding unit 104 is connected with the output of oscillator 102, the output of decoding unit 104 is connected with driver element 202.
In embodiments of the present invention, decoding unit 104 is according to business N and remainder M, determine the sampling period, this sampling period comprises two kinds of sampling pulse intervals, and then according to these two kinds of sampling pulse intervals, the data byte in each frame is sampled, and decodes, above-mentioned data byte refers to a plurality of bytes after each frame first byte, the standard DMX512 agreement of take is example, and the figure place of frame start byte is 9, the figure place of each data byte also for 9(wherein the 1st be 1 ' b0).Corresponding 9 sampling pulses of each data byte, the time width that each is interpulse, controls by N and M.Wherein, in order to sample accurately, generally in the sampling of the center of each bit, the sampled point that is start bit is (N/2) T apart from this data byte start bit trailing edge width, 8 follow-up data bit sampling pulses are spaced apart (N+1) T or NT, wherein the number of N+1 is M, and the number of N is (9-M), and can sampling pulse be set by interpolation method and be spaced apart (N+1) T or NT.
The embodiment of the present invention by the time cycle in frame start byte low level figure place to counting the cycle of oscillation of oscillator signal, and count value is carried out to division arithmetic, obtain quotient and the remainder, according to quotient and the remainder, decode, do not have accumulated error to produce, without reducing solution code error by promoting data transmission rate, greatly improved the accuracy rate of decoding, and realize simply, cost is low, good stability.
Fig. 5 shows a realization example circuit of division arithmetic unit in the host-host protocol decoding that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
As one embodiment of the invention, this division arithmetic unit 103 adopts divider sum counter to realize, can realize division circuit by trigger, also can adopt other logical devices to realize, the standard DMX512 agreement of take is example, nine circuit that remove that can adopt four d type flip flops realizations, wherein d type flip flop DFF1 and d type flip flop DFF2 have formed except 3 circuit, and the state of this circuit is converted to: 00 → 01 → 10 → 00
D type flip flop DFF3 and d type flip flop DFF4 also form except 3 circuit, and then have formed except 9 circuit.
This division arithmetic unit 103 comprises:
The first d type flip flop DFF1, the second d type flip flop DFF2,3d flip-flop DFF3, four d flip-flop DFF4, the first NOR gate OR1, the second NOR gate OR2, binary counter 131 and logical operation module 132;
The reset terminal RD1 of the first d type flip flop DFF1, the reset terminal RD2 of the second d type flip flop DFF2, the reset terminal RD3 of 3d flip-flop DFF3, the reset terminal RD4 of four d flip-flop DFF4 is the control end of division arithmetic unit 13 simultaneously, the input end of clock CK1 of the first d type flip flop DFF1, the input end of clock CK2 of the second d type flip flop DFF2 is the input of division arithmetic unit 13, the trigger end D2 of the second d type flip flop DFF2 is connected with the forward output Q0 of the first d type flip flop DFF1, the first input end of the first NOR gate OR1 is connected with the forward output Q0 of the first d type flip flop DFF1, the second input of the first NOR gate OR1 is connected with the forward output Q1 of the second d type flip flop DFF2, the output while of the first NOR gate OR1 and the trigger end D1 of the first d type flip flop DFF1, the input end of clock CK3 of 3d flip-flop DFF3, the input end of clock CK4 of four d flip-flop DFF4 connects, the trigger end D4 of four d flip-flop DFF4 is connected with the forward output Q2 of 3d flip-flop DFF3, the first input end of the second NOR gate OR2 is connected with the forward output Q2 of 3d flip-flop DFF3, the second input of the second NOR gate OR2 is connected with the forward output Q3 of four d flip-flop DFF4, the output of the second NOR gate OR2 is connected with the trigger end D3 of 3d flip-flop DFF3 and the input end of clock CK of binary counter 131 simultaneously, the output of binary counter 131 is the first output of division arithmetic unit 13, the forward output Q0 of the first d type flip flop DFF1, the forward output Q1 of the second d type flip flop DFF2, the forward output Q2 of 3d flip-flop DFF3, the forward output Q3 of four d flip-flop DFF4 is successively in the first input end of logical operation module 132, the second input, the 3rd input, four-input terminal connects, the output of logical operation module 132 is the second output of division arithmetic unit 13.
In embodiments of the present invention, the oscillator signal OSC of oscillator 102 outputs counts and removes after nine computings by four d type flip flop DFF1-DFF4, by binary counter 131, obtain business N, and remainder M need to obtain after the logical transition of logical operation module 132, M binary number representation is M
3m
2m
1m
0, its logical transition formula is:
Wherein, Q
0-Q
3be respectively the logic state of d type flip flop DFF1-DFF4 forward output output, and obtain following corresponding form by this logical transition formula:
In embodiments of the present invention, logical operation module 132 can be formed by connecting according to the logical expression of remainder M by a plurality of gates, repeats no more herein.
Fig. 6 shows a realization example structure of decoding unit in the host-host protocol decoding that the embodiment of the present invention provides, and for convenience of explanation, only shows part related to the present invention.
As one embodiment of the invention, decoding unit 104 comprises:
The first demultiplier 141, the second demultiplier 142, the 3rd demultiplier 143, control module 144, state machine 145 and decoder 146;
The first input end of control module 144 is the first input end of decoding unit 104, the second input of control module 144 is the second input of decoding unit 104, the first output of control module 144 is connected with the input of the first demultiplier 141, the second output of control module 144 is connected with the input of the second demultiplier 142, the 3rd output of control module 144 is connected with the input of the 3rd demultiplier 143, the output of state machine 145 is connected with the 3rd input of control module 144, the clock end that the clock end of control module 144 is decoding unit, the output of control module 144 is connected with the first input end of decoder 146, the second input of decoder 146 is the 3rd input of decoding unit 104, the output of decoder 146 is the output of decoding unit 104.
In embodiments of the present invention, control module 144 generates the first sampling period and the second sampling period according to business N, and data byte figure place j is write to the first demultiplier 141, the remainder M of reception is write to the second demultiplier 142, control module 144 is according to the result of successively decreasing of the first demultiplier 141 and the second demultiplier 142, the first sampling period (N+1) T or the second sampling period NT are write to the 3rd demultiplier 143, and generate sampling pulse according to the result of successively decreasing of the 3rd demultiplier 143, according to the data byte sampling in each frame in 146 pairs of transmission data of this sampling pulse decoder, decode.
As one embodiment of the invention, can the interpolation of the first sampling period (N+1) T or the second sampling period NT be set by state machine 145, the state transition graph of this state machine 145 can be:
0000→0001→0010→0011→0100→0101→0110→0111→1000→0000……。
For example, the time width that samples start byte is 176T, through except after 9 processing, obtains N=19 so, and M=5, is shown N=5 ' b10011 with binary form, M=4 ' b0101.
During sampling start bit, sampled point is set as to 5 ' b01001.Thereafter the data bit sampling period is respectively 5 ' b10100 5 times, 35 ' b10011.And, when distributing, adopt the mode distributing of inserting as far as possible, for example from sampling period of start bit to the 8 data bit as shown in Figure 7.
Concrete sampling process is: the trailing edge of each data byte of usining starts as sampled data, the sampled point of start bit is (N/2) T, if M=3, by state machine, interpolation is set, for example, what the 2nd sampling pulse and the 1st sampling pulse were set is spaced apart (N+1) T, the 3rd sampling pulse and the 2nd sampling pulse be spaced apart (N+1) T, the 4th sampling pulse and the 3rd sampling pulse be spaced apart (N+1) T, the 5th sampling pulse and the 4th sampling pulse be spaced apart NT, the 6th sampling pulse and the 5th sampling pulse be spaced apart NT, the 7th sampling pulse and the 6th sampling pulse be spaced apart NT, the 8th sampling pulse and the 7th sampling pulse be spaced apart NT, the 9th sampling pulse and the 8th sampling pulse be spaced apart NT.Understandably, the selection at above-mentioned each sampling pulse interval can change setting by changing the setting of the state conversion value of state machine, for example, by the NT that is set to of the 3rd sampling pulse and the 2nd sampling pulse, the 8th sampling pulse and the 7th sampling pulse be set to (N+1) T, and often sending sampling pulse one time, the first demultiplier, the second demultiplier and the 3rd demultiplier should correspondingly successively decrease data byte figure place j, remainder M and sampling period.
Specifically the process of successively decreasing is:
Control module generates (N/2) T of initial sampling period according to the cycle of business N and oscillator signal OSC, to in this example of data byte figure place j(, be 9) write the first demultiplier 141, and this initial sampling period (N/2) T is write to the 3rd demultiplier 143, the first demultiplier 141 starts to subtract 1 operation according to the cycle of oscillator signal OSC, now the 3rd demultiplier 143 also enters the program of successively decreasing under the periodic Control of oscillator signal OSC, and export first sampling pulse being decremented at 0 o'clock, simultaneously, control module 144 generates the first sampling period (N+1) T and the second sampling period NT according to business N, and remainder M is write to the second demultiplier 142, under the control of state machine 145, control module 144 writes the 3rd demultiplier 143 by the first sampling period (N+1) T or the second sampling period NT, when state machine 145 controls that the first sampling period, (N+1) T write the 3rd demultiplier 143, the second demultiplier 142 all successively decreases 1, and the 3rd demultiplier 143 successively decreases after being written into the first sampling period (N+1) T or the second sampling period NT, until be decremented at 0 o'clock, export second sampling pulse, again by control module 144, the first sampling period (N+1) T or the second sampling period NT are write in the 3rd demultiplier 143 simultaneously, until the first demultiplier 141 is decremented to zero, and each time in the first sampling period, (N+1) T was written into the 3rd demultiplier 143 time, the second demultiplier 142 all subtracts 1, until the second demultiplier 142 is decremented to zero, so circulation will be exported j sampling pulse successively, complete the sampling operation of whole data byte.
If do not adopt state machine 145, also can first to third state machine 143, write the first sampling period (N+1) T, and judge whether the second demultiplier 142 is zero, if the second demultiplier 142 is non-vanishing, continue to write the first sampling period (N+1) T to the 3rd demultiplier 143, until the second demultiplier 142 is decremented to zero, then writes the 3rd demultiplier 143 by the second sampling period NT, until the first demultiplier 141 is decremented to zero.
When the first demultiplier 141 is decremented to zero, represent that this data byte sampled.
It should be noted that, if last 1 of the binary system of N is 1, and M ≠ 0 can subtract 1 by M so, and the sampled point of start bit is [N/2]+1.Wherein [N/2] refers to its integer part.
The embodiment of the present invention by the time cycle in frame start byte low level figure place to counting the cycle of oscillation of oscillator signal, and count value is carried out to division arithmetic, obtain quotient and the remainder, according to quotient and the remainder, decode, do not have accumulated error to produce, without reducing solution code error by promoting data transmission rate, greatly improved the accuracy rate of decoding, and realize simply, cost is low, good stability.
These are only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. a host-host protocol coding/decoding method, is characterized in that, described method comprises the steps:
Generate oscillator signal;
Detect frame start signal, and when described frame start signal being detected, output sampling control signal;
Receive after described sampling control signal, within the time cycle of frame start byte low level figure place, to counting the cycle of oscillation of described oscillator signal, and described count value is carried out to division arithmetic, output quotient and the remainder;
According to quotient and the remainder, determine the sampling period, to generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded.
2. the method for claim 1, is characterized in that, describedly according to quotient and the remainder, determines the sampling period, and to generate sampling pulse, and the step of the data byte in transmission data being decoded according to described sampling pulse is specially:
According to described business, generate the first sampling period and the second sampling period;
Data byte figure place is write to the first demultiplier, described remainder is write to the second demultiplier;
According to the result of successively decreasing of described the first demultiplier and described the second demultiplier, described the first sampling period or described the second sampling period are write to the 3rd demultiplier;
According to the result of successively decreasing of described the 3rd demultiplier, generate sampling pulse;
According to described sampling pulse, to the data byte sampling in each frame in transmission data, decode.
3. a host-host protocol decoding device, described device is connected with driver element, comprising:
Oscillator, for generating oscillator signal;
Controller, for detection of frame start signal, and when described frame start signal being detected, output sampling control signal, the input of described controller receives transmission data;
Division arithmetic unit, for after receiving described sampling control signal, within the time cycle of frame start byte low level figure place to counting the cycle of oscillation of described oscillator signal, and described count value is carried out to division arithmetic, output quotient and the remainder, the control end of described division arithmetic unit is connected with the output of described controller, and the input of described division arithmetic unit is connected with the output of described oscillator;
Decoding unit, for determining the sampling period according to described quotient and the remainder, to generate sampling pulse, and according to described sampling pulse, the data byte in transmission data is decoded, the first input end of described decoding unit is connected with the first output of described division arithmetic unit, the second input of described decoding unit is connected with the second output of described division arithmetic unit, the 3rd input of described decoding unit is connected to receive transmission data with the input of described controller, the clock end of described decoding unit is connected with the output of described oscillator, the output of described decoding unit is connected with described driver element.
4. device as claimed in claim 3, is characterized in that, described controller is state machine or time detection device.
5. device as claimed in claim 3, is characterized in that, described division arithmetic unit comprises:
The first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the first NOR gate, the second NOR gate, binary counter and logical operation module;
The reset terminal of described the first d type flip flop, the reset terminal of described the second d type flip flop, the reset terminal of described 3d flip-flop, the reset terminal of described four d flip-flop is the control end of described division arithmetic unit simultaneously, the input end of clock of described the first d type flip flop, the input end of clock of described the second d type flip flop is the input of described division arithmetic unit, the trigger end of described the second d type flip flop is connected with the forward output of described the first d type flip flop, the first input end of described the first NOR gate is connected with the forward output of described the first d type flip flop, the second input of described the first NOR gate is connected with the forward output of described the second d type flip flop, the output while of described the first NOR gate and the trigger end of described the first d type flip flop, the input end of clock of described 3d flip-flop, the input end of clock of described four d flip-flop connects, the trigger end of described four d flip-flop is connected with the forward output of described 3d flip-flop, the first input end of described the second NOR gate is connected with the forward output of described 3d flip-flop, the second input of described the second NOR gate is connected with the forward output of described four d flip-flop, the output of described the second NOR gate is connected with the trigger end of described 3d flip-flop and the input end of clock of described binary counter simultaneously, the output of described binary counter is the first output of described division arithmetic unit, the forward output of described the first d type flip flop, the forward output of described the second d type flip flop, the forward output of described 3d flip-flop, the forward output of described four d flip-flop is successively in the first input end of described logical operation module, the second input, the 3rd input, four-input terminal connects, the output of described logical operation module is the second output of described division arithmetic unit.
6. device as claimed in claim 3, is characterized in that, described decoding unit comprises:
The first demultiplier, the second demultiplier, the 3rd demultiplier, control module, state machine and decoder;
The first input end of described control module is the first input end of described decoding unit, the second input that the second input of described control module is described decoding unit, the first output of described control module is connected with the input of described the first demultiplier, the second output of described control module is connected with the input of described the second demultiplier, described the 3rd output of described control module is connected with the input of described the 3rd demultiplier, the output of described state machine is connected with the 3rd input of described control module, the clock end that the clock end of described control module is described decoding unit, the output of described control module is connected with the first input end of described decoder, the 3rd input that the second input of described decoder is described decoding unit, the output of described decoder is the output of described decoding unit.
7. a host-host protocol decoding chip, is characterized in that, described equipment comprises the host-host protocol decoding device as described in claim 3 to 6 any one.
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| CN201310513788.1A CN103561008B (en) | 2013-10-25 | 2013-10-25 | A kind of host-host protocol coding/decoding method, device and host-host protocol decoding chip |
| US14/351,137 US9264215B2 (en) | 2013-10-25 | 2014-01-10 | Transmission protocol decoding method, device, and transmission protocol decoding chip |
| PCT/CN2014/070454 WO2015058473A1 (en) | 2013-10-25 | 2014-01-10 | Decoding method and apparatus of transmission protocol and transmission protocol decoding chip |
| EP14711903.6A EP2887616A4 (en) | 2013-10-25 | 2014-01-10 | Decoding method and apparatus of transmission protocol and transmission protocol decoding chip |
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| CN107452309A (en) * | 2017-08-31 | 2017-12-08 | 深圳市明微电子股份有限公司 | A kind of decoding circuit of self-adapting data frequency |
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