CN103545355A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103545355A CN103545355A CN201210241514.7A CN201210241514A CN103545355A CN 103545355 A CN103545355 A CN 103545355A CN 201210241514 A CN201210241514 A CN 201210241514A CN 103545355 A CN103545355 A CN 103545355A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000001301 oxygen Substances 0.000 claims abstract description 61
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 61
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims description 173
- 239000000463 material Substances 0.000 claims description 29
- 239000011241 protective layer Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 23
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 16
- 229910052735 hafnium Inorganic materials 0.000 claims description 16
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 9
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 9
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 8
- -1 hafnium nitride Chemical class 0.000 claims description 8
- INIGCWGJTZDVRY-UHFFFAOYSA-N hafnium zirconium Chemical compound [Zr].[Hf] INIGCWGJTZDVRY-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 6
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 6
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- DBOSZDMILYIJNB-UHFFFAOYSA-M N.[O-2].[O-2].[O-2].[O-2].[OH-].O.[Hf+4].[Ta+5] Chemical compound N.[O-2].[O-2].[O-2].[O-2].[OH-].O.[Hf+4].[Ta+5] DBOSZDMILYIJNB-UHFFFAOYSA-M 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 claims description 3
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 3
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 claims description 3
- OPZZBWHYLNRIQZ-UHFFFAOYSA-N [Si]=O.[Zr].[N] Chemical compound [Si]=O.[Zr].[N] OPZZBWHYLNRIQZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 3
- 238000010521 absorption reaction Methods 0.000 abstract 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 37
- 238000002955 isolation Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002926 oxygen Chemical class 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
Abstract
Disclosed are a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a high k gate dielectric layer, an oxygen absorption layer and gate electrodes, wherein the high k gate dielectric layer is positioned on the upper surface of the substrate, the oxygen absorption layer is positioned on the upper surface or the lower surface of the high k gate dielectric layer, and the gate electrodes are positioned on the upper surface of the high k gate dielectric layer. The manufacturing method of the semiconductor device includes the steps: providing the substrate; forming the high k gate dielectric layer on the upper surface of the substrate; forming the oxygen absorption layer on the upper surface of the substrate or on the upper surface of the high k gate dielectric layer before or after forming the high k gate dielectric layer; forming the gate electrodes on the upper surface of the high k gate dielectric layer. The semiconductor device is provided with thin equivalent oxide, and the performance of the semiconductor device can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular a kind of semiconductor device and preparation method thereof.
Background technology
Nowadays,, in lower process node, gate dielectric layer and the grid stacked structure that metal gate electrode combines with the high k material of low equivalent oxide thickness (EOT, Equivalent Oxide Thickness) have been subject to application widely.
Transistorized formation method about high K/ metal gate structure can be the U.S. patent documents of US 2009/0142899 A1 with reference to publication number.
In order to improve the interfacial characteristics of high-k gate dielectric layer and substrate, boundary layer (interfacial layer can be set between substrate and high-k gate dielectric layer, IL), this boundary layer can not only provide the interface of better quality between substrate and boundary layer, and the interface of better quality can also be provided between high-k gate dielectric layer and boundary layer.In addition,, in order to protect high-k gate dielectric layer, can also between high-k gate dielectric layer and gate electrode, protective layer be set.
Therefore, in prior art, a kind of manufacture method of semiconductor device comprises:
Substrate is provided;
In described substrate top surface, form boundary layer;
At described boundary layer upper surface, form high-k gate dielectric layer;
At described high-k gate dielectric layer upper surface, form protective layer;
At described protective layer upper surface, form the pseudo-grid of polysilicon material;
Formation source/drain region, and carry out annealing in process;
Remove pseudo-grid and form opening, in opening, fill metal, form the gate electrode of metal material.
But the equivalent oxide thickness of the high-k gate dielectric layer of the semiconductor device that employing said method is made is very thick, finally affected the performance of semiconductor device.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device and preparation method thereof, can obtain the semiconductor device of lower equivalent oxide thickness, and can improve the performance of semiconductor device.
For addressing the above problem, the invention provides a kind of semiconductor device, comprising:
Substrate;
Be positioned at the high-k gate dielectric layer of described substrate top surface;
Be positioned at the gate electrode of described high-k gate dielectric layer upper surface;
Be positioned at the oxygen uptake layer of described high-k gate dielectric layer upper surface or lower surface.
In order to address the above problem, the present invention also provides a kind of manufacture method of semiconductor device, comprising:
Substrate is provided;
In described substrate top surface, form high-k gate dielectric layer;
At described high-k gate dielectric layer upper surface, form gate electrode;
Before or after forming high-k gate dielectric layer, in substrate top surface or high-k gate dielectric layer upper surface, form oxygen uptake layer.
Compared with prior art, technical solution of the present invention has the following advantages: at high-k gate dielectric layer upper surface or lower surface, oxygen uptake layer is set, this oxygen uptake layer can adsorb the free oxygen atom of invading by gate electrode, thereby can avoid the impact of the equivalent oxide thickness of free oxygen atom pair high-k gate dielectric layer, finally guarantee the superior function of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the structural representation of the semiconductor device that in embodiment of the present invention, embodiment provides;
Fig. 2 is the structural representation of the semiconductor device that in embodiment of the present invention, another embodiment provides;
Fig. 3 is the schematic flow sheet of the manufacture method of the semiconductor device that in embodiment of the present invention, embodiment provides;
Fig. 4 is the schematic flow sheet of the manufacture method of the semiconductor device that in embodiment of the present invention, another embodiment provides.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Just as described in the background section, the equivalent oxide thickness of the high-k gate dielectric layer of the semiconductor device that prior art is made is very thick, has finally affected the performance of semiconductor device.
Through inventor, study discovery: because substrate comprises fleet plough groove isolation structure (STI) more, and fleet plough groove isolation structure comprises a lot of oxygen atoms, in forming the subsequent process of semiconductor device, can experience one or many high-temperature process (as: annealing), thereby make the oxygen atom in fleet plough groove isolation structure free out.These free oxygen atoms can pass through gate electrode, protective layer and high-k gate dielectric layer successively; enter boundary layer; thereby the threshold voltage of semiconductor device is changed; even can cause the regrowth of boundary layer bottom; finally increase the equivalent oxide thickness of semiconductor device, affected the performance of semiconductor device.
For above-mentioned defect, inventor proposes, at upper surface or the lower surface of high-k gate dielectric layer, oxygen uptake layer is set, this oxygen uptake layer can adsorb free oxygen atom out from fleet plough groove isolation structure, and adsorbed the oxygen uptake layer after oxygen atom and also can jointly form new high-k gate dielectric layer with former high-k gate dielectric layer, thereby both can avoid the impact of the equivalent oxide thickness of free oxygen atom pair high-k gate dielectric layer, not affect again the performance of semiconductor device.
Below in conjunction with accompanying drawing, be elaborated.
Shown in figure 1, in present embodiment, an embodiment provides a kind of semiconductor device, comprising:
Be positioned at the boundary layer 210 of described substrate 110 upper surfaces;
Be positioned at the oxygen uptake layer 310 of described boundary layer 210 upper surfaces;
Be positioned at the high-k gate dielectric layer 410 of described oxygen uptake layer 310 upper surface;
Be positioned at the protective layer 510 of described high-k gate dielectric layer 410 upper surfaces;
Be positioned at the gate electrode 610 of described protective layer 510 upper surfaces.
In described substrate 110, can comprise fleet plough groove isolation structure.
The material of described boundary layer 210 can comprise silica or silicon oxynitride, thereby can improve the interfacial characteristics between substrate 110 and oxygen uptake layer 310.
The thickness range of described boundary layer 210 can comprise
It should be noted that, in the present embodiment, semiconductor device also can not comprise boundary layer, and it does not affect protection scope of the present invention.
The material of described oxygen uptake layer 310 can comprise: a kind of or combination in any in hafnium, hafnium nitride and zirconium hafnium.When the material of oxygen uptake layer 310 comprises hafnium, after follow-up adsorb oxygen atom, hafnium will become hafnium oxide; When the material of oxygen uptake layer 310 comprises hafnium nitride, after follow-up adsorb oxygen atom, hafnium nitride will become nitrogen hafnium oxide; When the material of oxygen uptake layer 310 comprises zirconium hafnium, after follow-up adsorb oxygen atom, zirconium hafnium will become zirconia and hafnium oxide.Above-mentioned hafnium oxide, silicon oxynitride or zirconic dielectric constant are all very high, are all high k materials.In addition, due to oxygen uptake layer 310 next-door neighbour's high-k gate dielectric layer 410, therefore the oxygen uptake layer 310 after adsorb oxygen atom will play the effect identical with high-k gate dielectric layer 410, the oxygen uptake layer 310 that is adsorb oxygen atom is common as new high-k gate dielectric layer with high-k gate dielectric layer 410, thereby can not affect the performance of semiconductor device.
The thickness range of described oxygen uptake layer 310 can comprise:
The material of described high-k gate dielectric layer 410 can comprise: a kind of or combination in any in hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium and aluminium oxide.
Owing to can playing the effect identical with high-k gate dielectric layer 410 after oxygen uptake layer 310 adsorb oxygen atom, therefore in the present embodiment, can reduce the thickness of high-k gate dielectric layer 410, make to change into after adsorb oxygen atom the thickness of the high-k gate dielectric layer that equals to design in semiconductor device after the oxygen uptake layer 310 of high k material and the thickness of high-k gate dielectric layer 410.Particularly, the thickness range of described high-k gate dielectric layer 410 can comprise:
The material of described protective layer 510 can comprise: titanium nitride or tantalum nitride, thus can protect high-k gate dielectric layer 410.
The thickness range of described protective layer 510 can comprise:
It should be noted that, in the present embodiment, can not comprise protective layer, it does not affect protection scope of the present invention yet.
The material of described gate electrode 610 can be metal, can be also polysilicon.
The present embodiment arranges oxygen uptake layer 310 by the lower surface at high-k gate dielectric layer 410, thereby can adsorb free oxygen atom out from fleet plough groove isolation structure etc., prevent that oxygen atom from passing through gate electrode 610, protective layer 510 and high-k gate dielectric layer 410 enter boundary layer 210, and the oxygen uptake layer 310 that has adsorbed oxygen atom also can form new high-k gate dielectric layer jointly with former high-k gate dielectric layer 410, thereby both can avoid the impact of the equivalent oxide thickness of free oxygen atom pair high-k gate dielectric layer, do not affect again the performance of semiconductor device, finally improved the performance of semiconductor device.
Shown in figure 2, present embodiment another embodiment also provide a kind of semiconductor device, comprising:
Be positioned at the boundary layer 220 of described substrate 120 upper surfaces;
Be positioned at the high-k gate dielectric layer 420 of described boundary layer 220 upper surfaces;
Be positioned at the oxygen uptake layer 320 of described high-k gate dielectric layer 420 upper surfaces;
Be positioned at the protective layer 520 of described oxygen uptake layer 320 upper surface;
Be positioned at the gate electrode 620 of described protective layer 520 upper surfaces.
Compare with previous embodiment, the present embodiment is adjusted to the position of oxygen uptake layer 320 upper surface of high-k gate dielectric layer 420 from the lower surface of high-k gate dielectric layer 420, and all the other are all identical with previous embodiment, do not repeat them here.
In the present embodiment, oxygen uptake layer 320 also can adsorb free oxygen atom out from fleet plough groove isolation structure etc., prevent that oxygen atom from entering boundary layer 220, and the oxygen uptake layer 320 that has adsorbed oxygen atom also can form new high-k gate dielectric layer jointly with former high-k gate dielectric layer 420, thereby both can avoid the impact of the equivalent oxide thickness of free oxygen atom pair high-k gate dielectric layer, do not affect again the performance of semiconductor device, finally improved the performance of semiconductor device.
Correspondingly, shown in figure 3, embodiment of present embodiment provides a kind of manufacture method of semiconductor device, comprising:
Step S11, provides substrate;
Step S12, forms boundary layer in described substrate top surface;
Step S13, forms oxygen uptake layer at described boundary layer upper surface;
Step S14, forms high-k gate dielectric layer at described oxygen uptake layer upper surface;
Step S15, forms protective layer at described high-k gate dielectric layer upper surface;
Step S16, forms gate electrode at described protective layer upper surface.
Described boundary layer can adopt heat growth method or chemically grown method to form.
Particularly, the material of described boundary layer can comprise: silica or silicon oxynitride, its thickness range can comprise
Described oxygen uptake layer can adopt atom layer deposition process to form.
Particularly, the material of described oxygen uptake layer can comprise: a kind of or combination in any in hafnium, hafnium nitride and zirconium hafnium, and its thickness range can comprise:
When the material of oxygen uptake layer comprises hafnium, after follow-up adsorb oxygen atom, hafnium will become hafnium oxide; When the material of oxygen uptake layer comprises hafnium nitride, after follow-up adsorb oxygen atom, hafnium nitride will become nitrogen hafnium oxide; When the material of oxygen uptake layer comprises zirconium hafnium, after follow-up adsorb oxygen atom, zirconium hafnium will become zirconia and hafnium oxide.Above-mentioned hafnium oxide, silicon oxynitride or zirconic dielectric constant are all very high, are all high k materials.In addition, due to follow-up, at oxygen uptake layer upper surface, form high-k gate dielectric layer, therefore the oxygen uptake layer after adsorb oxygen atom will play the effect identical with high-k gate dielectric layer, be the oxygen uptake layer of adsorb oxygen atom and high-k gate dielectric layer jointly as new high-k gate dielectric layer, thereby can not affect the performance of semiconductor device.
It should be noted that, in the present embodiment, can also be omitted in the step that substrate top surface forms boundary layer, thereby directly on substrate, form oxygen uptake layer, it does not affect protection scope of the present invention.
Described high-k gate dielectric layer can adopt atom layer deposition process to form.
Particularly, the material of described high-k gate dielectric layer can comprise: a kind of or combination in any in hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium and aluminium oxide, and its thickness range can comprise:
Owing to can playing the effect identical with high-k gate dielectric layer after oxygen uptake layer adsorb oxygen atom, therefore in the present embodiment, can reduce the thickness of high-k gate dielectric layer, make to change into after adsorb oxygen atom the thickness of the high-k gate dielectric layer that the oxygen uptake layer of high k material and the thickness of high-k gate dielectric layer equals to design in semiconductor device afterwards.
It should be noted that, the material of oxygen uptake layer and the material of high-k gate dielectric layer after adsorb oxygen atom can be identical, also can be different.
Described protective layer can adopt chemical vapour deposition technique or atomic layer deposition method to form.
Particularly, the material of described protective layer can comprise: titanium nitride or tantalum nitride, and its thickness range can comprise:
Described formation gate electrode can comprise:
At described protective layer upper surface, form the pseudo-grid of polysilicon material;
Formation source/drain region, and carry out annealing in process;
Remove pseudo-grid and form opening, in opening, fill metal, form the gate electrode of metal material.
It should be noted that, can omit the step that forms protective layer in the present embodiment, thereby form gate electrode at high-k gate dielectric layer upper surface, it does not limit the scope of the invention.
The present embodiment forms the step of oxygen uptake layer by increase, guarantee that oxygen uptake layer can adsorb free oxygen atom out from fleet plough groove isolation structure etc., prevent that oxygen atom from entering boundary layer, and the oxygen uptake layer that has adsorbed oxygen atom also can form new high-k gate dielectric layer jointly with former high-k gate dielectric layer, thereby both can avoid the impact of the equivalent oxide thickness of free oxygen atom pair high-k gate dielectric layer, do not affect again the performance of semiconductor device, finally improved the performance of semiconductor device.
Shown in figure 4, another embodiment of present embodiment also provides a kind of manufacture method of semiconductor device, comprising:
Step S21, provides substrate;
Step S22, forms boundary layer in described substrate top surface;
Step S23, forms high-k gate dielectric layer at described boundary layer upper surface;
Step S24, forms oxygen uptake layer at described high-k gate dielectric layer upper surface;
Step S25, forms protective layer at described oxygen uptake layer upper surface;
Step S26, forms gate electrode at described protective layer upper surface.
Compare with previous embodiment, the present embodiment has been adjusted the sequencing that forms oxygen uptake layer step and form high-k gate dielectric layer step, and all the other are identical with previous embodiment, do not repeat them here.
The oxygen uptake layer that the present embodiment forms can adsorb free oxygen atom out from fleet plough groove isolation structure etc. equally, thereby both can avoid the impact of the equivalent oxide thickness of free oxygen atom pair high-k gate dielectric layer, do not affect again the performance of semiconductor device, finally improved the performance of semiconductor device.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a semiconductor device, comprising:
Substrate;
Be positioned at the high-k gate dielectric layer of described substrate top surface;
Be positioned at the gate electrode of described high-k gate dielectric layer upper surface;
It is characterized in that, also comprise:
Be positioned at the oxygen uptake layer of described high-k gate dielectric layer upper surface or lower surface.
2. semiconductor device as claimed in claim 1, is characterized in that, the material of described oxygen uptake layer comprises: a kind of or combination in any in hafnium, hafnium nitride and zirconium hafnium.
3. semiconductor device as claimed in claim 1 or 2, is characterized in that, the thickness of described oxygen uptake layer comprises:
4. semiconductor device as claimed in claim 1, is characterized in that, also comprises: the boundary layer that is close to described substrate top surface.
5. semiconductor device as claimed in claim 4, is characterized in that, the material of described boundary layer comprises: silica or silicon oxynitride; The thickness range of described boundary layer comprises:
6. the semiconductor device as described in claim 1 or 4, is characterized in that, also comprises: the protective layer that is close to described gate electrode lower surface.
7. semiconductor device as claimed in claim 6, is characterized in that, the material of described protective layer comprises: titanium nitride or tantalum nitride; The thickness range of described protective layer comprises:
8. semiconductor device as claimed in claim 1, it is characterized in that, the material of described high-k gate dielectric layer comprises a kind of or combination in any in hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium and aluminium oxide; The thickness range of described high-k gate dielectric layer comprises:
9. a manufacture method for semiconductor device, comprising:
Substrate is provided;
In described substrate top surface, form high-k gate dielectric layer;
At described high-k gate dielectric layer upper surface, form gate electrode;
It is characterized in that, also comprise:
Before or after forming high-k gate dielectric layer, in substrate top surface or high-k gate dielectric layer upper surface, form oxygen uptake layer.
10. the manufacture method of semiconductor device as claimed in claim 9, is characterized in that, described oxygen uptake layer adopts atom layer deposition process to form.
The manufacture method of 11. semiconductor device as claimed in claim 9, is characterized in that, the material of described oxygen uptake layer comprises: a kind of or combination in any in hafnium, hafnium nitride and zirconium hafnium.
The manufacture method of 12. semiconductor device as described in claim 9 or 10, is characterized in that, the thickness of described oxygen uptake layer comprises:
The manufacture method of 13. semiconductor device as claimed in claim 9, is characterized in that, also comprises: before forming high-k gate dielectric layer or oxygen uptake layer, be close to described substrate top surface and form boundary layer.
The manufacture method of 14. semiconductor device as described in claim 9 or 13, is characterized in that, also comprises: after forming high-k gate dielectric layer or oxygen uptake layer and before forming gate electrode, at high-k gate dielectric layer upper surface or oxygen uptake layer upper surface formation protective layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210241514.7A CN103545355A (en) | 2012-07-12 | 2012-07-12 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210241514.7A CN103545355A (en) | 2012-07-12 | 2012-07-12 | Semiconductor device and manufacturing method thereof |
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| CN103545355A true CN103545355A (en) | 2014-01-29 |
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| CN201210241514.7A Pending CN103545355A (en) | 2012-07-12 | 2012-07-12 | Semiconductor device and manufacturing method thereof |
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| CN111769043A (en) * | 2019-04-02 | 2020-10-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method of gate dielectric layer, semiconductor structure and forming method thereof |
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