CN103545199A - Method used for thick metal etching of power device - Google Patents
Method used for thick metal etching of power device Download PDFInfo
- Publication number
- CN103545199A CN103545199A CN201210246239.8A CN201210246239A CN103545199A CN 103545199 A CN103545199 A CN 103545199A CN 201210246239 A CN201210246239 A CN 201210246239A CN 103545199 A CN103545199 A CN 103545199A
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- China
- Prior art keywords
- thick metal
- etching
- metal layers
- described step
- power device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
Abstract
The invention discloses a method used for thick metal etching of a power device. The method includes the steps: 1), depositing a thick metal layer on a medium layer; 2), performing photoresist coating, exposing and developing on the thick metal layer; 3), performing wet etching on the thick metal layer; 4), performing dry etching on the thick metal layer. By the method, the problem of etching residue of thick metal and the problem of resist floating and over-etching in wet etching can be effectively improved.
Description
Technical field
The present invention relates to the method for the metal etch in a kind of semiconductor applications, particularly relate to a kind of method for the thick metal etch of power device.
Background technology
In power device manufacturing process, in mos field effect transistor (MOSFET) manufacture, metal layer thickness is conventionally at 3～3.5 μ m, and specialities are for making the resistance to large electric current of device, and metal layer thickness can thicken 6 μ m.
Wherein, for the thick metal flow process of the dry etching in existing power device manufacturing process, as follows:
1) thick metal deposit on dielectric layer, metal material is AlCu or AlSiCu, thickness 5～7 μ m, photoresist coating, exposure, development;
2) dry etching metal, etching depth 6 μ m, the section after the thick metal of etching is as shown in Figure 1.
For the thick metal process of above-mentioned use one step dry etching, can make the application of thick metal directly cause the dry etch process of application conventionally difficult, the organic product forming in the process of etching upper strata metal covers lower metal, causes etching residue, thereby causes component failure.
In addition, although in power device manufacturing process, the also technique of the thick metal of useful wet etching, its flow process is as follows:
1) thick metal deposit on dielectric layer, metal material is AlCu or AlSiCu, thickness 5～7 μ m, photoresist coating, exposure, development;
2) wet etching metal, etching depth 6 μ m, the section after the thick metal of etching is as shown in Figure 2.
Although only use the thick metal of a step wet etching, but because metal level is thick especially, for guaranteeing etching noresidue, need to strengthen over etching (over etch), this directly causes lateral etching amount excessive, thereby have, in etching process, to occur that photoresist adheres to not firm, cause the risk of floating glue, and excessive because of lateral etching amount, liquid can cause harmful effect to device understructure, can cause device understructure by the problem of liquid etching.
Therefore, need develop a kind of new thick metal etch process, to reduce metal residual, and in wet etching, occur float glue, cross the problems such as quarter.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method for the thick metal etch of power device.By the method, can effectively improve the etching residue problem of thick metal, and in wet etching, occur float glue, cross the problems such as quarter.
For solving the problems of the technologies described above, the method for the thick metal etch of power device of the present invention, comprises step:
1) deposit thick metal layers on dielectric layer;
2), on thick metal layers, carry out photoresist coating, exposure, development;
3) wet etching thick metal layers;
4) dry etching thick metal layers.
Described power device comprises: mos field effect transistor.
In described step 1), dielectric layer comprises: silicon dioxide and boron phosphorus silicate glass (BPSG) that chemical vapour deposition (CVD) generates; The method of thick metal layers deposit comprises: physical vapor deposition (PVD); Metal material is AlCu or AlSiCu, and the thickness of thick metal layers is 5～7 μ m.
Described step 2) in, the thickness 2 μ m～4 μ m of photoresist.
In described step 3), the chemical liquid adopting in wet etching comprises: the mixed liquor of two or three in phosphoric acid, nitric acid or acetic acid; Wherein, the weight percent hundred of phosphoric acid is 70%～80%, and the weight percent hundred of nitric acid is 3%～8%, and the weight percent hundred of acetic acid is 3%～15%.The degree of depth of wet etching is 2～4 μ m.
In described step 4), the degree of depth of dry etching is 2～4 μ m.
In power device manufacturing process, the present invention, by first utilizing wet method that thick metal layers is needed to etched portions attenuate, takes away etching product by washing away of liquid, deionized water in wet etching process simultaneously, effectively reduces the barrier of follow-up dry etching; Further use again subsequently dry etching, residual metallic is carved.Therefore, the present invention both can effectively improve the etching residue problem of only using the thick metal of dry etching, only can avoid again floating glue, the excessive harmful effect that causes device understructure to be etched of lateral etching amount with the thick metal of wet etching, effectively improve the etching residue problem of thick metal, and in wet etching, occur float glue, cross problem at quarter.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the sectional schematic diagram after the thick metal of existing technique dry etching;
Fig. 2 is the sectional schematic diagram after the thick metal of existing technique wet etching;
Fig. 3 is the sectional schematic diagram after photoresist developing of the present invention;
Fig. 4 is the sectional schematic diagram after wet etching of the present invention;
Fig. 5 is the sectional schematic diagram after dry etching of the present invention.
Embodiment
Method for the thick metal etch of power device (as mos field effect transistor MOSFET) of the present invention, comprises step:
1) upper at interlayer dielectric layer (ILD), adopt PVD method deposit thick metal layers;
Wherein, the material of interlayer dielectric layer,, is followed successively by silicon dioxide and boron phosphorus silicate glass (BPSG) that chemical vapour deposition (CVD) generates from bottom to top, and the thickness of silicon dioxide is 1000A～2000A, thickness 3000A～6000A of BPSG; Metal material is AlCu or AlSiCu, and the thickness of this thick metal layers is 5～7 μ m;
2) on thick metal layers, carry out photoresist coating, exposure, development, result is as shown in Figure 3; Wherein, photoresist thickness can be 2 μ m～4 μ m;
3) adopt chemical liquid, carry out wet etching thick metal layers, the degree of depth of etching is 2～4 μ m, and result as shown in Figure 4;
This chemical liquid can be selected from the mixed liquor of two or three in phosphoric acid, nitric acid or acetic acid; Wherein, the weight percent hundred of phosphoric acid is 70%～80%, and the weight percent hundred of nitric acid is 3%～8%, and the weight percent hundred of acetic acid is 3%～15%.
Preferably, chemical liquid is the mixed liquor of acetic acid, nitric acid; Conventional PHC, M2.
4) dry etch process routinely, carries out thick metal layers etching, and the degree of depth of etching is 2～4 μ m, and result as shown in Figure 5.
Carry out according to the method described above thick metal etch, i.e. the present invention is by increase wet etching metal after photoetching process, and after this wet etching metal, carry out dry etching metal, therefore, can kish etching is clean, meanwhile, also can solve floating glue, crossing problem at quarter of occurring in wet etching.
Claims (9)
1. for a method for the thick metal etch of power device, it is characterized in that, comprise step:
1) deposit thick metal layers on dielectric layer;
2), on thick metal layers, carry out photoresist coating, exposure, development;
3) wet etching thick metal layers;
4) dry etching thick metal layers.
2. the method for claim 1, is characterized in that: described power device comprises: mos field effect transistor.
3. the method for claim 1, is characterized in that: in described step 1), dielectric layer comprises: silicon dioxide and boron phosphorus silicate glass that chemical vapour deposition (CVD) generates.
4. the method for claim 1, is characterized in that: in described step 1), the method for thick metal layers deposit comprises: physical vapour deposition (PVD).
5. the method for claim 1, is characterized in that: in described step 1), metal material is AlCu or AlSiCu, and the thickness of thick metal layers is 5～7 μ m.
6. the method for claim 1, is characterized in that: described step 2), and the thickness 2 μ m～4 μ m of photoresist.
7. the method for claim 1, is characterized in that: in described step 3), the chemical liquid adopting in wet etching comprises: the mixed liquor of two or three in phosphoric acid, nitric acid or acetic acid;
The degree of depth of wet etching is 2～4 μ m.
8. method as claimed in claim 7, is characterized in that: the weight percent hundred of described phosphoric acid is 70%～80%, and the weight percent hundred of nitric acid is 3%～8%, and the weight percent hundred of acetic acid is 3%～15%.
9. the method for claim 1, is characterized in that: in described step 4), the degree of depth of dry etching is 2～4 μ m.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210246239.8A CN103545199A (en) | 2012-07-16 | 2012-07-16 | Method used for thick metal etching of power device |
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| CN201210246239.8A CN103545199A (en) | 2012-07-16 | 2012-07-16 | Method used for thick metal etching of power device |
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| CN103545199A true CN103545199A (en) | 2014-01-29 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4775550A (en) * | 1986-06-03 | 1988-10-04 | Intel Corporation | Surface planarization method for VLSI technology |
| US6293457B1 (en) * | 2000-06-08 | 2001-09-25 | International Business Machines Corporation | Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization |
| CN101667556A (en) * | 2009-09-09 | 2010-03-10 | 上海宏力半导体制造有限公司 | Through hole etching method |
| CN102024747A (en) * | 2009-09-11 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing aluminium plug of power device |
| CN102169862A (en) * | 2011-03-02 | 2011-08-31 | 杭州士兰集成电路有限公司 | Fairlead structure for Bipolar circuit and manufacturing method thereof |
| CN102354684A (en) * | 2011-11-14 | 2012-02-15 | 杭州士兰集成电路有限公司 | Wiring structure forming method |
| CN103560113A (en) * | 2013-11-15 | 2014-02-05 | 北京京东方光电科技有限公司 | Array structure and manufacturing method thereof, array substrate and display device |
-
2012
- 2012-07-16 CN CN201210246239.8A patent/CN103545199A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4775550A (en) * | 1986-06-03 | 1988-10-04 | Intel Corporation | Surface planarization method for VLSI technology |
| US6293457B1 (en) * | 2000-06-08 | 2001-09-25 | International Business Machines Corporation | Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization |
| CN101667556A (en) * | 2009-09-09 | 2010-03-10 | 上海宏力半导体制造有限公司 | Through hole etching method |
| CN102024747A (en) * | 2009-09-11 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing aluminium plug of power device |
| CN102169862A (en) * | 2011-03-02 | 2011-08-31 | 杭州士兰集成电路有限公司 | Fairlead structure for Bipolar circuit and manufacturing method thereof |
| CN102354684A (en) * | 2011-11-14 | 2012-02-15 | 杭州士兰集成电路有限公司 | Wiring structure forming method |
| CN103560113A (en) * | 2013-11-15 | 2014-02-05 | 北京京东方光电科技有限公司 | Array structure and manufacturing method thereof, array substrate and display device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140114 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20140114 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20140129 |