CN103474407B - Semiconductor package - Google Patents
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- CN103474407B CN103474407B CN201310455301.9A CN201310455301A CN103474407B CN 103474407 B CN103474407 B CN 103474407B CN 201310455301 A CN201310455301 A CN 201310455301A CN 103474407 B CN103474407 B CN 103474407B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
- H01L2224/02126—Collar structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
- H01L2224/11902—Multiple masking steps
- H01L2224/11903—Multiple masking steps using different masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
Abstract
A kind of semiconductor package, comprising: the semiconductor-based end, and the described semiconductor-based end has weldering bed course; Cover the passivation layer of the described semiconductor-based end and part of solder pads layer, described passivation layer has the first opening of expose portion weldering bed course; It is positioned at the metal post of the first opening; Convex lower metal layer between metal post and weldering bed course, the edge of described convex lower metal layer has the undercut flaw to metal column bottom depression; Filling up the layer of compensation of described undercut flaw, the material of described layer of compensation is metal. The metal post of the semiconductor package of the present invention and the adhesivity of convex lower metal layer be better, it is to increase stability and reliability.
Description
Technical field
The present invention relates to field of semiconductor package, in particular to a kind of semiconductor package.
Background technology
Semiconductor packages refers to the process that wafer obtains individual chips according to product type and the processing of function demand. Existing semiconductor packages comprises the mode such as wire bond package and Flip-Chip Using. Compared with wire bond package mode, Flip-Chip Using mode has packaging density height, excellent radiation performance, I/O (I/O) port density height and reliability advantages of higher.
Flip-Chip Using mode relatively early arranges weldering pad on chip, and utilizes the convex point being arranged on weldering pad (comprising I/O weldering pad) to weld with base plate for packaging, it is achieved Chip Packaging. Along with semicon industry develops to miniatureization direction, the density being formed on wafer chip is increasing, accordingly, on wafer, the density of weldering pad and convex point is increasing, distance between convex point is more and more less, only utilizing the convex point of comparatively large vol directly to carry out welding the problem convex some bridge joint easily occur with base plate for packaging, namely adjacent convex point is short-circuited connection.
For solving convex some bridge joint problem, industry proposes intraconnections copper column technology (copperinterconnectposttechnology). In intraconnections copper column technology, chip is connected on base plate for packaging by copper post and the convex point being positioned on copper post. Due to the introducing of copper post, the thickness of convex point can significantly reduce, and can have less spacing between convex point, and therefore convex some bridge joint problem is weakened, and the introducing of copper post simultaneously also reduces electric capacity carrying (capacitanceload) of encapsulated circuit.
Prior art discloses a kind of chip packaging method adopting Flip-Chip Using mode, comprising:
With reference to figure 1, it is provided that the semiconductor-based end 100, it is formed with weldering bed course 101 the described semiconductor-based end 100; Forming the passivation layer 102 covering the described semiconductor-based end 100 and part of solder pads layer 101 surface, described passivation layer 102 has the opening 104 exposing weldering bed course 101 part surface; Passivation layer 102 is formed polymer layer 103.
With reference to figure 2, forming the convex lower metal layer (UnderBumpMetal, referred to as UBM) 105 covering described polymer layer 103 and part of solder pads layer 101 surface, described convex lower metal layer 105 is as conductive layer during follow-up plating formation metal post and Seed Layer; Described convex lower metal layer 105 forms mask layer 106, described mask layer 106 has the opening 107 exposing the weldering convex lower metal layer 105 of bed course 101 upper part.
With reference to figure 3, adopt electroplating technology at opening 107(with reference to figure 2) the full metal of middle filling, form metal post 108; Solder layer 109 is formed on metal post 108 surface.
With reference to figure 4, remove described mask layer 106(with reference to figure 3); Remove the convex lower metal layer 105 on polymer layer 103 surface of metal post 108 both sides, remove convex lower metal layer 105 without mask wet etching and can reduce plasma etching to the damage of metal post 108, and the residual of convex lower metal layer material on polymer layer 103 surface can be reduced; Solder layer is carried out reflux technique, forms convex point 110.
But, the reliability of the encapsulation structure of existing formation is poor, it is easy to lost efficacy.
Summary of the invention
The problem that the present invention solves how to improve the reliability and stability of device in packaging process.
For solving the problem, the present invention provides a kind of semiconductor package, comprising: the semiconductor-based end, and the described semiconductor-based end has weldering bed course; Cover the passivation layer of the described semiconductor-based end and part of solder pads layer, described passivation layer has the first opening of expose portion weldering bed course; It is positioned at the metal post of the first opening; Convex lower metal layer between metal post and weldering bed course, the edge of described convex lower metal layer has the undercut flaw to metal column bottom depression; Filling up the layer of compensation of described undercut flaw, the material of described layer of compensation is metal.
Optionally, the width of described layer of compensation is equal to or greater than the width of described undercut flaw, and the thickness of layer of compensation equals the thickness of convex lower metal layer.
Optionally, described layer of compensation thickness is greater than the thickness of convex lower metal layer, and layer of compensation covers the partial sidewall of described metal column bottom.
Optionally, the material of layer of compensation is identical with the material of convex lower metal layer or not identical, and the material of described layer of compensation is identical with metal column material or not identical.
Optionally, described layer of compensation is individual layer or multilayer lamination structure.
Optionally, described layer of compensation at least comprises the infiltration metal level contacted with convex lower metal layer.
Optionally, described layer of compensation is double stacked structure, and described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and fills the filler metal layer of undercut flaw.
Optionally, described infiltration metal level is one or more in nickel, titanium, tantalum.
Optionally, described filler metal layer is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
Optionally, also comprise: the diffusion impervious layer that is positioned on surface, metal column top, the convex point being positioned on diffusion impervious layer.
Compared with prior art, the technical scheme of the present invention has the following advantages:
The semiconductor package of the present invention has layer of compensation, layer of compensation can compensate the undercut flaw that metal column bottom is formed, the material of layer of compensation is metal, layer of compensation fills described undercut flaw, contact area between metal post and convex lower metal layer is increased and adhesion property enhancing, prevent the metal post from coming off and producing gap at the contact surface of metal post and convex lower metal layer, it is to increase the stability of semiconductor package and reliability.
Further, described layer of compensation thickness is greater than the thickness of convex lower metal layer, and layer of compensation covers the partial sidewall of described metal column bottom, layer of compensation not only fills undercut flaw, described layer of compensation also can the part surface of bottom sidewall of covering metal post, therefore layer of compensation not only plays the effect filling undercut flaw, and described layer of compensation also plays the effect supporting metal post and enlarge active surface.
Accompanying drawing explanation
Fig. 1��Fig. 4 is the cross-sectional view of prior art encapsulation structure-forming process;
Fig. 5��Figure 15 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor package.
Embodiment
Find after deliberation, existing employing removes, without mask wet etching, the convex lower metal layer not covered by metal post, easily produce undercut flaw, specifically please refer to Fig. 3 and Fig. 4, when taking metal post 108 as mask, when wet etching removes the convex lower metal layer 105 on the polymer layer 103 of metal post 108 both sides, due to isotropy when wet method is carved, when removing convex lower metal layer 105, easily the convex lower metal layer 105 of the part under metal post 108 is produced over etching, remaining convex lower metal layer 105 under metal post 108 is inwardly caved in, forms undercut flaw 112. The existence of undercut flaw 112 can make the base section of metal post 108 unsettled, metal post 108 is reduced with the contact area of convex lower metal layer 105, poor adhesion between metal post 108 and convex lower metal layer 105 and weldering bed course, and the conducting resistance between metal post 108 and weldering bed course is increased, when metal post 108 is subject to the stress of outside pressure or inside, easily come off or produce gap at the contact surface with convex lower metal layer, have impact on the stability of encapsulation structure and reliability.
The present invention provides a kind of semiconductor package and forming method thereof, after convex lower metal layer forms undercut flaw, layer of compensation is formed at undercut flaw place, the material of layer of compensation is metal, layer of compensation fills described undercut flaw, contact area between metal post and convex lower metal layer is increased and adhesion property strengthens, prevent metal post from coming off and in the contact surface generation gap of metal post with convex lower metal layer, it is to increase the stability of semiconductor package and reliability.
For enabling above-mentioned purpose, the feature and advantage of the present invention more become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail. When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this. In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 5��Figure 15 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor package.
First, please refer to Fig. 5, it is provided that the semiconductor-based end 200, the described semiconductor-based end 200 is formed weldering bed course 201; Form the passivation layer 202 covering the described semiconductor-based end 200 and part of solder pads layer 201 surface, described passivation layer 202 has first opening 204 on expose portion weldering bed course 201 surface.
Being formed with some inside chip (not shown)s, described weldering bed course 201 is connected with the inside chip at the semiconductor-based end 200 at described the semiconductor-based end 200, described weldering bed course 201 interface that is connected with external chip as inside chip.
The described semiconductor-based end 200 is individual layer or multilayer lamination structure, when semiconducter substrate 200 is multilayer lamination structure, and at least one layer of medium layer comprising semiconducter substrate He being positioned in semiconducter substrate. Described semiconductor substrate materials can be silicon (Si), germanium (Ge) or silicon germanium (GeSi), silicon carbide (SiC); Can also be silicon-on-insulator (SOI), germanium on insulator (GOI); Or can also be other material, such as gallium arsenide etc. III-V compounds of group.
The material of described weldering bed course 201 can be the combination of one or more in aluminium, copper, silver, gold, nickel, tungsten. Described weldering bed course 201 is for connecting the intrabasement inside chip of semi-conductor and outer containment component.
The material of described passivation layer 202 can be one or more in silicon nitride, silicon oxynitride, silicon oxide, borosilicate glass, phosphorosilicate glass or boron-phosphorosilicate glass. Described passivation layer 202 is for the protection of the semiconducter device of lower section and has the effect of electric isolation.
In the present embodiment, described passivation layer 202 being also formed with polymer layer 203, described polymer layer 203 is the organic materialss such as epoxy resin (Epoxy), polyimide (PI), benzocyclobutene, poly-isoxazolyl benzenesulfonamide. The isolation of described polymer layer 203 for encapsulating between structure and outside atmosphere, and the stress in buffer chip.
Then, please refer to Fig. 6, at the first opening 204(with reference to figure 5) sidewall and bottom and polymer layer 203 on form convex lower metal layer 205; Forming the first mask layer 206 covering described convex lower metal layer 205, described first mask layer 206 has the 2nd opening 207 of the convex lower metal layer 205 of part exposed on the first opening.
Described convex lower metal layer 205 electroplates conductive layer when forming metal post or Seed Layer as follow-up, and as the adhesion layer between metal post and weldering bed course.
Described convex lower metal layer 205 can be one or more in aluminium, nickel, copper, titanium, chromium, tantalum, gold and silver. Such as, convex lower metal layer 205 can be the double stacked structure of nickel copper, titanium, nickel aluminium.
The 2nd opening 207 in described first mask layer 206 defines the position of the metal post of follow-up formation. In the present embodiment, the material of described first mask layer 206 is photoresist material, forms the 2nd opening 207 in the photoresist by exposure and developing process.
Then, please refer to Fig. 7, at the 2nd opening 207(with reference to figure 6) middle formation metal post 208.
Forming described metal post 208 and adopt electroplating technology, described metal post 208 material is copper or the copper alloy containing other metals. Other metals described can be one or more in tantalum, indium, tin, zinc, manganese, chromium or nickel. Described metal post 208 can also be the metallic substance that other are suitable.
The top surface of metal post 208 can be equal to or less than the surface of the first mask layer 206.
It should be noted that, the formation of described metal post 208 can also adopt the technique that other are suitable.
With reference to figure 8, remove described first mask layer 206(with reference to figure 7); Etching removes the convex lower metal layer 205 of metal post 208 both sides, and bottom metal post 208, the edge of remaining convex lower metal layer 205 has the undercut flaw 212 to metal post 208 bottom notch.
Remove described first mask layer 206 and can adopt cineration technics.
Remove the convex lower metal layer 205 of described metal post 208 both sides, adopt wet-etching technology, when adopting wet-etching technology to remove convex lower metal layer 205, to metal post 208 and polymer layer 203(or passivation layer 202) damage less, and the residual of convex lower metal layer material can't be produced on polymer layer 203. But due to isotropic during wet etching, thus during the convex lower metal layer on the passivation layer 202 removing metal post 208 both sides, under metal post 208, remaining convex lower metal layer 205 can produce undercut flaw 212. The existence of undercut flaw 212, metal post 208 can be reduced with the contact area of remaining convex lower metal layer 205, make the poor adhesion between metal post 208 and remaining convex lower metal layer 205 and weldering bed course, and the conducting resistance between metal post 208 and weldering bed course is increased, when metal post 208 is subject to the stress of outside pressure or inside, easily come off or produce gap at the contact surface with convex lower metal layer, have impact on the stability of encapsulation structure and reliability.
Then with reference to figure 9, forming sacrifice layer 213 on the part passivation layer 202 of metal post 208 both sides, described sacrifice layer 213 fills described undercut flaw 212(with reference to figure 8).
Described sacrifice layer 213 is follow-up removes the cavity being formed and exposing undercut flaw, then can be formed the layer of compensation filling undercut flaw by selective chemical plating.
2nd mask material of the material of described sacrifice layer 213 and convex lower metal layer 205 material, metal post 208 material, polymer layer 203 material and follow-up formation is all not identical. when follow-up removal sacrifice layer 213 forms cavity so that sacrifice layer 213 has high etching selection ratio relative to metal level 205 material, metal post 208 material, polymer layer 203 material and the 2nd mask layer. in the embodiment of the present invention, the existence of sacrifice layer 213, after making follow-up formation the 2nd mask layer, sacrifice layer 213 can be removed by the 3rd opening in the 2nd mask layer, and then form the cavity of undercut flaw 212 or convex lower metal layer 205 sidewall, due to the metal post sidewall on metal post 208 top surface and cavity, and the convex lower metal layer 205 outside cavity is all covered by the 2nd mask layer, thus the passage consisted of the 3rd opening and cavity optionally can form the layer of compensation filling undercut flaw 212 on the sidewall of convex lower metal layer 205, improve the precision that bottom metal layer is formed.
The material of described sacrifice layer 213 can be SiO2, SiN, SiON, polysilicon or decolorizing carbon. The material of sacrifice layer 213 described in the present embodiment is SiO2��
The thickness of described sacrifice layer 213 equals the thickness of convex lower metal layer 205, the width of described sacrifice layer 213 is greater than undercut flaw 212(with reference to figure 8) width, during follow-up formation the 2nd mask layer, make the 2nd mask layer can the sidewall of covering metal post 208, the 3rd opening in 2nd mask layer exposes the surface of one end away from metal post of sacrifice layer, and the 3rd opening can not expose the sidewall surfaces of metal post 208.
In other embodiments of the invention, the thickness of described sacrifice layer is greater than the thickness (or height of undercut flaw) of convex lower metal layer, make the partial sidewall of the bottom of sacrifice layer covering metal post, the layer of compensation of follow-up formation is except filling undercut flaw, the partial sidewall of all right covering metal column bottom, the contact area of the bottom of metal post and convex lower metal layer increased, it is to increase adhesivity between the two.
The forming method of described sacrifice layer 213 is: form sacrificial material layer on the sidewall of described convex lower metal layer 205, metal post 208 sidewall and surface and polymer layer 203 surface; Without sacrificial material layer described in mask etching, the sidewall at convex lower metal layer 205 forms sacrifice layer 213.
In other embodiments of the invention, the forming process of described sacrifice layer 213 can also be: forms the sacrificial material layer covering described metal post 208 and polymer layer 203 surface; Return the described sacrificial material layer of etching so that the thickness of remaining sacrificial material layer is more than or equal to the thickness of convex lower metal layer 205; Form mask layer, the remaining sacrificial material layer of part of the top of described mask layer covering metal post 208 and sidewall surfaces and close convex lower metal layer 205 sidewall; Remove the remaining sacrificial material layer not covered by mask layer, form sacrifice layer 213.
Then, please refer to Figure 10, formed and cover described sacrifice layer 213, passivation layer 202(polymer layer 203) and the 2nd mask layer 214 of metal post 208, described 2nd mask layer 214 has the 3rd opening 215 away from metal post 208 end surface of exposure sacrifice layer 213.
The material of described 2nd mask layer 214 is photoresist material, forms the 3rd opening 215 by exposure and developing process in the 2nd mask layer 214.
Described 2nd mask layer 214 covers surface and the sidewall of described metal post, follow-up after removing sacrifice layer 213, it is possible to adopt selective chemical depositing process to form the layer of compensation filling undercut flaw.
Then, please refer to Figure 11, remove described sacrifice layer 213(with reference to Figure 10 along the 3rd opening 215), form cavity 216, described cavity 216 is connected with the 3rd opening 215, and exposes undercut flaw 212.
Remove described sacrifice layer 213 and adopt wet-etching technology, in the present embodiment, adopt hydrofluoric acid solution to remove described sacrifice layer 213.
After removing sacrifice layer 213, forming cavity 216, described cavity 216 exposes undercut flaw 212 or the sidewall of convex lower metal layer 205.
In other embodiments of the invention, when the thickness of described sacrifice layer 213 is greater than the thickness of convex lower metal layer 205, described cavity also exposes the partial sidewall of the bottom of metal post 208.
Then, please refer to Figure 12, along the 3rd opening 215 and cavity 216(with reference to Figure 11) formed and fill up described undercut flaw 212(with reference to Figure 11) layer of compensation 217, the material of described layer of compensation 217 is metal.
The material of described layer of compensation 217 can be one or more in nickel, titanium, tantalum, aluminium, tungsten, copper, silver, tin, platinum, gold.
The technique forming described layer of compensation 217 is selective chemical plating, and selective chemical plating can optionally form metal level (layer of compensation 217) on the surface of metal. In other embodiments of the invention, it is also possible to adopt suitable technique to form described layer of compensation.
Before carrying out selective chemical plating, also comprise oil removing and activating process. Described oil removing process is for removing oily matter and the zone of oxidation of convex lower metal layer 205 sidewall surfaces, convex lower metal layer 205 sidewall surfaces is made to keep degree of cleaning, oil removing process can adopt acidic solution to clean, in other embodiments, oil removing process can not also be comprised, aforementioned when removing sacrifice layer, it is possible to the time that proper extension is removed, convex lower metal layer 205 surface is cleaned; After carrying out oil removing process, carrying out activating process, form nucleation centre when being used for electroless plating with the sidewall surfaces at convex lower metal layer 205, described activating process can be zinc activating process.
Described layer of compensation 217 can be individual layer or multilayer lamination structure.
In the present embodiment, described layer of compensation 217 is double stacked structure, described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and fills the filler metal layer of undercut flaw, the adhesion of described infiltration metal level for improving between described convex lower metal layer and filler metal layer, and as diffusion impervious layer, the atoms metal phase mutual diffusion in convex lower metal layer and filler metal layer can be prevented.
Described infiltration metal level is one or more in nickel, titanium, tantalum, and described filler metal layer is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
In the embodiment of the present invention, by forming layer of compensation 217, described layer of compensation 217 fills undercut flaw, the contact area of metal post 208 and convex lower metal layer 205 is increased, improve adhesivity, and the material of layer of compensation 217 is metal, reduce the conducting resistance between metal post 208 and weldering bed course.
Then, please refer to Figure 13 and Figure 14, remove described 2nd mask layer 214(and please refer to Figure 12); Metal post 208 top surface forms diffusion impervious layer 209; Diffusion impervious layer 209 is formed convex point 211.
Remove described 2nd mask layer 214 and adopt cineration technics or other suitable technique.
Described diffusion impervious layer 209 is for preventing the metallographic phase mutual diffusion in metal post 208 and convex point 211, and improving the adhesivity between convex point 211 and metal post, the material of described diffusion impervious layer 209 is one or more in nickel, tin, tin lead, gold and silver, palladium and indium.
The material of described convex point 211 can be one or more in the metals such as tin, Xi Yin, tin lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony. After described diffusion impervious layer 209 forms solder layer, solder layer is carried out reflux technique, form convex point.
It should be noted that, the formation of described diffusion impervious layer 209 and solder layer after forming metal post 208, can be formed before removing the first mask layer.
In other embodiments of the invention, please refer to Figure 15, when the thickness of sacrifice layer is greater than the thickness of convex lower metal layer 205, the part surface of the bottom sidewall of corresponding cavity meeting exposing metal post 208 after removing sacrifice layer, therefore when adopting selective chemical plating to form layer of compensation 217, layer of compensation 217 is made not only to fill undercut flaw, described layer of compensation 217 also can the part surface of bottom sidewall of covering metal post 208, therefore layer of compensation 217 not only plays the effect filling undercut flaw, described layer of compensation 217 also plays the effect supporting metal post 208 and enlarge active surface, when metal post 108 is when being subject to the stress of outside pressure or inside, metal post is made to be not easy from convex lower metal layer 205 to come off or the contact surface of metal post 108 and convex lower metal layer 205 not easily produces gap.
The semiconductor package that aforesaid method is formed, please refer to Figure 14, comprise: the semiconductor-based end 200, the described semiconductor-based end 200, has weldering bed course 201, cover the passivation layer 202 of the described semiconductor-based end 200 and part of solder pads layer 201, described passivation layer 202 has the first opening of expose portion weldering bed course 201.
It is positioned at the metal post 208 of the first opening;
Convex lower metal layer 205 between metal post 208 and weldering bed course 201, the edge of described convex lower metal layer 205 has the undercut flaw to metal post 208 bottom notch;
Filling up the layer of compensation 217 of described undercut flaw, the material of described layer of compensation 217 is metal.
Concrete, the width of described layer of compensation 217 is equal to or greater than the width of described undercut flaw, and the thickness of described layer of compensation 217 equals the thickness of convex lower metal layer 205.
In other embodiments of the invention, with reference to Figure 15, described layer of compensation 217 thickness is greater than the thickness (being greater than the height of undercut flaw) of convex lower metal layer 205, and layer of compensation 217 covers the partial sidewall bottom described metal post 208.
The material of layer of compensation 217 is identical with the material of convex lower metal layer 205 or not identical, and the material of described layer of compensation 217 is identical with metal post 208 material or not identical.
Described layer of compensation 217 is individual layer or multilayer lamination structure.
In a specific embodiment, described layer of compensation 217 at least comprises the infiltration metal level contacted with convex lower metal layer.
In another specific embodiment, described layer of compensation 217 is double stacked structure, and described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and fills the filler metal layer of undercut flaw.
Described infiltration metal level is one or more in nickel, titanium, tantalum, and described filler metal layer is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
Also comprise: the polymer layer 203 being positioned on passivation layer 202.
Also comprise: the diffusion impervious layer 209 that is positioned on surface, metal column top 208, the convex point 211 being positioned on diffusion impervious layer 209.
Although present disclosure is as above, but the present invention is not defined in this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a semiconductor package, it is characterised in that, comprising:
The semiconductor-based end, the described semiconductor-based end, has weldering bed course;
Cover the passivation layer of the described semiconductor-based end and part of solder pads layer, described passivation layer has the first opening of expose portion weldering bed course;
It is positioned at the metal post of the first opening;
Convex lower metal layer between metal post and weldering bed course, the edge of described convex lower metal layer has the undercut flaw to metal column bottom depression;
Covering the 2nd mask layer of described convex lower metal layer and metal post, have the 3rd opening and cavity of connection in described 2nd mask layer, described 3rd opening is away from metal post surface, and described cavity exposes undercut flaw;
Filling up the layer of compensation of described undercut flaw, the material of described layer of compensation is metal, and described layer of compensation is positioned at cavity.
2. semiconductor package as claimed in claim 1, it is characterised in that, the width of described layer of compensation is equal to or greater than the width of described undercut flaw, and the thickness of layer of compensation equals the thickness of convex lower metal layer.
3. semiconductor package as claimed in claim 1, it is characterised in that, described layer of compensation thickness is greater than the thickness of convex lower metal layer, and layer of compensation covers the partial sidewall of described metal column bottom.
4. semiconductor package as claimed in claim 1, it is characterised in that, the material of layer of compensation is identical with the material of convex lower metal layer or not identical, and the material of described layer of compensation is identical with metal column material or not identical.
5. semiconductor package as claimed in claim 1, it is characterised in that, described layer of compensation is individual layer or multilayer lamination structure.
6. semiconductor package as claimed in claim 5, it is characterised in that, described layer of compensation at least comprises the infiltration metal level contacted with convex lower metal layer.
7. semiconductor package as claimed in claim 5, it is characterised in that, described layer of compensation is double stacked structure, and described double stacked structure comprises infiltration metal level, is positioned on infiltration metal level and fills the filler metal layer of undercut flaw.
8. semiconductor package as claimed in claims 6 or 7, it is characterised in that, described infiltration metal level is one or more in nickel, titanium, tantalum.
9. semiconductor package as claimed in claim 7, it is characterised in that, described filler metal layer is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
10. semiconductor package as claimed in claim 1, it is characterised in that, also comprise: the diffusion impervious layer that is positioned on surface, metal column top, the convex point being positioned on diffusion impervious layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310455301.9A CN103474407B (en) | 2013-09-29 | 2013-09-29 | Semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310455301.9A CN103474407B (en) | 2013-09-29 | 2013-09-29 | Semiconductor package |
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| CN103474407A CN103474407A (en) | 2013-12-25 |
| CN103474407B true CN103474407B (en) | 2016-06-01 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541366B1 (en) * | 2002-01-08 | 2003-04-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving a solder bump adhesion bond to a UBM contact layer |
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| KR20020094472A (en) * | 2001-06-12 | 2002-12-18 | 삼성전자 주식회사 | Method for fabricating Solder Bump for semiconductor packaging |
| TWI244184B (en) * | 2002-11-12 | 2005-11-21 | Siliconware Precision Industries Co Ltd | Semiconductor device with under bump metallurgy and method for fabricating the same |
| TWI298204B (en) * | 2005-11-21 | 2008-06-21 | Advanced Semiconductor Eng | Structure of bumps forming on an under metallurgy layer and method for making the same |
| TW201019440A (en) * | 2008-11-03 | 2010-05-16 | Int Semiconductor Tech Ltd | Bumped chip and semiconductor flip-chip device applied from the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6541366B1 (en) * | 2002-01-08 | 2003-04-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving a solder bump adhesion bond to a UBM contact layer |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |