CN103474407A - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
CN103474407A
CN103474407A CN2013104553019A CN201310455301A CN103474407A CN 103474407 A CN103474407 A CN 103474407A CN 2013104553019 A CN2013104553019 A CN 2013104553019A CN 201310455301 A CN201310455301 A CN 201310455301A CN 103474407 A CN103474407 A CN 103474407A
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Prior art keywords
layer
compensation
metal
protruding lower
semiconductor package
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CN2013104553019A
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CN103474407B (en
Inventor
石磊
陶玉娟
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements

Abstract

A semiconductor package structure comprises a semiconductor substrate, a passivation layer, a metal column, a convex lower metal layer and a compensation layer. The semiconductor substrate comprises a welding pad layer, the passivation layer covers the semiconductor substrate and one part of the welding pad layer, a first opening where one part of the welding pad layer is exposed is formed in the passivation layer, the metal column is positioned in the first opening, the convex lower metal layer is arranged between the metal column and the welding pad layer, undercut flaws sinking to the bottom of the metal column are formed in the edge of the convex lower metal layer, the undercut flaws are filled with the compensation layer, and the compensation layer is made of metal. The adhesion between the metal column and the convex lower metal layer is good, so that the stability and the reliability are improved.

Description

Semiconductor package
Technical field
The present invention relates to the semiconductor packages field, particularly a kind of semiconductor package.
Background technology
Semiconductor packages refers to and wafer is obtained to the process of individual chips according to product type and functional requirement processing.Existing semiconductor packages comprises the modes such as wire bond package and Flip-Chip Using.With the wire bond package mode, compare, it is high that the Flip-Chip Using mode has packaging density, excellent radiation performance, the high and high reliability of I/O (I/O) port density.
Flip-Chip Using mode early arranges weld pad on chip, and utilizes the salient point and the base plate for packaging that are arranged on weld pad (comprising the I/O weld pad) to be welded, and realizes chip package.Along with semicon industry to microminiaturized future development, be formed on wafer the density of chip increasing, accordingly, on wafer, the density of weld pad and salient point is increasing, distance between salient point is more and more less, the salient point that only utilizes larger volume directly and base plate for packaging weld the problem that is prone to the salient point bridge joint, i.e. the adjacent salient point connection that is short-circuited.
For solving salient point bridge joint problem, industry proposes intraconnections copper column technology (copper interconnect post technology).In intraconnections copper column technology, chip is connected on base plate for packaging by copper post and the salient point be positioned on the copper post.Due to the introducing of copper post, the thickness of salient point can significantly reduce, and between salient point, can have less spacing, so salient point bridge joint problem is weakened, and the introducing of copper post has simultaneously also reduced the electric capacity carrying (capacitance load) of encapsulated circuit.
Prior art discloses a kind of chip packaging method that adopts the Flip-Chip Using mode, comprising:
With reference to figure 1, semiconductor base 100 is provided, be formed with soldering pad layer 101 on described semiconductor base 100; Form the passivation layer 102 that covers described semiconductor base 100 and part of solder pads layer 101 surface, described passivation layer 102 has the opening 104 that exposes soldering pad layer 101 part surfaces; Form polymeric layer 103 on passivation layer 102.
With reference to figure 2, form the protruding lower metal layer (Under Bump Metal, referred to as UBM) 105 that covers described polymeric layer 103 and part of solder pads layer 101 surface, conductive layer and Seed Layer when described protruding lower metal layer 105 forms metal column as follow-up plating; Form mask layer 106 on described protruding lower metal layer 105, there is the opening 107 that exposes the protruding lower metal layer 105 of part on soldering pad layer 101 in described mask layer 106.
With reference to figure 3, adopt electroplating technology at opening 107(with reference to figure 2) in fill full metal, formation metal column 108; Form solder layer 109 on metal column 108 surfaces.
With reference to figure 4, remove described mask layer 106(with reference to figure 3); Remove the protruding lower metal layer 105 on polymeric layer 103 surfaces of metal column 108 both sides, remove protruding lower metal layer 105 without the mask wet etching and can reduce the damage of plasma etching to metal column 108, and can reduce residual on polymeric layer 103 surfaces of protruding lower metal layer material; Solder layer is carried out to reflux technique, form salient point 110.
But the reliability of the existing encapsulating structure formed is poor, easily loses efficacy.
Summary of the invention
The problem that the present invention solves is how to improve the reliability and stability of device in packaging technology.
For addressing the above problem, the invention provides a kind of semiconductor package, comprising: semiconductor base, described semiconductor base has soldering pad layer; Cover the passivation layer of described semiconductor base and part of solder pads layer, there is the first opening of expose portion soldering pad layer in described passivation layer; Be positioned at the metal column of the first opening; Protruding lower metal layer between metal column and soldering pad layer, the edge of described protruding lower metal layer has to the undercut flaw of metal column bottom notch; Fill up the layer of compensation of described undercut flaw, the material of described layer of compensation is metal.
Optionally, the width of described layer of compensation is equal to or greater than the width of described undercut flaw, and the thickness of layer of compensation equals the thickness of protruding lower metal layer.
Optionally, described layer of compensation thickness is greater than the thickness of protruding lower metal layer, and layer of compensation covers the partial sidewall of described metal column bottom.
Optionally, the material of layer of compensation is identical with the material of protruding lower metal layer or not identical, and the material of described layer of compensation is identical with the metal column material or not identical.
Optionally, described layer of compensation is the single or multiple lift stacked structure.
Optionally, described layer of compensation at least comprises the infiltration metal level contacted with protruding lower metal layer.
Optionally, described layer of compensation is the double stacked structure, and described double stacked structure comprises the infiltration metal level, is positioned at the filling metal level that infiltrates on metal level and fill undercut flaw.
Optionally, described infiltration metal level is one or more in nickel, titanium, tantalum.
Optionally, described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
Optionally, also comprise: be positioned at diffusion impervious layer on the metal column top surface, be positioned at the salient point on diffusion impervious layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
Semiconductor package of the present invention has layer of compensation, layer of compensation can compensate the undercut flaw that the metal column bottom forms, the material of layer of compensation is metal, layer of compensation is filled described undercut flaw, make the contact area between metal column and protruding lower metal layer increase and the adhesion property enhancing, prevent that metal column from coming off and, in the contact-making surface generation gap of metal column and protruding lower metal layer, improved stability and the reliability of semiconductor package.
Further, described layer of compensation thickness is greater than the thickness of protruding lower metal layer, and layer of compensation covers the partial sidewall of described metal column bottom, layer of compensation is not only filled undercut flaw, described layer of compensation also can the covering metal post the part surface of bottom sidewall, therefore layer of compensation not only plays the effect of filling undercut flaw, and described layer of compensation also plays the effect of supporting metal column and enlarge active surface.
The accompanying drawing explanation
The cross-sectional view that Fig. 1～Fig. 4 is prior art encapsulating structure forming process;
The cross-sectional view of the forming process that Fig. 5～Figure 15 is embodiment of the present invention semiconductor package.
Embodiment
Find after deliberation, the existing protruding lower metal layer do not covered by metal column without the removal of mask wet etching that adopts is, easily produce undercut flaw, specifically please refer to Fig. 3 and Fig. 4, when take metal column 108 as mask, when wet etching is removed the protruding lower metal layer 105 on the polymeric layer 103 of metal column 108 both sides, isotropism while carving due to wet method, when removing protruding lower metal layer 105, easily the protruding lower metal layer 105 of the part under metal column 108 is produced to over etching, under making metal column 108, remaining protruding lower metal layer 105 caves inward, and forms undercut flaw 112.The existence of undercut flaw 112 can make the base section of metal column 108 unsettled, make metal column 108 and the contact area of protruding lower metal layer 105 reduce, adhesiveness variation between metal column 108 and protruding lower metal layer 105 and soldering pad layer, and make the conducting resistance between metal column 108 and soldering pad layer increase, when metal column 108 is subject to the stress of outside pressure or inside, easily come off or produce gap at the contact-making surface with protruding lower metal layer, having affected stability and the reliability of encapsulating structure.
The invention provides a kind of semiconductor package and forming method thereof, after protruding lower metal layer forms undercut flaw, form layer of compensation at the undercut flaw place, the material of layer of compensation is metal, layer of compensation is filled described undercut flaw, make the contact area between metal column and protruding lower metal layer increase and the adhesion property enhancing, prevent that metal column from coming off and, in the contact-making surface generation gap of metal column and protruding lower metal layer, improved stability and the reliability of semiconductor package.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.When the embodiment of the present invention is described in detail in detail, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.The three-dimensional space that in actual fabrication, should comprise in addition, length, width and the degree of depth.
The cross-sectional view of the forming process that Fig. 5～Figure 15 is embodiment of the present invention semiconductor package.
At first, please refer to Fig. 5, semiconductor base 200 is provided, on described semiconductor base 200, be formed with soldering pad layer 201; Form the passivation layer 202 that covers described semiconductor base 200 and part of solder pads layer 201 surface, there is first opening 204 on expose portion soldering pad layer 201 surfaces in described passivation layer 202.
Be formed with some inside chip (not shown)s in described semiconductor base 200, described soldering pad layer 201 is connected with the inside chip in semiconductor base 200, described soldering pad layer 201 interface be connected with external chip as inside chip.
Described semiconductor base 200 is the single or multiple lift stacked structure, when Semiconductor substrate 200 is the multiple-level stack structure, comprises Semiconductor substrate and is positioned at least one deck dielectric layer on Semiconductor substrate.Described semiconductor substrate materials can be silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC); Can be also silicon-on-insulator (SOI), germanium on insulator (GOI); Perhaps can also be for other material, such as the III such as GaAs-V compounds of group.
The material of described soldering pad layer 201 can be one or more the combination in aluminium, copper, silver, gold, nickel, tungsten.Described soldering pad layer 201 is for connecting inside chip and the outer enclosure parts in semiconductor base.
The material of described passivation layer 202 can be one or more in silicon nitride, silicon oxynitride, silica, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass.Described passivation layer 202 is for the protection of the semiconductor device of below the effect with electric isolation.
In the present embodiment, on described passivation layer 202, also be formed with polymeric layer 203, described polymeric layer 203 is the organic materials such as epoxy resin (Epoxy), polyimides (PI), benzocyclobutene, polyphenyl oxazole.Described polymeric layer 203 is for the isolation between encapsulating structure and external environment condition, and the stress in buffer chip.
Then, please refer to Fig. 6, at the first opening 204(with reference to figure 5) sidewall and bottom and polymeric layer 203 on form protruding lower metal layer 205; Form the first mask layer 206 that covers described protruding lower metal layer 205, described the first mask layer 206 has the second opening 207 that exposes the protruding lower metal layer 205 of part on the first opening.
Conductive layer or Seed Layer when described protruding lower metal layer 205 forms metal column as follow-up plating, and as the adhesion layer between metal column and soldering pad layer.
Described protruding lower metal layer 205 can be one or more in aluminium, nickel, copper, titanium, chromium, tantalum, gold, silver.Such as, protruding lower metal layer 205 can be the double stacked structure of ambrose alloy, titanium, nickel aluminium.
The position of the metal column of the follow-up formation of the second opening 207 definition in described the first mask layer 206.In the present embodiment, the material of described the first mask layer 206 is photoresist, by exposure and developing process, forms the second opening 207 in photoresist.
Then, please refer to Fig. 7, at the second opening 207(with reference to figure 6) in form metal column 208.
Form described metal column 208 and adopt electroplating technologies, described metal column 208 materials are copper or the copper alloy that contains other metals.Described other metals can be one or more in tantalum, indium, tin, zinc, manganese, chromium or nickel.Described metal column 208 can be also other suitable metal materials.
The top surface of metal column 208 can be equal to or less than the surface of the first mask layer 206.
It should be noted that, the formation of described metal column 208 also can adopt other suitable techniques.
With reference to figure 8, remove described the first mask layer 206(with reference to figure 7); Etching is removed the protruding lower metal layer 205 of metal column 208 both sides, and the edge of the metal column 208 remaining protruding lower metal layers 205 in bottom has to the undercut flaw 212 of metal column 208 bottom notch.
Remove described the first mask layer 206 and can adopt cineration technics.
Remove the protruding lower metal layer 205 of described metal column 208 both sides, adopt wet-etching technology, while adopting wet-etching technology to remove protruding lower metal layer 205, to metal column 208 and polymeric layer 203(or passivation layer 202) damage less, and can't on polymeric layer 203, produce the residual of protruding lower metal layer material.But isotropic during due to wet etching, thereby during the protruding lower metal layer on removing the passivation layer 202 of metal column 208 both sides, under metal column 208, remaining protruding lower metal layer 205 can produce undercut flaws 212.The existence of undercut flaw 212, make metal column 208 and the contact area of remaining protruding lower metal layer 205 to reduce, make the adhesiveness variation between metal column 208 and remaining protruding lower metal layer 205 and soldering pad layer, and make the conducting resistance between metal column 208 and soldering pad layer increase, when metal column 208 is subject to the stress of outside pressure or inside, easily come off or produce gap at the contact-making surface with protruding lower metal layer, having affected stability and the reliability of encapsulating structure.
Then, with reference to figure 9, form sacrifice layer 213 on the part passivation layer 202 of metal column 208 both sides, described sacrifice layer 213 is filled described undercut flaw 212(with reference to figure 8).
The follow-up removal of described sacrifice layer 213 forms the cavity that exposes undercut flaw, then by selective chemical plating, can form the layer of compensation of filling undercut flaw.
The material of described sacrifice layer 213 is all not identical with the second mask material of protruding lower metal layer 205 materials, metal column 208 materials, polymeric layer 203 materials and follow-up formation.When follow-up removal sacrifice layer 213 forms cavity, make sacrifice layer 213 there is high etching selection ratio with respect to metal level 205 materials, metal column 208 materials, polymeric layer 203 materials and the second mask layer.In the embodiment of the present invention, the existence of sacrifice layer 213, after making follow-up formation the second mask layer, can remove sacrifice layer 213 by the 3rd opening in the second mask layer, and then the cavity of formation undercut flaw 212 or protruding lower metal layer 205 sidewalls, due to the metal column sidewall on metal column 208 top surfaces and cavity, and the outer protruding lower metal layer 205 of cavity is all covered by the second mask layer, thereby the passage formed by the 3rd opening and cavity can optionally form the layer of compensation of filling undercut flaw 212 on the sidewall of protruding lower metal layer 205, improved the precision that bottom metal layer forms.
The material of described sacrifice layer 213 can be SiO 2, SiN, SiON, polysilicon or amorphous carbon.The material of sacrifice layer described in the present embodiment 213 is SiO 2.
The thickness of described sacrifice layer 213 equals the thickness of protruding lower metal layer 205, the width of described sacrifice layer 213 is greater than undercut flaw 212(with reference to figure 8) width, during follow-up formation the second mask layer, make the sidewall that the second mask layer can covering metal post 208, the 3rd opening in the second mask layer exposes the surface of the end away from metal column of sacrifice layer, and the 3rd opening can not expose the sidewall surfaces of metal column 208.
In other embodiments of the invention, the thickness of described sacrifice layer is greater than the thickness (or height of undercut flaw) of protruding lower metal layer, make the partial sidewall of the bottom of sacrifice layer covering metal post, the layer of compensation of follow-up formation is except filling undercut flaw, the partial sidewall of all right covering metal column bottom, make the bottom of metal column and the contact area of protruding lower metal layer increase, improved adhesiveness between the two.
The formation method of described sacrifice layer 213 is: sidewall, metal column 208 sidewalls and surface and polymeric layer 203 surfaces at described protruding lower metal layer 205 form sacrificial material layer; Without the described sacrificial material layer of mask etching, at the sidewall formation sacrifice layer 213 of protruding lower metal layer 205.
In other embodiments of the invention, the forming process of described sacrifice layer 213 can also be: form the sacrificial material layer that covers described metal column 208 and polymeric layer 203 surfaces; Return the described sacrificial material layer of etching, make the thickness of remaining sacrificial material layer be more than or equal to the thickness of protruding lower metal layer 205; Form mask layer, the remaining sacrificial material layer of part of the top of described mask layer covering metal post 208 and sidewall surfaces and close protruding lower metal layer 205 sidewalls; Remove the remaining sacrificial material layer do not covered by mask layer, form sacrifice layer 213.
Then, please refer to Figure 10, form to cover described sacrifice layer 213, passivation layer 202(polymeric layer 203) and the second mask layer 214 of metal column 208, there is the 3rd opening 215 away from metal column 208 1 end surfaces of exposure sacrifice layer 213 in described the second mask layer 214.
The material of described the second mask layer 214 is photoresist, by exposure and developing process, forms the 3rd opening 215 in the second mask layer 214.
Described the second mask layer 214 covers surface and the sidewall of described metal column, follow-up after removing sacrifice layer 213, can adopt the selective chemical depositing process to form the layer of compensation of filling undercut flaw.
Then, please refer to Figure 11, along the 3rd opening 215, remove described sacrifice layer 213(with reference to Figure 10), form cavity 216, described cavity 216 is communicated with the 3rd opening 215, and exposes undercut flaw 212.
Remove described sacrifice layer 213 and adopt wet-etching technology, in the present embodiment, adopt hydrofluoric acid solution to remove described sacrifice layer 213.
After removing sacrifice layer 213, form cavity 216, described cavity 216 exposes the sidewall of undercut flaw 212 or protruding lower metal layer 205.
In other embodiments of the invention, when the thickness of described sacrifice layer 213 is greater than the thickness of protruding lower metal layer 205, described cavity also exposes the partial sidewall of the bottom of metal column 208.
Then, please refer to Figure 12, along the 3rd opening 215 and cavity 216(with reference to Figure 11) form and fill up described undercut flaw 212(with reference to Figure 11) and layer of compensation 217, the material of described layer of compensation 217 is metal.
The material of described layer of compensation 217 can be one or more in nickel, titanium, tantalum, aluminium, tungsten, copper, silver, tin, platinum, gold.
The technique that forms described layer of compensation 217 is selective chemical plating, and selective chemical plating can optionally form metal level (layer of compensation 217) at metallic surface.In other embodiments of the invention, also can adopt suitable technique to form described layer of compensation.
Before carrying out selective chemical plating, also comprise oil removing and activating process.Described oil removing process is for removing oily matter and the oxide layer of protruding lower metal layer 205 sidewall surfaces, make protruding lower metal layer 205 sidewall surfaces degree of keeping clean, oil removing process can adopt acid solution to clean, in other embodiments, also can not comprise oil removing process, aforementioned when removing sacrifice layer, as can proper extension the to remove time, protruding lower metal layer 205 surfaces are cleaned; After carrying out oil removing process, carry out activating process, the nuclearing centre while with the sidewall surfaces at protruding lower metal layer 205, being formed for chemical plating, described activating process can be the zinc activating process.
Described layer of compensation 217 can be the single or multiple lift stacked structure.
In the present embodiment, described layer of compensation 217 is the double stacked structure, described double stacked structure comprises the infiltration metal level, is positioned at the filling metal level that infiltrates on metal level and fill undercut flaw, described infiltration metal level is for improving described protruding lower metal layer and filling the adhesion between metal level, and can be used as diffusion impervious layer, prevent protruding lower metal layer and fill the metallic atom phase counterdiffusion in metal level.
Described infiltration metal level is one or more in nickel, titanium, tantalum, and described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
In the embodiment of the present invention, by forming layer of compensation 217, described layer of compensation 217 is filled undercut flaw, make the contact area of metal column 208 and protruding lower metal layer 205 increase, improved adhesiveness, and the material of layer of compensation 217 is metal, reduced the conducting resistance between metal column 208 and soldering pad layer.
Then, please refer to Figure 13 and Figure 14, remove described the second mask layer 214(and please refer to Figure 12); Form diffusion impervious layer 209 on metal column 208 top surfaces; Form salient point 211 on diffusion impervious layer 209.
Remove described the second mask layer 214 and adopt cineration technics or other suitable technique.
Described diffusion impervious layer 209 is for preventing the Metal Phase counterdiffusion of metal column 208 and salient point 211, and improving the adhesiveness between salient point 211 and metal column, the material of described diffusion impervious layer 209 is one or more in nickel, tin, tin lead, gold, silver, palladium and indium.
The material of described salient point 211 can be one or more in the metals such as tin, Xi Yin, tin lead, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony.Form solder layer on described diffusion impervious layer 209 after, solder layer is carried out to reflux technique, form salient point.
It should be noted that, the formation of described diffusion impervious layer 209 and solder layer can, after forming metal column 208, be removed the first mask layer and form before.
In other embodiments of the invention, please refer to Figure 15, when the thickness of sacrifice layer is greater than the thickness of protruding lower metal layer 205, the part surface of the bottom sidewall of corresponding cavity meeting exposing metal post 208 after the removal sacrifice layer, therefore when adopting selective chemical plating to form layer of compensation 217, make layer of compensation 217 not only fill undercut flaw, described layer of compensation 217 also can covering metal post 208 the part surface of bottom sidewall, therefore layer of compensation 217 not only plays the effect of filling undercut flaw, described layer of compensation 217 also plays the effect of supporting metal column 208 and enlarge active surface, when metal column 108 when being subject to outside pressure or inner stress, make metal column be not easy to come off or metal column 108 and the difficult gap that produces of the contact-making surface of protruding lower metal layer 205 from protruding lower metal layer 205.
The semiconductor package that said method forms, please refer to Figure 14, comprise: semiconductor base 200, described semiconductor base 200 has soldering pad layer 201, cover the passivation layer 202 of described semiconductor base 200 and part of solder pads layer 201, there is the first opening of expose portion soldering pad layer 201 in described passivation layer 202.
Be positioned at the metal column 208 of the first opening;
Protruding lower metal layer 205 between metal column 208 and soldering pad layer 201, the edge of described protruding lower metal layer 205 has to the undercut flaw of metal column 208 bottom notch;
Fill up the layer of compensation 217 of described undercut flaw, the material of described layer of compensation 217 is metal.
Concrete, the width of described layer of compensation 217 is equal to or greater than the width of described undercut flaw, and the thickness of described layer of compensation 217 equals the thickness of protruding lower metal layer 205.
In other embodiments of the invention, with reference to Figure 15, described layer of compensation 217 thickness are greater than the thickness (being greater than the height of undercut flaw) of protruding lower metal layer 205, and layer of compensation 217 covers the partial sidewall of described metal column 208 bottoms.
The material of layer of compensation 217 is identical or not identical with the material of protruding lower metal layer 205, and the material of described layer of compensation 217 is identical with metal column 208 materials or not identical.
Described layer of compensation 217 is the single or multiple lift stacked structure.
In a specific embodiment, described layer of compensation 217 at least comprises the infiltration metal level contacted with protruding lower metal layer.
In another specific embodiment, described layer of compensation 217 is the double stacked structure, and described double stacked structure comprises the infiltration metal level, is positioned at the filling metal level that infiltrates on metal level and fill undercut flaw.
Described infiltration metal level is one or more in nickel, titanium, tantalum, and described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
Also comprise: be positioned at the polymeric layer 203 on passivation layer 202.
Also comprise: be positioned at the lip-deep diffusion impervious layer 209 in metal column top 208, be positioned at the salient point 211 on diffusion impervious layer 209.
Although the present invention discloses as above, the present invention not is defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.

Claims (10)

1. a semiconductor package, is characterized in that, comprising:
Semiconductor base, described semiconductor base has soldering pad layer;
Cover the passivation layer of described semiconductor base and part of solder pads layer, there is the first opening of expose portion soldering pad layer in described passivation layer;
Be positioned at the metal column of the first opening;
Protruding lower metal layer between metal column and soldering pad layer, the edge of described protruding lower metal layer has to the undercut flaw of metal column bottom notch;
Fill up the layer of compensation of described undercut flaw, the material of described layer of compensation is metal.
2. semiconductor package as claimed in claim 1, is characterized in that, the width of described layer of compensation is equal to or greater than the width of described undercut flaw, and the thickness of layer of compensation equals the thickness of protruding lower metal layer.
3. semiconductor package as claimed in claim 1, is characterized in that, described layer of compensation thickness is greater than the thickness of protruding lower metal layer, and layer of compensation covers the partial sidewall of described metal column bottom.
4. semiconductor package as claimed in claim 1, is characterized in that, the material of layer of compensation is identical with the material of protruding lower metal layer or not identical, and the material of described layer of compensation is identical with the metal column material or not identical.
5. semiconductor package as claimed in claim 1, is characterized in that, described layer of compensation is the single or multiple lift stacked structure.
6. semiconductor package as claimed in claim 5, is characterized in that, described layer of compensation at least comprises the infiltration metal level contacted with protruding lower metal layer.
7. semiconductor package as claimed in claim 5, is characterized in that, described layer of compensation is the double stacked structure, and described double stacked structure comprises the infiltration metal level, is positioned at the filling metal level that infiltrates on metal level and fill undercut flaw.
8. semiconductor package as described as claim 6 or 7, is characterized in that, described infiltration metal level is one or more in nickel, titanium, tantalum.
9. semiconductor package as claimed in claim 7, is characterized in that, described filling metal level is one or more in aluminium, tungsten, copper, silver, tin, platinum, gold.
10. semiconductor package as claimed in claim 1, is characterized in that, also comprises: be positioned at diffusion impervious layer on the metal column top surface, be positioned at the salient point on diffusion impervious layer.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020094472A (en) * 2001-06-12 2002-12-18 삼성전자 주식회사 Method for fabricating Solder Bump for semiconductor packaging
US6541366B1 (en) * 2002-01-08 2003-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving a solder bump adhesion bond to a UBM contact layer
US20040092092A1 (en) * 2002-11-12 2004-05-13 Siliconware Precision Industries, Ltd. Semiconductor device with under bump metallurgy and method for fabricating the same
US20070117368A1 (en) * 2005-11-21 2007-05-24 Chi-Long Tsai Structure of bumps forming on an under metallurgy layer and method for making the same
US20100109159A1 (en) * 2008-11-03 2010-05-06 Chih-Wen Ho Bumped chip with displacement of gold bumps

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020094472A (en) * 2001-06-12 2002-12-18 삼성전자 주식회사 Method for fabricating Solder Bump for semiconductor packaging
US6541366B1 (en) * 2002-01-08 2003-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving a solder bump adhesion bond to a UBM contact layer
US20040092092A1 (en) * 2002-11-12 2004-05-13 Siliconware Precision Industries, Ltd. Semiconductor device with under bump metallurgy and method for fabricating the same
US20070117368A1 (en) * 2005-11-21 2007-05-24 Chi-Long Tsai Structure of bumps forming on an under metallurgy layer and method for making the same
US20100109159A1 (en) * 2008-11-03 2010-05-06 Chih-Wen Ho Bumped chip with displacement of gold bumps

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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288

Patentee after: Tongfu Microelectronics Co., Ltd.

Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong