CN103425437A - Initial written address selection method and device - Google Patents
Initial written address selection method and device Download PDFInfo
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- CN103425437A CN103425437A CN2012101657280A CN201210165728A CN103425437A CN 103425437 A CN103425437 A CN 103425437A CN 2012101657280 A CN2012101657280 A CN 2012101657280A CN 201210165728 A CN201210165728 A CN 201210165728A CN 103425437 A CN103425437 A CN 103425437A
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Abstract
The invention discloses an initial written address selection method and belongs to the field of electrical digital data. The method includes: receiving a data writing command sent to a storage structure; determining an address of a MOD(M1+N,M)-th storage unit as a temporary initial written address according to a M1-th storage unit corresponding to the last initial written address; judging whether a cumulative number of current write requests in a counter of the storage unit corresponding to the temporary initial written address is a maximum among all counters or not; if not, determining the temporary initial written address as a current initial written address. According to the method, the last initial written address is determined as the temporary initial written address; the temporary initial written address is determined as the current initial written address when the accumulative number of the current write requests in the counter of the storage unit corresponding to the temporary initial written address is not the maximum among all counters; accordingly, data are written evenly and bandwidth utilization ratio is increased.
Description
Technical field
The present invention relates to electric digital data processing field, particularly a kind of initial writing address system of selection and device.
Background technology
Storer is for storing the device of data in the hardware devices such as computing machine or server.In prior art, storer commonly used has SRAM(Static Random Access Memory, static RAM), DDR(Double Data Rate Synchronous Dynamic Random Access Memory, the Double Data Rate synchronous DRAM), QDR(Quad Data Rate Synchronous Dynamic Random Access Memory, the Quad Data Rate synchronous DRAM) etc.The multi-disc storer can form jumbo storage organization to meet the big data quantity needs in when storage.
Please refer to Fig. 1, it shows a kind of structural representation of existing storage organization.This storage organization includes 6 PMC(Packet Memory Controller, the bag memory controller), each PMC controls two DDR, including again 8 bank(in every DDR is the physical store body, for storing data, herein referred to as storage unit).DDR in each PMC, each PMC and the bank in each DDR independently are numbered respectively simultaneously, 6 bag memory controllers are numbered respectively PMC0-PMC5, comprise two random access memory of DDR0-DDR1 in each bag memory controller, comprise again eight physical store bodies of bank0-bank7 in each random access memory.The intrinsic memory mechanism based on DDR, each bank single write operation can write 32B(Byte, byte) data, each PMC single operation can write the data of 64B.
In the time need on storage organization, carrying out the read-write of big data quantity, in order to guarantee that data are at every DDR, with carrying out in each bank of every DDR, relatively write uniformly, to reach the minimizing read/write conflict, the maximum effect that improves bandwidth ability.Prior art provides a kind of initial writing address system of selection: the first, and external chip receives the data that storage organization is sent and writes instruction; The second, external chip generate at random one No. PMC, No. DDR and No. bank, and No. PMC of will generate at random, No. DDR and No. bank corresponding bank are as initial writing address; The 3rd, external chip is initiated write request to PMC, and from initial writing address, corresponding bank starts to carry out data according to predetermined write sequence and writes in request.Predetermined write sequence refers to while often writing the 32B data, adds one No. DDR; Often write the 64B data and add one No. PMC; While often writing the 64*6B data, add one No. bank.
In realizing process of the present invention, the inventor finds that at least there is following problem in prior art:
In existing initial writing address system of selection, although can guarantee the homogeneity of data writing from long-term use procedure, but inhomogeneous situation may appear writing in the short time use procedure, such as: storage organization as shown in Figure 1, in carrying out the process of 96 data writings continuously, certain several adjacent or close bank may repeatedly be chosen as initial writing address, and corresponding, some adjacent or close bank may be never selected in addition.
Summary of the invention
For solve data write inhomogeneous, the problem that bandwidth availability ratio is low, the embodiment of the present invention provides a kind of initial writing address system of selection and memory controller.Described technical scheme is as follows:
On the one hand, provide a kind of initial writing address system of selection, described method comprises:
The data that reception is sent storage organization write instruction, described storage organization comprises memory controller and M storage unit, each storage unit has address sum counter separately, and each counter is for preserving the current write request cumulative number of corresponding stored unit;
According to the corresponding M of initial writing address last time
1Individual storage unit is determined MOD(M
1+ N, M) address of individual storage unit is as tentative initial writing address;
Judge whether the current write request cumulative number in the counter of described tentative initial writing address institute's corresponding stored unit is the maximal value in all counters;
If not, described tentative initial writing address is defined as to this initial writing address;
Wherein, M is more than or equal to 2 integer; M
1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integer and be not the approximate number of M.
On the other hand, provide a kind of initial writing address selecting arrangement, described device comprises:
Command reception module and address selection module;
Described command reception module, write instruction for receiving the data that storage organization is sent, described storage organization comprises memory controller and M storage unit, each storage unit has address sum counter separately, and each counter is for preserving the current write request cumulative number of corresponding stored unit;
Described address selection module comprises:
The address determining unit, for according to the corresponding M of initial writing address last time
1Individual storage unit is determined MOD(M
1+ N, M) address of individual storage unit is as tentative initial writing address;
Whether the first judging unit is the maximal value in all counters for the current write request cumulative number of the counter that judges tentative initial writing address institute's corresponding stored unit that described address determining unit is determined;
Described address determining unit, if also, for the maximal value in the not all counter of current write request cumulative number of the counter of the described tentative initial writing address institute's corresponding stored of described the first judgment unit judges unit, will describedly fix tentatively initial writing address and be defined as this initial writing address;
Wherein, M is more than or equal to 2 integer; M
1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integer and be not the approximate number of M.
The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:
By to have data to write fashionable at every turn, according to the corresponding M of initial writing address last time
1Individual storage unit is determined MOD(M
1+ N, M) address of individual storage unit is as tentative initial writing address, and during the maximal value in the not all counter of current write request cumulative number in counter of judging this tentative initial writing address institute's corresponding stored unit, determine tentative initial writing address to be this initial writing address, reach even data writing in buffer memory, promote the purpose of bandwidth availability ratio.
The accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, in below describing embodiment, the accompanying drawing of required use is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of the buffer structure that provides of background technology of the present invention;
Fig. 2 is the method flow diagram of the initial writing address system of selection that provides of the embodiment of the present invention one;
Fig. 3 is the method flow diagram of the initial writing address system of selection that provides of the embodiment of the present invention two;
Fig. 4 is the pointer repeating query schematic diagram that the embodiment of the present invention two provides;
Fig. 5 is the memory cell arrangement coordinate schematic diagram sequentially that the embodiment of the present invention two provides;
Fig. 6 is the structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Fig. 7 is the another kind of structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Fig. 8 is another structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Fig. 9 is another structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Figure 10 is also a kind of structural representation of the initial writing address selecting arrangement that provides of the embodiment of the present invention three;
Figure 11 is the structural representation of the request sending module that provides of the embodiment of the present invention three.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment mono-
Refer to Fig. 2, it shows a kind of method flow diagram of initial writing address system of selection, and this initial writing address system of selection can be applied to the storage organization shown in Fig. 1.The initial writing address system of selection that the embodiment of the present invention provides can comprise:
Wherein, storage organization comprises memory controller and M storage unit, and each storage unit has address sum counter separately, and each counter is for preserving the current write request cumulative number of corresponding stored unit.
Wherein N is default step-length, M is more than or equal to 2 integer, in addition, in order to reach the initial writing address of uniform design, so that the purpose of even data writing in buffer memory, need to be in the process of the tentative initial writing address of Continuous Selection M can each storage unit of rotation visit (repeating query), therefore, N can be for 1 or for being less than M and not being the positive integer of M approximate number (being that M can not be divided exactly by N).MOD(M
1+ N, M) mean (M
1+ N)/M remainder number: if M
1+ N is less than M, MOD(M
1+ N, M)=M
1+ N, select M
1+ N the corresponding address of storage unit is tentative initial writing address; If M
1+ N is greater than M, MOD(M
1+ N, M)=M
1+ N-M, select M
1+ N-M the corresponding address of storage unit is tentative initial writing address.
In practical application, the method of the tentative initial writing address of this step 102 selection can be by arranging the pointer that points to the bank address, pointer is realized according to the predetermined step-length N repeating query mode of (progressively increase behind last bank address when pointer, return to first bank address and continue to progressively increase) of progressively increasing.By this step, can by each storage unit in a fixed order poll once, no matter can reach the short time or add up for a long time, be all the effect evenly write.
Consider the execution speed of hardware, there are data to write fashionable at every turn, first calculate the numerical value of the counter that all bank are corresponding, get the maximal value in all counters, and whether be the peaked bit sequence in all counters according to the current write request cumulative number in the numerical value acquisition individual count device of the current write request cumulative number in this maximal value and individual count device, whether the current write request cumulative number that the value of T numerical value in this bit sequence characterizes in T counter is the maximal value in all counters, wherein, T is greater than 0 integer that is less than or equal to M.By this step, can jump peaked mechanism by realizing, make the write request cumulative number on each bank as far as possible even.
If be somebody's turn to do the maximal value in the not all counter of numerical value of fixing tentatively write request cumulative number in the bank that initial writing address is corresponding, should fix tentatively initial writing address as this initial writing address.
In sum, the initial writing address system of selection that the present embodiment one provides, according to the corresponding M of initial writing address last time
1individual storage unit is determined MOD(M
1+ N, M) address of individual storage unit as tentative initial writing address (due to N be 1 or N be to be less than M and be not the positive integer of M approximate number, thereby can be in the process of Continuous Selection M tentative initial writing address, can repeating query to each storage unit), and during the maximal value in the not all counter of current write request cumulative number in counter of judging this tentative initial writing address institute's corresponding stored unit, determine tentative initial writing address to be this initial writing address, reach even data writing in buffer memory, promote the purpose of bandwidth availability ratio, storage organization as shown in Figure 1, than prior art, the method that the present embodiment provides can repeating query arrive each bank in the process of continuous 96 tentative initial writing positions of selection, thereby provides than better homogeneity and the higher bandwidth availability ratio of writing of prior art.
Embodiment bis-
Initial writing address system of selection for more detailed description embodiment mono-provides, refer to Fig. 2, and it shows a kind of method flow diagram of initial writing address system of selection, and the method can be applied to all kinds of servers that relate to the Large Volume Data buffer memory.Still take that to be applied at the storage organization shown in Fig. 1 be example, this initial writing address system of selection can realize in the external chip that utilizes same bus to be connected with storage organization, and the initial writing address system of selection that the embodiment of the present invention provides can comprise:
Step 201, external chip is received in the instruction of data writing in storage organization;
While having data stream will write in storage organization in bus, the external core sector-meeting receives the instruction of data writing in storage organization.
Step 202, according to the corresponding M of initial writing address last time
1Individual storage unit is determined MOD(M
1+ N, M) address of individual storage unit is as tentative initial writing address;
Wherein, storage organization comprises one or more memory controllers, and M bank(storage unit controlling of memory controller); N is default step-length, and M is more than or equal to 2 integer, N be 1 or N be positive integer and be not the approximate number of M.Concrete storage organization as shown in Figure 1, storage organization includes 6 memory controllers, and M=6*2*8=96 bank.Wherein, default step-length N can be 7.
The mode that complementation in this step can be progressively increased according to predetermined step-length by the repeating query pointer in actual applications realizes same effect.Concretely, each bank has an address for read-write and one separately for preserving the counter of the current write request cumulative number of corresponding bank, and the address sum counter of each bank is corresponding one by one.External chip sets in advance a counter corresponding to each bank of repeating query pointed, and after the instruction that receives data writing in storage organization, the repeating query pointer, on the counter basis of the corresponding bank of initial writing address last time, is progressively increased by default step-length 7.Please in conjunction with the pointer repeating query schematic diagram with reference to shown in figure 4, if default step-length is 7.Before progressively increasing, the 1st counter corresponding to bank of repeating query pointed; After progressively increasing, the 8th corresponding counter of bank of repeating query pointed, again progressively increase and point to the 15th the corresponding counter of bank; If progressively increase, after the counter that any one bank is corresponding in last 6 bank, while again progressively increasing, the repeating query pointer returns to counter corresponding in the 1st to 6 bank.
In other words, if take in each DDR shown in Fig. 1 the storage organization that comprises 8 bank is example, before supposing to progressively increase, counter corresponding to bank that repeating query pointed (PMC0, DDR0, bank0) is pointed; After progressively increasing for the first time, counter corresponding to bank that repeating query pointed (PMC0, DDR0, bank7) is pointed; And after progressively increasing for the second time, counter corresponding to bank that repeating query pointed (PMC0, DDR1, bank6) is pointed; After progressively increasing again, counter corresponding to bank that repeating query pointed (PMC1, DDR0, bank5) is pointed; ,,; So circulation is gone down.When the repeating query pointer progressively increases by default step-length 7, can guarantee that the repeating query pointer can repeating query arrive the corresponding counter of each bank.In actual applications, this default step-length also can be configured to other numerical value, as long as can guarantee that repeating query arrives the counter that each bank is corresponding during according to this default step-length repeating query, in theory, and so long as not the approximate number of M, can be as default step-length.
Before this writes, the address of the corresponding bank of counter that polling pointer points to is initial writing address last time; After polling pointer progressively increases once, the address of the corresponding bank of counter of the current sensing of polling pointer can be used as temporary transient initial writing address.
Step 203, judge this tentative initial writing address the reading of corresponding counter whether be maximal value, if so, enter step 204 if not, enter step 205;
Because the address sum counter of each bank is corresponding one by one, therefore, counter corresponding to each address is the counter of the corresponding bank in this address, and this meter reading is the current write request cumulative number of this bank.
Concrete, external chip can also set in advance a maximum register, after receiving the instruction of data writing in storage organization at every turn, the current value of the counter that all bank are corresponding is obtained in the external core sector-meeting, maximal value wherein is stored in maximum register, by the numeric ratio in the numerical value of each counter and maximum register simultaneously, whether the current write request cumulative number obtained in the individual count device according to comparative result is the peaked bit sequence in all counters, whether the current write request cumulative number that the value of T numerical value in this bit sequence characterizes in T counter is the maximal value in all counters, wherein, T is greater than 0 integer that is less than or equal to M.Server judges by the bit sequence obtained whether the numerical value of this corresponding counter of tentative initial writing address institute is maximal value, if so, returns to step 202, and continuation is progressively increased the repeating query pointer by default step-length; If should tentative initial writing address the numerical value of corresponding counter be not maximal value, enter step 204.It should be noted that this section details is for realize preferred scheme for hardware, if adopt software mode to realize, can not generate bit sequence and directly compare.
In addition, if all counter values all equate, such as the value of all M counter is 0, after progressively increasing once by the repeating query pointer according to default step-length, directly enter step 204.
Step 204, according to the tentative corresponding M of initial writing address last time
2Individual storage unit is determined MOD(M
2+ N, M) address of individual storage unit is as tentative initial writing address, and returns to step 203;
When the counter values of the repeating query pointed after progressively increasing by default step-length is maximal value, external chip can be according to tentative M corresponding to initial writing address last time
2Individual storage unit is determined MOD(M
2+ N, M) individual storage unit is fixed tentatively initial writing address as another, wherein, and M
2=MOD(M
1+ N, M); Then external chip rejudges whether the current write request cumulative number in another counter of fixing tentatively initial writing address institute's corresponding stored unit is the maximal value in all counters.Although statement is slightly different, those skilled in the art can know, by looping step 203 and step 204, can search out corresponding counter is not peaked tentative initial writing address.
Step 205, should fix tentatively initial writing address as this initial writing address;
When the counter values of the repeating query pointed after progressively increasing by default step-length is not maximal value, using this counter, the tentative initial writing address of corresponding bank is as this initial writing address.
Step 206, from this initial writing address, according to predefined procedure successively to memory controller be sent in current writing address write the write request of a packet in corresponding bank.
Concrete, server can become one or more packet by Data Division to be written, and wherein, the data volume that each packet comprises is not more than the maximum amount of data that the operation of memory controller write-once can write.Such as, the DDR storer is example, and the each write operation of PMC can write the data of 32B in DDR, and server can become Data Division to be written the packet of a plurality of 32B of comprising data, and the data of not enough 32B are processed according to 32B.
For effective bandwidth is maximized, can be from initial writing address, be sent in the write request of asking in turn the data writing bag in each bank to memory controller successively according to the order of repeating query DDR, PMC and bank.Concrete, for the ease of statement, can mean by the form of coordinate putting in order or writing address of each bank, wherein, the x axle means the order of placement of X DDR in storage organization, the y axle means putting in order of Y bank in each DDR; After one of the every transmission of server writes the write request of a packet in current writing address institute's corresponding stored unit, judge in current writing address (x, y), whether x equals X-1; If in current writing address (x, y), x is not equal to X-1, after the x in current writing address being added to 1, continue to be sent in to memory controller the write request that writes next packet in current writing address institute's corresponding stored unit; If in current writing address (x, y), x equals X-1, continue y in the current writing address of judgement (x, y) and whether equal Y-1; If y is not equal to Y-1 in current writing address (x, y), changes the x in current writing address into 0, and, after y adds 1, continue to be sent in to memory controller the write request that writes next packet in current writing address institute's corresponding stored unit; If y equals Y-1 in current writing address (x, y), after all changing the x in current writing address and y into 0, continue to be sent in to memory controller the write request that writes next packet in current writing address institute's corresponding stored unit.
Concrete, with 12 DDR that comprise shown in Fig. 1, the storage organization that every DDR comprises 8 bank is example, refer to Fig. 5 shown in the coordinate schematic diagram of memory cell arrangement order, if selecting coordinate is (0, 0) represented bank(is (PMC0 in Fig. 1, DDR0, bank0) bank pointed to) as this initial writing address, after external chip is sent in the request of the packet that writes a 32B in this bank to memory controller PMC0, it is (0 that external chip continues to be sent in coordinate to memory controller PMC0, 1) bank(is (PMC0 in Fig. 1, DDR1, bank0) write the write request of the packet of next 32B the bank pointed to), until the whole requests of all packets are complete, if the x that server is judged in current bank coordinate (x, y) is 11, such as the coordinate of current bank is (11,0), selects to be sent in to memory controller PMC0 the bank relaying that coordinate is (0,1) and continue the request into next 32B packet, when memory controller is judged current bank coordinate for (11,7), continue to be sent in to memory controller PMC0 the request that writes next 32B packet in the bank of coordinate for (0,0).
In addition, memory controller is in each bank during data writing, need to be refreshed, the operation such as precharge, due to this refreshes, the operation of precharge is used time much larger than memory controller to each bank in time of request data writing, therefore, write fashionablely in data, on counter corresponding to each bank, may accumulate a plurality of write requests are arranged.For the write request accumulative total situation of true each bank of reflection, each external chip is after memory controller is sent in the write request that writes a packet in certain bank, and the counter values that this bank is corresponding adds 1; When packet corresponding to this write request really writes this bank, memory controller can return to a settling signal that writes corresponding to this write request to external chip, after external chip receives that this writes settling signal, is about to counter values corresponding to bank and subtracts 1.
In sum, the initial writing position system of selection of the data that the present embodiment two provides, by fashionable whenever there being data to write, the mode that the repeating query pointer is progressively increased according to default step-length is chosen tentative initial writing position, to fix tentatively counter values that initial writing position is corresponding and the mode of maximal value comparison simultaneously and determine this initial writing address, and according to first repeating query DDR, the PMC order of repeating query bank again asks data writing in each bank, and when the request data writing, counter values is added to 1, really write and fashionable counter values is subtracted to 1 in data, reach each bank write request accumulative total situation of true reflection, even data writing improve the purpose of bandwidth availability ratio in each bank.
It should be noted that, although describe with storage organization shown in Fig. 1 herein always.But, in practical application, storage organization can be not limited to the storage organization shown in Fig. 1, such as, memory controller can be 10; Again such as storer can be 11 QDR storeies; For another example, the bank on every storer can not be 8, but 4, etc.
Embodiment tri-
Refer to Fig. 6, it shows the structural representation of the initial writing address selecting arrangement that the embodiment of the present invention three provides, in the external chip that this initial writing address selecting arrangement can be applied to utilize same bus to be connected with the storage organization shown in Fig. 1.This initial writing address selecting arrangement can comprise: command reception module 620 and address selection module 640;
Whether the first judging unit 644 is the maximal value in all counters for the current write request cumulative number of the counter that judges tentative initial writing address institute's corresponding stored unit that address determining unit 642 is determined;
If address determining unit 642 also, for the maximal value in the not all counter of current write request cumulative number of the counter of the first tentative initial writing address institute's corresponding stored of judging unit 644 judgement unit, will be fixed tentatively initial writing address and be defined as this initial writing address;
Wherein, M is more than or equal to 2 integer; M
1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integer and be not the approximate number of M.
If address determining unit 642 also judges that for the first judging unit 644 the current write request cumulative number of the counter of tentative initial writing address institute's corresponding stored unit is the maximal value in all counters, will fix tentatively the M that initial writing address is corresponding
2Individual storage unit is determined MOD(M
2+ N, M) individual storage unit is fixed tentatively initial writing address as another, wherein, and M
2=MOD(M
1+ N, M).
The first judging unit 644 also judges for continuing whether another current write request cumulative number of fixing tentatively the counter of initial writing address institute's corresponding stored unit that address determining unit 642 is determined is the maximal value in all counters.
This initial writing address selecting arrangement also comprises: split module 662, request sending module 664 and accumulative total module 666, as shown in Figure 8.
Request sending module 664, for this initial writing address of determining from address determining unit 642, is sent in to memory controller the request that writes a packet in current writing address institute's corresponding stored unit successively according to predefined procedure;
Accumulative total module 666 is accumulated for the current write request to counter.Accumulation module 666 can comprise: accumulated unit 666a and the second judging unit 666b, as shown in Figure 9.
The second judging unit 666b is for judging whether to receive the settling signal that writes corresponding to the request that writes a packet in current writing address institute's corresponding stored unit of memory controller feedback;
If accumulated unit 666a also receives and writes settling signal for the second judgment unit judges, the current write request cumulative number that will write in the counter of settling signal institute's corresponding stored unit subtracts one.
Initial writing address selecting arrangement also comprises: sequence generation module 680.Sequence generation module 680 can comprise: acquiring unit 682, computing unit 684 and sequence generating unit 686, as shown in figure 10.
Acquiring unit 682 is for obtaining the current write request cumulative number of individual count device;
Whether the current write request cumulative number that the maximal value in all counters that sequence generating unit 686 is calculated for current write request cumulative number and the computing unit 684 of the individual count device that obtains according to acquiring unit 682 obtains in the individual count device is the peaked bit sequence in all counters, whether the current write request cumulative number that the value of T numerical value in bit sequence characterizes in T counter is the maximal value in all counters, wherein, T is greater than 0 integer that is less than or equal to M;
Accordingly, the first judging unit 644 judges specifically for the bit sequence obtained according to sequence generating unit 686 whether the current write request cumulative number in the counter of fixing tentatively initial writing address institute's corresponding stored unit is the maximal value in all counters.
Storage organization comprises that address number is followed successively by 0 to X-1 X storer, and each storer comprises that address number is followed successively by 0 to Y-1 Y storage unit, and address determining unit 642, specifically for according to initial writing address (x last time
1, y
1) obtain and fix tentatively initial writing address (x
2, y
2), wherein, (x
2-x
1) * Y+(y
2-y
1)=N.
Request sending module 664 comprises: transmitting element 664a and the 3rd judging unit 664b, as shown in figure 11.
Transmitting element 664a starts to be sent in to memory controller the request that writes a packet in current writing address institute's corresponding stored unit from this initial writing address (x, y);
The 3rd judging unit 664b after current writing address institute's corresponding stored unit writes the request of a packet, judges in current writing address (x, y), whether x equals X-1 for one of the every transmission of transmitting element 664a;
If transmitting element 664b also judges current writing address (x for the 3rd judging unit 664b, y) in, x is not equal to X-1, after the x in current writing address being added to 1, continue to be sent in to memory controller the request that writes next packet in current writing address institute's corresponding stored unit;
If the 3rd judging unit 664b continues y in the current writing address of judgement (x, y) and whether equals Y-1 after also for the 3rd judging unit 664b, judging in current writing address (x, y) that x equals X-1;
If transmitting element 664a also judges current writing address (x for the 3rd judging unit 664b, y) in, y is not equal to Y-1, change the x in current writing address into 0, and, after y adds 1, be sent in the request that writes next packet in current writing address institute's corresponding stored unit to memory controller;
If transmitting element 664a also judges current writing address (x for the 3rd judging unit 664b, y) in, y equals Y-1, after all changing the x in current writing address and y into 0, continue to be sent in to memory controller the request that writes next packet in current writing address institute's corresponding stored unit.
In sum, the initial writing address selecting arrangement that the present embodiment three provides, by fashionable whenever there being data to write, according to last time initial writing position choose tentative initial writing position, to fix tentatively counter values that initial writing position is corresponding and the mode of maximal value comparison simultaneously and determine this initial writing address, and ask data writing according to predefined procedure in each bank, and when the request data writing, counter values is added to 1, really write and fashionable counter values is subtracted to 1 in data, reach each bank write request accumulative total situation of true reflection, even data writing improve the purpose of bandwidth availability ratio in each bank.
It should be noted that: the initial writing address selecting arrangement that above-described embodiment provides is when selecting initial writing address, only the division with above-mentioned each functional module is illustrated, in practical application, can above-mentioned functions be distributed and completed by different functional modules as required, the inner structure that is about to device is divided into different functional modules, to complete all or part of function described above.In addition, the initial writing address selecting arrangement that above-described embodiment provides belongs to same design with initial writing address system of selection embodiment, and its specific implementation process refers to embodiment of the method, repeats no more here.
One of ordinary skill in the art will appreciate that all or part of step that realizes above-described embodiment can complete by hardware, also can come the hardware that instruction is relevant to complete by program, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. an initial writing address system of selection, is characterized in that, described method comprises:
The data that reception is sent storage organization write instruction, described storage organization comprises memory controller and M storage unit, each storage unit has address sum counter separately, and each counter is for preserving the current write request cumulative number of corresponding stored unit;
According to the corresponding M of initial writing address last time
1Individual storage unit is determined MOD(M
1+ N, M) address of individual storage unit is as tentative initial writing address;
Judge whether the current write request cumulative number in the counter of described tentative initial writing address institute's corresponding stored unit is the maximal value in all counters;
If not, described tentative initial writing address is defined as to this initial writing address;
Wherein, M is more than or equal to 2 integer; M
1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integer and be not the approximate number of M.
2. initial writing address system of selection according to claim 1, it is characterized in that, whether the current write request cumulative number in the described counter that judges described tentative initial writing address institute's corresponding stored unit is after the maximal value in all counters, also comprises:
If so, according to described tentative M corresponding to initial writing address
2Individual storage unit is determined MOD(M
2+ N, M) individual storage unit is fixed tentatively initial writing address as another, wherein, and M
2=MOD(M
1+ N, M);
Continue judge whether the described current write request cumulative number that another is fixed tentatively in the counter of initial writing address institute's corresponding stored unit is the maximal value in all counters.
3. initial writing address system of selection according to claim 1, is characterized in that, described described tentative initial writing address is defined as to this initial writing address after, also comprise:
Data Division to be written is become to one or more packet, and wherein, the data volume that each packet comprises is not more than the maximum amount of data that described memory controller write-once operation can write;
From described this initial writing address, be sent in to described memory controller the write request that writes a packet in current writing address institute's corresponding stored unit successively according to predefined procedure;
After being sent in current writing address institute's corresponding stored unit and writing the write request of a packet to described memory controller, the current write request cumulative number in the counter of described current writing address institute's corresponding stored unit is added to one;
Judge whether to receive the settling signal that writes corresponding to described write request by described memory controller feedback;
If so, the current write request cumulative number in the counter of said write settling signal institute's corresponding stored unit is subtracted to one.
4. according to the arbitrary described initial writing address system of selection of claims 1 to 3, it is characterized in that, whether the current write request cumulative number in the described counter that judges described tentative initial writing address institute's corresponding stored unit is before the maximal value in all counters, also comprises:
Obtain the current write request cumulative number in the individual count device;
Calculate the maximal value in all counters according to the current write request cumulative number in described individual count device;
According to the current write request cumulative number in the current write request cumulative number in described individual count device and the acquisition of the maximal value in described all counters individual count device, whether be the peaked bit sequence in described all counters, whether the current write request cumulative number that the value of T numerical value in described bit sequence characterizes in T counter is the maximal value in described all counters, wherein, T is greater than 0 integer that is less than or equal to M;
Accordingly, whether the current write request cumulative number in the described counter that judges described tentative initial writing address institute's corresponding stored unit is the maximal value in all counters, specifically comprises:
Judge according to described bit sequence whether the current write request cumulative number in the counter of described tentative initial writing address institute's corresponding stored unit is the maximal value in all counters.
5. according to the arbitrary described initial writing address system of selection of claims 1 to 3, described storage organization comprises that address number is followed successively by 0 to X-1 X storer, each storer comprises that address number is followed successively by 0 to Y-1 Y storage unit, it is characterized in that, described from described this initial writing address, be sent in to memory controller the write request that writes a packet in current writing address institute's corresponding stored unit successively according to predefined procedure, specifically comprise:
From described this initial writing address (x, y) start to be sent in to memory controller the request that writes a packet in current writing address institute's corresponding stored unit, after one of every transmission writes the write request of a packet in current writing address institute's corresponding stored unit, judge in current writing address (x, y), whether x equals X-1;
If in current writing address (x, y), x is not equal to X-1, after the x in current writing address being added to 1, continue to be sent in to described memory controller the write request that writes next packet in current writing address institute's corresponding stored unit;
If in current writing address (x, y), x equals X-1, continue y in the current writing address of judgement (x, y) and whether equal Y-1;
If y is not equal to Y-1 in current writing address (x, y), changes the x in current writing address into 0, and, after y adds 1, continue to be sent in to described memory controller the write request that writes next packet in current writing address institute's corresponding stored unit;
If y equals Y-1 in current writing address (x, y), after all changing the x in current writing address and y into 0, continue to be sent in to described memory controller the write request that writes next packet in current writing address institute's corresponding stored unit.
6. an initial writing address selecting arrangement, is characterized in that, described device comprises: command reception module and address selection module;
Described command reception module, write instruction for receiving the data that storage organization is sent, described storage organization comprises memory controller and M storage unit, each storage unit has address sum counter separately, and each counter is for preserving the current write request cumulative number of corresponding stored unit;
Described address selection module comprises:
The address determining unit, for according to the corresponding M of initial writing address last time
1Individual storage unit is determined MOD(M
1+ N, M) address of individual storage unit is as tentative initial writing address;
Whether the first judging unit is the maximal value in all counters for the current write request cumulative number of the counter that judges tentative initial writing address institute's corresponding stored unit that described address determining unit is determined;
Described address determining unit, if also, for the maximal value in the not all counter of current write request cumulative number of the counter of the described tentative initial writing address institute's corresponding stored of described the first judgment unit judges unit, will describedly fix tentatively initial writing address and be defined as this initial writing address;
Wherein, M is more than or equal to 2 integer; M
1For being greater than 0, be less than or equal to the integer of M; N be 1 or N be positive integer and be not the approximate number of M.
7. initial writing address selecting arrangement according to claim 6, is characterized in that,
Described address determining unit also for, if the current write request cumulative number in the counter of the described tentative initial writing address institute's corresponding stored of described the first judgment unit judges unit is the maximal value in all counters, by described tentative M corresponding to initial writing address
2Individual storage unit is determined MOD(M
2+ N, M) individual storage unit is fixed tentatively initial writing address as another, wherein, and M
2=MOD(M
1+ N, M);
Described the first judging unit, also judge for continuing whether another current write request cumulative number of fixing tentatively the counter of initial writing address institute's corresponding stored unit that described address determining unit is determined is the maximal value in all counters.
8. initial writing address selecting arrangement according to claim 6, is characterized in that, described device also comprises: split module, request sending module and accumulative total module;
Described fractionation module, for Data Division to be written is become to one or more packet, wherein, the data volume that each packet comprises is not more than the maximum amount of data that the operation of memory controller write-once can write;
Request sending module, for from described this initial writing address, be sent in to memory controller the write request that writes a packet in current writing address institute's corresponding stored unit successively according to predefined procedure;
Described accumulative total module comprises:
Accumulated unit, after being sent in current writing address institute's corresponding stored unit and writing the write request of a packet to described memory controller for the described request sending module, the current write request cumulative number in the counter of described current writing address institute's corresponding stored unit is added to one;
The second judging unit, for judging whether to receive the settling signal that writes corresponding to described write request of described memory controller feedback;
Described accumulated unit, if also for described the second judgment unit judges, receive the said write settling signal, subtract one by the current write request cumulative number in the counter of said write settling signal institute's corresponding stored unit.
9. according to the arbitrary described initial writing address selecting arrangement of claim 6 to 8, it is characterized in that, described device also comprises: the sequence generation module; Described sequence generation module comprises:
Acquiring unit, for obtaining the current write request cumulative number of individual count device;
Maximum value calculation unit, calculate the maximal value in all counters for the current write request cumulative number of the individual count device that obtains according to described acquiring unit;
Sequence generating unit, whether the current write request cumulative number that the maximal value in all counters that calculate for current write request cumulative number and the described maximum value calculation unit of the individual count device that obtains according to described acquiring unit obtains in the individual count device is the peaked bit sequence in described all counters, whether the current write request cumulative number that the value of T numerical value in described bit sequence characterizes in T counter is the maximal value in described all counters, wherein, T is greater than 0 integer that is less than or equal to M;
Accordingly, described the first judging unit, judge specifically for the bit sequence obtained according to described sequence generating unit whether the current write request cumulative number in the counter of described tentative initial writing address institute's corresponding stored unit is the maximal value in all counters.
10. according to the arbitrary described initial writing address selecting arrangement of claim 6 to 8, described storage organization comprises that address number is followed successively by 0 to X-1 X storer, each storer comprises that address number is followed successively by 0 to Y-1 Y storage unit, it is characterized in that, the described request sending module comprises:
Transmitting element, start to be sent in to memory controller the write request that writes a packet in current writing address institute's corresponding stored unit from described this initial writing address (x, y);
The 3rd judging unit, after current writing address institute's corresponding stored unit writes the write request of a packet, judge in current writing address (x, y), whether x equals X-1 for one of the every transmission of described transmitting element;
Described transmitting element, if also for the current writing address (x of described the 3rd judgment unit judges, y) in, x is not equal to X-1, after the x in current writing address being added to 1, continues to be sent in to memory controller the write request that writes next packet in current writing address institute's corresponding stored unit;
Described the 3rd judging unit, if, after also for x in described the 3rd current writing address of judgment unit judges (x, y), equaling X-1, continue y in the current writing address of judgement (x, y) and whether equal Y-1;
Described transmitting element, if also for the current writing address (x of described the 3rd judgment unit judges, y) in, y is not equal to Y-1, change the x in current writing address into 0, and, after y adds 1, be sent in the write request that writes next packet in current writing address institute's corresponding stored unit to memory controller;
Described transmitting element, if also for the current writing address (x of described the 3rd judgment unit judges, y) in, y equals Y-1, after all changing the x in current writing address and y into 0, continue to be sent in to memory controller the write request that writes next packet in current writing address institute's corresponding stored unit.
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