CN103412284B - Matrix transposition method in SAR imaging system based on DSP chip - Google Patents
Matrix transposition method in SAR imaging system based on DSP chip Download PDFInfo
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Abstract
The invention discloses a matrix transposition method in an SAR imaging system based on a DSP chip. The problems that radar real-time imaging storage space is small, and the requirement for real-time performance is high are mainly solved. The implementation process of the matrix transposition method comprises the steps that (1) an original matrix is transversely divided; (2) a rough classification matrix is longitudinally divided; (3) small unit matrixes are obtained; (4) storage space is created; (5) the small unit matrixes are classified; (6) transposition is carried out on the small diagonal unit matrixes; (7) transposition is carried out on the small non-diagonal unit matrixes; (8) the transpositioned matrixes are combined. The matrix transposition method aims at the transposition operation of a large-scale radar return original data matrix, the large matrix is roughly and finely divided into two classes of small unit matrixes, different transposition methods are applied to processing the matrixes, a large amount of storage space is saved, and operation efficiency is improved. The matrix transposition method is simple, easy to implement and suitable for the transposition operation of various radar real-time imaging systems and other systems.
Description
Technical field
The invention belongs to communication technical field, further relate to the one in Radar Digital Signal Processing field based on matrix transpose method in synthetic-aperture radar (the Synthetize Aperture Radar SAR) imaging system of digital signal processor (Digital Signal Processor DSP) chip.The present invention can be used for carrying out quick transposition to extensive radar return data, to solve the deficiency of synthetic aperture radar image-forming requirement of real-time and storage resources.
Background technology
Radar return data matrix transposition data volume is large, requirement of real-time is high, but it is in short supply to process storage space under actual conditions, so the quick transposition method how realizing extensive matrix in limited storage space becomes problem demanding prompt solution, this also lays a good foundation for realizing real-time SAR imaging
A kind of method of matrix transpose is disclosed in the patent " a kind of method of matrix transpose " (publication number: CN102253925A, application number: 201010174342.7, the applying date: on 05 18th, 2010) of Jiangsu Actichip Technology Co., Ltd.'s application.First the method will treat that the matrix trace inequality of transposition is submatrix, then at every turn from a submatrix in order take out data line and the data of taking-up put into register one by one until all row data discharge, then the data reading register in order are one by one put in the correspondence position of matrix after transposition.The deficiency that this patented claim exists is, because register space is too little, and utilizes the extensive matrix transpose of the method to need one piece of very large storage space, is not suitable for extensive matrix transpose computing in this way.
Patent " matrix transpose method of synthetic aperture radar image-forming system and the transposition device " (publication number: CN103048644A of University of Electronic Science and Technology's application, application number: 201210553860.9, applying date: on Dec 19th, 2012) in disclose a kind of matrix transpose method and transposition device of synthetic aperture radar image-forming system.The method first Technologies Against Synthetic Aperture Radar echo matrix data input, then splits this matrix and the generation of read/write address, then by echo matrix data write SDRAM and echo matrix data read in the transposition exporting buffer unit and echo matrix data and export.The deficiency that this patented claim exists is, the data of SDRAM read in the wide constraint being all subject to bus with output speed, and matrix transpose device needs in SDRAM for intermediate variable opens up large storage space, so each data-moving meeting at substantial time, this cannot meet the real-time of matrix transpose.
Summary of the invention
The object of the invention is to the deficiency for above-mentioned prior art, a kind of quick transposition method for radar return data matrix extensive in radar real time imagery is provided, to realize completing real time radar imaging processing under storage space condition in short supply.
Realizing technical thought of the present invention is: do not open up large storage space to deposit matrix transpose intermediate variable, by extensive radar return data original matrix rough segmentation block, again the minor matrix of piecemeal is carefully divided, obtain the little square formation of two class unit, and with diverse ways, transpose process is carried out to the little square formation of this two class, finally the matrix after transposition is stored on corresponding DDR3 address.
The concrete steps realizing the object of the invention are as follows:
(1) laterally original matrix is divided:
Longitudinal continuous print radar return data original matrix in dsp chip external memory space will be stored in, laterally be divided into M rough segmentation matrix according to the number of dsp chip process core.
(2) longitudinally rough segmentation matrix is divided:
Each rough segmentation matrix is longitudinally divided into N number of preliminary square formation, the M after slightly being divided × N number of preliminary square formation.
(3) the little square formation of unit is obtained:
Each preliminary square formation is carefully divided into the little square formation of the equal-sized unit of parking space that multiple size and DSP internal storage space are opened up.
(4) storage space is opened up:
Open up four pieces of internal storage space addresses identical with unit little square formation size.
(5) to the little square formation classification of unit:
By the little square formation of unit be positioned in each preliminary square formation on diagonal line, be divided into the little square formation classification of diagonal element, by the little square formation of unit be positioned on off-diagonal, be divided into the little square formation classification of non-diagonal unit.
(6) the little square formation transpose process of diagonal element:
6a) from diagonal element little square formation classification, get a little square formation of diagonal element;
6b) by the direct memory instruction of dsp chip inside, by little for got diagonal element square formation, be transported to from external memory space address step (4) open up in internal storage space address one piece;
6c) transpose process is carried out to the little square formation of the diagonal element taken in internal storage space address, be stored in another block internal storage space address of having opened up after transposition;
6d) by the direct memory instruction of dsp chip inside, by little for the diagonal element after transposition square formation, be transported in the former external memory space address of depositing of the little square formation of this diagonal element from internal storage space address, the internal storage space address of release busy;
6e) judge whether the little square formation of diagonal element takes; If do not take, then perform step 6a); If take, perform step (7).
(7) the little square formation transpose process of non-diagonal unit:
7a) from the little square formation classification of non-diagonal unit, get two little square formations of non-diagonal unit about diagonal line symmetry;
7b) by the direct memory instruction of dsp chip inside, by got two little square formations of non-diagonal unit, be transported in two pieces of internal storage space addresses that step (4) opens up from external memory space address;
7c) respectively transpose process is carried out to the little square formation of non-diagonal unit taken in two pieces of internal storage space addresses, be stored in another two pieces of internal storage space addresses of having opened up after transposition;
7d) by the direct memory instruction of dsp chip inside, by the little square formation of non-diagonal unit of two after transposition, intersect and be transported in former external memory space address of depositing, the internal storage space address of release busy;
7e) judge whether the little square formation of non-diagonal unit takes; If do not take, perform step 7a); If take, then perform step (8).
(8) transposed matrix is combined:
8a) extract longitudinal data row of each preliminary square formation in the rough segmentation matrix be stored in dsp chip external memory space address successively;
8b) extracted longitudinal data is arranged, arrange according to the order of preliminary square formation, longitudinal data row of composition radar return data transposition matrix;
8c) judge whether the longitudinal data row of preliminary square formation take, if do not take, then perform step 8a) extract the next column of preliminary square formation; If take, obtain the longitudinal data block of radar return data transposition matrix, perform step 8d);
8d) by the longitudinal data block of radar return data transposition matrix, according to the order arrangement of dsp chip M process core, obtain the transposed matrix of radar return data.
Compared with prior art, the present invention has the following advantages:
First, the present invention divides original extensive matrix thickness respectively, avoid in transpose procedure the requirement of opening up very large storage space, overcome thus in prior art because register space is too little, be not suitable for the deficiency of extensive matrix transpose computing, make the present invention have the advantage of the larger scope of application.
Second, the present invention is by being divided into the little square formation of two class unit to original matrix thickness, again different transpose operation is carried out to little square formation after division, overcome in prior art and need, for intermediate variable opens up the shortcoming of large storage space, to make the present invention have the advantage of saving a large amount of storage space.
3rd, the present invention divides process to radar return data original matrix, overcome prior art process in real time in the shortcoming of data-moving at substantial time, make the present invention have the fast advantage of processing speed, improve the real-time of radar imagery further.
Accompanying drawing explanation
Fig. 1 is process flow diagram of the present invention;
Fig. 2 is the schematic diagram that radar return raw data matrix thickness of the present invention divides;
Fig. 3 is of the present invention to unit little square formation classification schematic diagram;
Fig. 4 is diagonal element of the present invention little square formation transpose process schematic diagram;
Fig. 5 is non-diagonal unit of the present invention little square formation transpose process schematic diagram;
Fig. 6 is combination transposed matrix schematic diagram of the present invention.
Specific implementation method
Below in conjunction with accompanying drawing, the present invention is described further.
With reference to accompanying drawing 1, concrete steps of the present invention are as follows:
Step 1, laterally divides original matrix.
Longitudinal continuous print radar return data original matrix in dsp chip external memory space will be stored in, laterally be divided into M rough segmentation matrix according to the number of dsp chip process core.
Radar return raw data matrix in example of the present invention is stored in the external memory space of dsp chip TMS320C6678, longitudinally continuously, longitudinally counts as nrn, laterally counts as nan.There is according to dsp chip TMS320C6678 the characteristic of eight parallel cores, be laterally divided into eight rough segmentation matrixes to give eight cores echo raw data.
Step 2, longitudinally divides rough segmentation matrix.
Because rough segmentation matrix is not square formation, each rough segmentation matrix is longitudinally divided into N number of preliminary square formation again,
wherein, N is the number of preliminary square formation, and nan is that the transverse direction of raw radar data matrix is counted, and nrn is that the longitudinal direction of raw radar data matrix is counted, and M is the number of rough segmentation matrix, also equals the number of dsp chip process core.
Because the number of dsp chip process core of the present invention is 8, so M=8 in embodiments of the invention.
With reference to Fig. 2, can find out clearly, radar return data original matrix is divided into eight rough segmentation matrixes by longitudinal by the present invention, is more laterally divided into N number of preliminary square formation.Fig. 2 is the schematic diagram that radar return raw data matrix thickness divides, in Fig. 2, the first half refers to that original matrix is divided into rough segmentation matrix 1, rough segmentation matrix 2, rough segmentation matrix 3, rough segmentation matrix 4, rough segmentation matrix 5, rough segmentation matrix 6, rough segmentation matrix 7, rough segmentation matrix 8, totally 8 rough segmentation matrixes.The latter half of Fig. 2 is that each rough segmentation matrix is longitudinally divided into a1, a2......, aN, N number of preliminary square formation altogether.By the horizontal and vertical division to original matrix, original matrix is divided into 8 × N number of preliminary square formation.
Step 3, obtains the little square formation of unit.
By laterally dividing and longitudinally drawing in two steps, radar return raw data matrix has been divided into M × N number of preliminary square formation.Each preliminary square formation is carefully divided into the little square formation of the equal-sized unit of parking space that multiple size and DSP internal storage space are opened up.For 16384 × 8192 floating type plural number original echo matrixes in example of the present invention, the size of each preliminary square formation is 2048 × 2048, more preliminary square formation is subdivided into the little square formation of unit of 128 × 128 sizes, and each preliminary square formation has 16 × 16 little square formations of unit.
According to the size of residual memory space in the internal storage space L2 of 512KB size, in the embodiment of the present invention, the little square formation size of unit is decided to be 128 × 128.In transpose operation of the present invention, only need the array of additionally opening up four 128 × 128 floating type complex magnitude, wherein put the little square formation of unit of original 128 × 128 sizes of taking out for two, deposit the little square formation of unit after transposition for another two.
Step 4, opens up storage space.
In internal storage space L2, open up four pieces of spaces identical with unit little square formation size, wherein deposit the little square formation of the unit taken out from DDR3 for two pieces, deposit the little square formation of unit after transposition for another two pieces.
In the embodiment of the present invention, be the space of opening up 4 128 × 128 floating type complex magnitude in the L2 of 512KB in the total size in space.
Step 5, to the little square formation classification of unit.
The little square formation of unit on diagonal line will be positioned in preliminary square formation, be divided into the little square formation classification of diagonal element, by the little square formation of unit be positioned on off-diagonal, be divided into the little square formation classification of non-diagonal unit.Such process is not opening up the array in external memory space under the condition storing the matrix of pilot process, and to the little square formation transposition of each unit, and the mode of corresponding stored realizes whole original echo transpose of a matrix.
With reference to Fig. 3, can find out clearly, little for unit square formation is divided into the little square formation of diagonal element and the little square formation of non-diagonal unit by the present invention.Fig. 3 is that in Fig. 3, little for the unit be positioned on the diagonal line of preliminary matrix square formation is divided into the little square formation of diagonal element, the little square formation of the unit on remaining off-diagonal is divided into the little square formation of non-diagonal unit to unit little square formation classification schematic diagram.By this classification, the little square formation of different classes of unit can do different transpose operation process.
Step 6, the little square formation transpose process of diagonal element.
6a) from the diagonal element of the DDR3 being stored in external memory space little square formation classification, get a little square formation of diagonal element;
6b) by the direct memory instruction of dsp chip inside, by little for got diagonal element square formation, be transported to from external memory space address and open up in internal storage space address in internal storage space L2;
In DSP program segment, 6c) call TI built-in function complex float type matrix transpose function DSPF_sp_mat_trans_cplx transpose process is carried out to the little square formation of diagonal element, be stored in after transposition in another block internal storage space address of having opened up.
The concrete steps of the little square formation transposition of diagonal element are:
The first step, appoints the element a of fetch bit in the little square formation of unit on capable n-th column position of m.
Second step, takes out the element b be arranged on unit little square formation n-th line m column position.
3rd step, exchanges the memory location of element a and element b in the little square formation of unit, is put in by element a in the little square formation of unit on n-th line m column position, to be put in by element b in the little square formation of unit on capable n-th column position of m.
4th step, in the little square formation of judging unit, whether the position of all elements exchanges complete, if do not exchanged, then performs the first step; Otherwise, terminate transpose process.
6d) by the direct memory instruction of dsp chip inside, by little for the diagonal element after transposition square formation, be transported in the former external memory space address D DR3 deposited of the little square formation of this diagonal element from internal storage space address, the internal storage space address of release busy;
6e) judge whether the little square formation of diagonal element takes; If do not take, then perform step 6a); If take, perform step (7).
With reference to Fig. 4, transpose operation is carried out to a little square formation of diagonal element.Fig. 4 is diagonal element little square formation transpose process schematic diagram, by the little square formation of diagonal unit be positioned in figure on preliminary diagonal of a matrix, moves in L2 address, and carry out transpose operation from the address of DDR in L2, then deposit on original DDR address.By such process, the little square formation of all diagonal element completes transpose operation.
Step 7, the little square formation transpose process of non-diagonal unit.
7a) from the little square formation classification of non-diagonal unit, utilize in the original echo matrix of DMA DDR3 from external memory space address and get two little square formations of non-diagonal unit about diagonal line symmetry, the little square formation that the little square formation of the n-th row as capable in m and n-th line m arrange;
7b) by the direct memory instruction of dsp chip inside, by got two little square formations of non-diagonal unit, be transported in two pieces of internal storage space addresses of opening up in L2;
In DSP program segment, 7c) call complex float type matrix transpose function DSPF_sp_mat_trans_cplx in TI storehouse respectively transposition is carried out to the little square formation of non-diagonal unit that these two store in array, be stored in after transposition in another two pieces of internal storage space addresses of having opened up.
The concrete steps of the little square formation transposition of each non-diagonal unit are:
The first step, appoints the element a taking out and be arranged on capable n-th column position of unit little square formation m.
Second step, takes out the element b be arranged on unit little square formation n-th line m column position.
3rd step, exchanges the memory location of element a and element b in the little square formation of unit, is put in by element a in the little square formation of unit on n-th line m column position, to be put in by element b in the little square formation of unit on capable n-th column position of m.
4th step, in the little square formation of judging unit, whether the position of all elements exchanges complete, if do not exchanged, then performs the first step; Otherwise, terminate transpose process.
7d) by the direct memory instruction of dsp chip inside, by the little square formation of non-diagonal unit of two after transposition, intersect and be transported in former external memory space address of depositing, the internal storage space address of release busy;
7e) judge whether the little square formation of non-diagonal unit takes; If do not take, perform step 7a); If take, the little square formation transposition of non-diagonal unit completes.
With reference to Fig. 5, transpose operation is carried out to a little square formation of non-diagonal unit.Fig. 5 is non-diagonal element little square formation transpose process schematic diagram, the little square formation of Liang Ge non-diagonal unit being arranged in preliminary diagonal of a matrix symmetry in figure is moved to L2 address from the address of DDR, and carry out transpose operation respectively in L2, then intersection is deposited on the DDR address of the other side.All little square formations of non-diagonal unit just complete transpose operation by such process.
Step 8, combination transposed matrix.
In the embodiment of the present invention, the little square formation of unit is all carried out after transpose process terminates, and the preliminary square formation of 2048 × 2048 sizes just obtains transposition, and the longitudinal direction of radar return raw data matrix becomes horizontal continuous print radar return transposed matrix continuously.Longitudinal data row to obtain radar return transposed matrix need data splitting.
The specific implementation of combination transposed matrix is according to following steps:
8a) extract longitudinal data row of each preliminary square formation in the rough segmentation matrix be stored in dsp chip external memory space address successively;
8b) extracted longitudinal data is arranged, arrange according to the order of preliminary square formation, longitudinal data row of composition radar return data transposition matrix;
8c) judge whether the longitudinal data row of preliminary square formation take, if do not take, then perform step 8a) extract the next column of preliminary square formation; If take, obtain the longitudinal data block of radar return data transposition matrix, perform step 8d);
8d) by the longitudinal data block of radar return data transposition matrix, according to the order arrangement of dsp chip M process core, obtain the transposed matrix of radar return data.
With reference to Fig. 6, the preliminary square formation after transposition is combined into radar return data transposition matrix.Fig. 6 is combination transposed matrix schematic diagram, the continuation column data of four preliminary square formations are become after being positioned at a Data in Azimuth Direction transposition of rough segmentation matrix in figure, so extract a Data in Azimuth Direction of radar return data transposition matrix, need the column vector of getting preliminary square formation respectively, and according to these column vectors of sequential combination of DSP process core, namely obtain the Data in Azimuth Direction of distance to continuous print echo matrix.
So far, complete based on matrix transpose method in the SAR imaging system of dsp chip.
The present invention is based on SAR Real-time processing, and the basic step briefly introducing SAR imaging is: the first step solves the inertial navigation parameter of echo data matrix, and adjust the distance to continuous print echo data distance pulse pressure, non-space-variant and space-variant compensate; Echo data matrix transpose to orientation to continuously, is transformed to distance time domain-orientation Doppler domain by second step; 3rd step by echo data matrix transpose be distance to continuously, carry out range migration correction; 4th step is by echo data matrix transpose to orientation to continuously, and by data transformation to distance time domain-orientation time domain, estimating Doppler frequency modulation rate also carries out orientation to pulse pressure.Whole SAR Real Time Image System needs cubic matrix transpose operation, if can improve matrix transpose arithmetic speed, will improve the efficiency of real time imagery greatly.
Contrast the present invention below by test and take memory space requirements with traditional transposition method and operation time compares, further illustrate effect of the present invention.
Test 1: the present invention and traditional transposition method take storage space and contrast.
This test is the development board based on TMS320C6678, and radar return data original matrix distance is to 16384 × 8192 floating type complex matrixs of continuous (longitudinally continuously), and distance is 16384 to counting, and orientation is 8192 to counting.
The storage size of TMS320C6678 development board is analyzed.TMS320C6678 is a digital signal processor with high-performance and abundant Resources on Chip, and have eight process cores, dominant frequency is up to 1.0GHz.
With reference to table 1, the storer of TMS320C6678 comprises the one-level program storage (L1P) of a 32KB, the level data memory (L1D) of a 32KB, the second-level storage (L2) of a 512KB, the multinuclear of 4096KB share storage space (MSMC), the external memory space (DDR3) of external 2GB.
The storage size of table 1:TMS320C6678 development board
| The size (byte) of storage space | |
| External memory area DDR3 | 2G |
| One-level program storage area L1P | 32K |
| Level one data memory block L1D | 32K |
| Secondary storage area L2 | 512K |
| Multinuclear shares storage space MSMC | 4M |
Radar return data original matrix needs 1GB storage space, and therefore the DDR3 of 2GB just deposits ping-pong two groups of echo data matrixes.According to the transposition function in TI storehouse, transposition is carried out to whole original matrix, need in DDR3, open up the array that a size is 16384 × 8192 floating type plural numbers, this wastes external memory space greatly, and also without unnecessary storage space in the DDR3 of this development board.
It is the array of opening up 4 128 × 128 floating type complex magnitude in the L2 of 512KB that the transposition method that have employed in the present invention only needs in total size, wherein deposits the little square formation of the unit taken out from DDR3 for two, deposits the little square formation of unit after transposition for another two.
Test 2: the present invention and the time-consuming contrast of traditional transposition method
This test is the development board based on TMS320C6678, and radar return data original matrix distance is to continuous print 16384 × 8192 floating type complex matrix, and distance is 16384 to counting, and orientation is 8192 to counting.
EDMA interval is relatively utilized to get orientation to a column data, call in TI storehouse and get orientation after matrix transpose function transposition more continuously to a column data, get orientation after utilizing transposition method transposition of the present invention again and get discontinuous Data in Azimuth Direction row in 16384 × 8192 radar return data original matrix to these three kinds of distinct methods of a column data, also comparison operation is consuming time for statistics.
With reference to table 2, utilizing EDMA interval to get orientation, to add orientation to the Fourier transform time used to the matrix transpose of this method of a column data be the 2.0656e+009 clock period, call in TI storehouse and get orientation after matrix transpose function transposition more continuously to add orientation to the Fourier transform time used to the matrix transpose of this method of a column data be the 9.5852e+009 clock period, getting orientation after utilizing transposition method transposition of the present invention again, to add orientation to the Fourier transform time used to the matrix transpose of this method of a column data be the 1.0311e+009 clock period.
As can be known from Table 2, call in TI storehouse and get this method of orientation to a column data more continuously after complex matrix transposition function transposition, consuming time the longest, be secondly utilize EDMA interval to get the method for orientation to a column data, what the used time economized most is get orientation to a column data after utilizing transposition method of the present invention.
Table 2: the used time of getting non-continuous data row with three kinds of diverse ways compares
One 8192 complex vector located FFT need 228 after tested, 220 clock period, it is consuming time known that time described in table 2 deducts FFT, utilize transposition method of the present invention can get the method saving nearly ten times times of orientation to a column data after complex matrix transposition function transposition again than calling in TI storehouse, Billy gets orientation with EDMA interval and saves nearly half the time to the method for a column data.
Claims (2)
1., based on a matrix transpose method in the SAR imaging system of dsp chip, comprise the steps:
(1) laterally original matrix is divided:
Longitudinal continuous print radar return data original matrix in dsp chip external memory space will be stored in, laterally be divided into M rough segmentation matrix according to the number of dsp chip process core;
(2) longitudinally rough segmentation matrix is divided:
Each rough segmentation matrix is longitudinally divided into N number of preliminary square formation, the M after slightly being divided × N number of preliminary square formation;
In N number of preliminary square formation, N must meet following formula:
Wherein, N is the number of preliminary square formation, and nan is that the transverse direction of radar return data original matrix is counted, and M is the number of rough segmentation matrix, and nrn is that the longitudinal direction of radar return data original matrix is counted;
(3) the little square formation of unit is obtained:
Each preliminary square formation is carefully divided into the little square formation of the equal-sized unit of parking space that multiple size and DSP internal storage space are opened up;
(4) storage space is opened up:
Open up four pieces of internal storage space addresses identical with unit little square formation size;
(5) to the little square formation classification of unit:
By the little square formation of unit be positioned in each preliminary square formation on diagonal line, be divided into the little square formation classification of diagonal element, by the little square formation of unit be positioned on off-diagonal, be divided into the little square formation classification of non-diagonal unit;
(6) the little square formation transpose process of diagonal element:
6a) from diagonal element little square formation classification, get a little square formation of diagonal element;
6b) by the direct memory instruction of dsp chip inside, by little for got diagonal element square formation, be transported to from external memory space address step (4) open up in internal storage space address one piece;
6c) transpose process is carried out to the little square formation of the diagonal element taken in internal storage space address, be stored in another block internal storage space address of having opened up after transposition;
6d) by the direct memory instruction of dsp chip inside, by little for the diagonal element after transposition square formation, be transported in the former external memory space address of depositing of the little square formation of this diagonal element from internal storage space address, the internal storage space address of release busy;
6e) judge whether the little square formation of diagonal element takes; If do not take, then perform step 6a); If take, perform step (7);
(7) the little square formation transpose process of non-diagonal unit:
7a) from the little square formation classification of non-diagonal unit, get two little square formations of non-diagonal unit about diagonal line symmetry;
7b) by the direct memory instruction of dsp chip inside, by got two little square formations of non-diagonal unit, be transported in two pieces of internal storage space addresses that step (4) opens up from external memory space address;
7c) respectively transpose process is carried out to the little square formation of non-diagonal unit taken in two pieces of internal storage space addresses, be stored in another two pieces of internal storage space addresses of having opened up after transposition;
7d) by the direct memory instruction of dsp chip inside, by the little square formation of non-diagonal unit of two after transposition, intersect and be transported in former external memory space address of depositing, the internal storage space address of release busy;
7e) judge whether the little square formation of non-diagonal unit takes; If do not take, perform step 7a); If take, then perform step (8);
(8) transposed matrix is combined:
8a) extract the longitudinal data row being stored in each preliminary square formation in the rough segmentation matrix of dsp chip external memory space address successively;
8b) extracted longitudinal data is arranged, arrange according to the order of preliminary square formation, longitudinal data row of composition radar return data transposition matrix;
8c) judge whether the longitudinal data row of preliminary square formation take, if do not take, then perform step 8a) extract the next column of preliminary square formation; If take, obtain the longitudinal data block of radar return data transposition matrix, perform step 8d);
8d) by the longitudinal data block of radar return data transposition matrix, according to the order arrangement of dsp chip M process core, obtain the transposed matrix of radar return data.
2. according to described in claim 1 based on matrix transpose method in the SAR imaging system of dsp chip, it is characterized in that, step 6c), step 7c) concrete steps of described transpose process are as follows:
The first step, appoints the element a taking out and be arranged on capable n-th column position of unit little square formation m;
Second step, takes out the element b be arranged on unit little square formation n-th line m column position;
3rd step, exchanges the memory location of element a and element b in the little square formation of unit, is put in by element a in the little square formation of unit on n-th line m column position, to be put in by element b in the little square formation of unit on capable n-th column position of m;
4th step, in the little square formation of judging unit, whether the position of all elements exchanges complete, if do not exchanged, then performs the first step; Otherwise, terminate transpose process.
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| CN103761709B (en) * | 2014-01-07 | 2016-08-03 | 西安电子科技大学 | Parallel REAL TIME SAR IMAGES based on multi-DSP fall speckle denoising method |
| CN105527609A (en) * | 2015-12-02 | 2016-04-27 | 西安电子工程研究所 | PD radar system matrix transposition method based on DSP |
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