CN103378046A - Chip assembling structure and chip assembling method - Google Patents
Chip assembling structure and chip assembling method Download PDFInfo
- Publication number
- CN103378046A CN103378046A CN2012101256105A CN201210125610A CN103378046A CN 103378046 A CN103378046 A CN 103378046A CN 2012101256105 A CN2012101256105 A CN 2012101256105A CN 201210125610 A CN201210125610 A CN 201210125610A CN 103378046 A CN103378046 A CN 103378046A
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- weld pad
- chip
- circuit board
- soldered
- bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4941—Connecting portions the connecting portions being stacked
- H01L2224/49425—Wedge bonds
- H01L2224/49426—Wedge bonds on the semiconductor or solid-state body
Abstract
A chip assembling structure comprises a circuit board and a chip located on the circuit board. A plurality of first welding pads are formed on the circuit board, and a plurality of second welding pads corresponding to the first welding pads respectively are formed on the chip. Two first welding balls are formed in each first welding pad. Each second welding pad is connected with each corresponding first welding pad through two bonding wires. One ends of the two bonding wires are connected with every two welding balls respectively, and the other ends of the two bonding wires are connected with each second welding pad through a hot-pressure bonding method. The invention further relates to a chip assembling method.
Description
Technical field
The present invention relates to a kind of chipset assembling structure and chip assemble method.
Background technology
Be the function that realizes being scheduled to, generally comprise circuit board and a plurality of chip that is arranged on the described circuit board in the electronic product, between the described chip and described chip be electrically connected by the routing mode with described circuit board.
When having high-frequency signals to pass through, the wire bond structure between described chip and substrate can produce than the forceful electric power sense, and this inductance can have a strong impact on circuit characteristic, so that circuit impedance is difficult to coupling, simultaneously so that signal loss increase.
In addition, along with the development of technology, the size of chip exceedes little, and correspondingly, the pin size on the chip also exceedes little, and the reducing of pin size must cause the routing difficulty to increase.
Summary of the invention
In view of this, be necessary to provide a kind of and can reduce inductance and easy chipset assembling structure and chip assemble method.
A kind of chipset assembling structure comprises a circuit board and a chip that is positioned on the described circuit board.Be formed with a plurality of the first weld pads on the described circuit board, form a plurality of the second weld pads that correspond respectively to described the first weld pad on the described chip.Be formed with two the first soldered balls on described each first weld pad.Each described second weld pad is continuous with the first corresponding weld pad by two bonding wires.One end of described two bonding wires links to each other with described two the first soldered balls respectively, and the other end links to each other by the thermocompression bonding mode with described the second weld pad.
A kind of chip assemble method, it comprises the steps:
A circuit board is provided;
A chip is provided;
Chip to be assembled is fixedly installed on described circuit board surface, is formed with a plurality of the first weld pads on the described circuit board, be formed with the second corresponding weld pad of a plurality of and described the first weld pad on the described chip;
On each described first weld pad, form two the second soldered balls;
Two bonding wires are provided, an end of described two bonding wires is welded mutually with described the second soldered ball respectively;
With described two bonding wires by described the first soldered ball tractive to described the second weld pad, the other end of described bonding wire is soldered on described the second weld pad in the thermocompression bonding mode.
Compared with prior art, described chipset assembling structure and chip assemble method, owing to adopt two bonding wires to connect the second corresponding weld pad on the first weld pad on the described circuit board and the described chip, and consist of relation in parallel between described two bonding wires, therefore can so that described the first weld pad and the second weld pad between the connection line inductance reduce, improve circuit characteristic.In addition, described bonding wire is soldered on described the second weld pad by the thermocompression bonding mode, can will hang down the difficulty of routing, can increase the cross-sectional area of described the second weld pad and described bonding wire coupling part simultaneously, further reduces inductance.
Description of drawings
Fig. 1 is the schematic diagram of the chipset assembling structure of the embodiment of the invention.
Fig. 2 is the flow chart of the chip assemble method of the embodiment of the invention.
The main element symbol description
| The chipset assembling structure | 100 |
| Circuit board | 10 |
| Loading end | 11 |
| The first weld pad | 12 |
| The first soldered ball | 13 |
| Chip | 20 |
| The second weld pad | 21 |
| Bonding wire | 30 |
| Initiating terminal | 31 |
| Clearing end | 32 |
| Wedge-shaped part | 33 |
Following embodiment further specifies the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with accompanying drawing the present invention being done one specifically introduces.
See also Fig. 1, the chipset assembling structure 100 of the embodiment of the invention comprises a circuit board 10, a bonding wire 30 that is arranged at the chip 20 on the described circuit board 10 and connects described circuit board 10 and described chip 20.
Described circuit board 10 comprises a loading end 11 that is used for carrying described chip 20.Be provided with a plurality of the first weld pads 12 on the described loading end 11, described the first weld pad 12 links to each other with circuit terminal (not shown) on the described circuit board 10, is formed with two the first soldered balls 13 on described each first weld pad 12.In the ability mode, distance is identical between described two the first soldered balls 13 and the described chip 20, certainly, between described the first soldered ball 13 and the described chip 20 apart from also can be different.
Described chip 20 is fixedly installed on the loading end 11 of described circuit board 10.Described chip 20 surfaces are provided with a plurality of the second weld pads 21, and described the second weld pad 21 is corresponding with the first weld pad 12 on the described circuit board 10.
In the present embodiment, the quantity of described the first weld pad 12 and described the second weld pad 21 is two, is appreciated that described the first weld pad 12 can change according to different demands to some extent from the quantity of described the second weld pad 21.
Described bonding wire 30 is used for will described the first weld pad 12 and corresponding the second weld pad 21 electrical connections.Linked to each other by two bonding wires 30 between every a pair of the first weld pad 12 and the second weld pad 21.Described each bar bonding wire 30 comprises an initiating terminal 31 that links to each other with described the first soldered ball 13, a clearing end 32 that links to each other with described the second weld pad 21.Described initiating terminal 31 is the end that described bonding wire 30 is at first fixed when welding, and described clearing end 32 is the end that described bonding wire 30 is fixed when welding at last.Described clearing end 32 adopts thermal compression welding mode and described the second weld pad 21, and the welding position of two bonding wires 30 overlaps on described each second weld pad 21.Described two bonding wires 30 form a wedge-shaped part 33 in place, described the second weld pad 21 welding positions.
Described the first soldered ball 13, described the second soldered ball 22 and described bonding wire 30 are made of the metal material of high conductivity, and in the present embodiment, described the first soldered ball 13, described the second soldered ball 22 and described bonding wire 30 consist of by gold (Au).
In the present embodiment, the quantity of the described chip 20 on the described circuit board 10 is one.The quantity that should be pointed out that described chip 20 also can be for a plurality of, and the thickness of a plurality of chip 20 can be different.
See also Fig. 2, the chip assemble method of the embodiment of the invention comprises the steps:
A circuit board is provided;
A chip is provided;
Chip to be assembled is fixedly installed on described circuit board surface, is formed with a plurality of the first weld pads on the described circuit board, be formed with the second corresponding weld pad of a plurality of and described the first weld pad on the described chip;
On described first weld pad, form two the second soldered balls;
Two bonding wires are provided, an end of described two bonding wires is welded mutually with described the second soldered ball respectively;
With described two bonding wires by described the first soldered ball tractive to described the second weld pad, the other end of described bonding wire is soldered on described the second weld pad in the thermocompression bonding mode.
In the above-mentioned steps, the other end of described bonding wire mutually overlaps and is soldered on described the second weld pad.
The above only describes the method for attachment of one of them second weld pad of described chip and corresponding first weld pad of described circuit board in detail, be appreciated that, other second weld pad can adopt same procedure to realize connecting with corresponding the first weld pad, gives unnecessary details no longer one by one herein.
Described chipset assembling structure and chip assemble method, owing to adopt two bonding wires to connect the second corresponding weld pad on the first weld pad on the described circuit board and the described chip, and consist of relation in parallel between described two bonding wires, therefore can so that described the first weld pad and the second weld pad between the connection line inductance reduce, improve circuit characteristic.In addition, described bonding wire is soldered on described the second weld pad by the thermocompression bonding mode, can will hang down the difficulty of routing, can increase the cross-sectional area of described the second weld pad and described bonding wire coupling part simultaneously, further reduces inductance.
In addition, those skilled in the art also can do other variation in spirit of the present invention, and certainly, the variation that these are done according to spirit of the present invention all should be included within the present invention's scope required for protection.
Claims (10)
1. chipset assembling structure, the chip that comprises that a circuit board and one are positioned on the described circuit board and be electrical connected with described circuit board, be formed with a plurality of the first weld pads on the described circuit board, form a plurality of the second weld pads that correspond respectively to described the first weld pad on the described chip, it is characterized in that: be formed with two the first soldered balls on described each first weld pad, each described second weld pad is continuous with the first corresponding weld pad by two bonding wires, one end of described two bonding wires links to each other with described two the first soldered balls respectively, and the other end links to each other by the thermocompression bonding mode with described the second weld pad.
2. chipset assembling structure as claimed in claim 1 is characterized in that: distance is identical between described two the first soldered balls and the described chip.
3. chipset assembling structure as claimed in claim 1, it is characterized in that: the welding position of described each the above two bonding wire of the second weld pad overlaps.
4. chipset assembling structure as claimed in claim 1 is characterized in that: described two are wired in place, described the second weld pad welding position and form a wedge-shaped part.
5. chipset assembling structure as claimed in claim 1 is characterized in that: the material of described the first soldered ball, described the second soldered ball and described bonding wire is gold.
6. a chip assemble method is characterized in that, comprises the steps:
A circuit board is provided;
A chip is provided;
Chip to be assembled is fixedly installed on circuit board surface, is formed with a plurality of the first weld pads on the described circuit board, be formed with the second corresponding weld pad of a plurality of and described the first weld pad on the described chip;
On each described first weld pad, form two the second soldered balls;
Two bonding wires are provided, an end of described two bonding wires is welded mutually with described the second soldered ball respectively;
With described two bonding wires by described the first soldered ball tractive to described the second weld pad, the other end of described bonding wire is soldered on described the second weld pad in the thermocompression bonding mode.
7. chip assemble method as claimed in claim 6 is characterized in that: interval same distance between two the first soldered balls that form on described the first weld pad and the described chip.
8. chip assemble method as claimed in claim 6 is characterized in that: with thermocompression bonding the other end of described bonding wire is soldered on described the second weld pad in the step, the welding position of two bonding wires overlaps on described the second weld pad.
9. chip assemble method as claimed in claim 6 is characterized in that: described two are wired in place, described the second weld pad welding position and form a wedge-shaped part.
10. chip assemble method as claimed in claim 6 is characterized in that: the material of described the first soldered ball, described the second soldered ball and described bonding wire is gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101256105A CN103378046A (en) | 2012-04-26 | 2012-04-26 | Chip assembling structure and chip assembling method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101256105A CN103378046A (en) | 2012-04-26 | 2012-04-26 | Chip assembling structure and chip assembling method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103378046A true CN103378046A (en) | 2013-10-30 |
Family
ID=49462957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101256105A Pending CN103378046A (en) | 2012-04-26 | 2012-04-26 | Chip assembling structure and chip assembling method |
Country Status (1)
| Country | Link |
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| CN (1) | CN103378046A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107808829A (en) * | 2017-10-24 | 2018-03-16 | 南京矽邦半导体有限公司 | One kind is directed to the small secondary wire soldering method of pad chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
| JPH07335680A (en) * | 1994-06-14 | 1995-12-22 | Fujitsu Ltd | Circuit board, its manufacture, wire bonding method for semiconductor device and sealing method for the same device |
| US6034423A (en) * | 1998-04-02 | 2000-03-07 | National Semiconductor Corporation | Lead frame design for increased chip pinout |
| JP2005251957A (en) * | 2004-03-04 | 2005-09-15 | Renesas Technology Corp | Semiconductor device |
| CN201804856U (en) * | 2010-09-05 | 2011-04-20 | 四川大雁微电子有限公司 | Surface-mounted semiconductor element |
-
2012
- 2012-04-26 CN CN2012101256105A patent/CN103378046A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
| JPH07335680A (en) * | 1994-06-14 | 1995-12-22 | Fujitsu Ltd | Circuit board, its manufacture, wire bonding method for semiconductor device and sealing method for the same device |
| US6034423A (en) * | 1998-04-02 | 2000-03-07 | National Semiconductor Corporation | Lead frame design for increased chip pinout |
| JP2005251957A (en) * | 2004-03-04 | 2005-09-15 | Renesas Technology Corp | Semiconductor device |
| CN201804856U (en) * | 2010-09-05 | 2011-04-20 | 四川大雁微电子有限公司 | Surface-mounted semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107808829A (en) * | 2017-10-24 | 2018-03-16 | 南京矽邦半导体有限公司 | One kind is directed to the small secondary wire soldering method of pad chip |
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Application publication date: 20131030 |