CN103350983B - Integrated wafer-level vacuum packaged MEMS device and manufacturing method thereof - Google Patents
Integrated wafer-level vacuum packaged MEMS device and manufacturing method thereof Download PDFInfo
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- CN103350983B CN103350983B CN201310272193.1A CN201310272193A CN103350983B CN 103350983 B CN103350983 B CN 103350983B CN 201310272193 A CN201310272193 A CN 201310272193A CN 103350983 B CN103350983 B CN 103350983B
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Abstract
The invention discloses an integrated wafer-level vacuum packaged MEMS device and a manufacturing method thereof. The manufacturing method comprises the following steps: forming an MEMS structure on a monocrystalline silicon wafer substrate; forming a first sacrificial layer on the MEMS structure; forming a patterned electrode layer on the first sacrificial layer; forming a second sacrificial layer on the electrode layer; forming a sealed cavity on the monocrystalline silicon wafer substrate located below the MEMS structure and sealing the cavity with a third sacrificial layer; allowing the second and third sacrificial layers to be patterned; forming a cover layer on the third sacrificial layer; allowing the cover layer to be patterned and removing the first, second and third sacrificial layers to enable the MEMS structure to be released; forming a sealing structure on the cover layer; forming a metal lead wire on the sealing structure; and carrying out low temperature annealing. According to the invention, the MEMS structure is a monocrystalline silicon material and is anchored on the upper part of a packaging structure, so influence of the stress of the substrate on the device is reduced; a gap between an electrode and the MEMS structure is fairly small, so energy loss of the device is reduced, and low cost and high quality of the MEMS device are obtained.
Description
Technical field
The present invention relates to semiconductor fabrication, be specifically related to a kind of MEMS and manufacture method thereof of integrated wafer-level vacuum packaged.
Background technology
MEMS (Micro-Electro-Mechanical Systems, be called for short MEMS), referring to can batch making, integrates micro mechanism, microsensor, the microdevice of micro actuator and signal transacting and control circuit etc. or system.MEMS manufacturing technology has merged multiple Micrometer-Nanometer Processing Technology, opens a brand-new technical field and industry.The microsensor adopting MEMS technology to make has very wide application prospect in Aeronautics and Astronautics, automobile, military affairs and all spectra that almost people touch.
Current modal MEMS manufacture method uses isolate supports (SOI) wafer to manufacture MEMS exactly.Sacrifice layer now between MEMS structure and substrate is the silica material in the middle of SOI wafer, the material that binds is the polysilicon, silica, germanium silicon etc. of epitaxially grown polysilicon or low-pressure chemical vapor phase deposition (LPCVD), and MEMS structure and the sacrifice layer bound between material are LPCVD silica.Another kind of manufacture method uses monocrystalline silicon wafer crystal to manufacture MEMS exactly, and the crystal orientation of usual monocrystalline silicon wafer crystal is <100>.Now MEMS structure is manufactured by epitaxially grown silicon materials, this silicon epitaxial layers part is monocrystalline silicon, and another part is polysilicon, the material that binds of Vacuum Package is epitaxially grown polysilicon or LPCVD silica, and the sacrifice layer between MEMS structure and substrate or Vacuum Package capping layer is low-doped silicon.
But use now SOI wafer to manufacture the method for MEMS mainly based on wafer bonding technique, its manufacturing process is complicated, processing cost is high, adds the manufacturing cost of MEMS.On the other hand, if use epitaxially grown silicon materials to process MEMS structure, because silicon epitaxial layers comprises partial polysilicon, and in polycrystalline silicon material, there is structure cell boundary effect, substantially increase the energy loss of MEMS.And the structure member of MEMS conventional at present is all anchored on the substrate layer of bottom, like this in follow-up encapsulation process, in substrate, any unmatched residual stress all can cause the distortion of MEMS structure parts anchor point, greatly have impact on the performance of MEMS.
Summary of the invention
The object of the invention is to the MEMS and the manufacture method thereof that propose a kind of integrated wafer-level vacuum packaged, to solve in MEMS the problem that there is substrate stress, reduce the manufacturing cost of MEMS.
The invention discloses a kind of manufacture method of MEMS of integrated wafer-level vacuum packaged, comprise the following steps:
Monocrystalline silicon wafer crystal substrate forms MEMS structure;
Described MEMS structure is formed the first sacrifice layer;
Described first sacrifice layer forms patterned electrode layer;
Described patterned electrode layer forms the second sacrifice layer;
Described monocrystalline silicon wafer crystal substrate forms sealed cavity, and wherein said sealed cavity is positioned at below MEMS structure, and described sealed cavity is sealed by the 3rd sacrifice layer be formed on described second sacrifice layer;
Graphically described second sacrifice layer and the 3rd sacrifice layer, described second sacrifice layer and the 3rd sacrifice layer form hatch frame;
Described patterned 3rd sacrifice layer forms cover layer, and described cover layer is connected with the opening on the 3rd sacrifice layer by described second sacrifice layer with described electrode layer;
Graphical described cover layer, described cover layer forms hatch frame, and the part-structure of the part-structure of described first sacrifice layer, the part-structure of described second sacrifice layer and described 3rd sacrifice layer is removed by described tectal hatch frame, MEMS structure is discharged;
Described cover layer forms hermetically-sealed construction, described hermetically-sealed construction has the hatch frame for Metal Contact;
Described hermetically-sealed construction forms metal lead wire;
Process annealing.
Further, the crystal orientation of described monocrystalline silicon wafer crystal substrate is <111>.
Further, described MEMS structure is formed the first sacrifice layer and also comprises graphically described first sacrifice layer, described first sacrifice layer obtains hatch frame, the hatch frame of wherein said first sacrifice layer is for determining the anchor station of described MEMS structure.
Further, described monocrystalline silicon wafer crystal substrate forms sealed cavity to comprise:
Described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate form the opening that at least one is communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, for monocrystalline silicon wafer crystal substrate described in expose portion;
By described opening, described monocrystalline silicon wafer crystal substrate forms a cavity, and wherein said cavity is positioned at below MEMS structure, and the method that described monocrystalline silicon wafer crystal substrate is formed cavity is the anisotropic etching method of silicon;
Described second sacrifice layer forms the 3rd sacrifice layer, seals described opening, make described cavity form a sealed cavity.
Further, described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate form at least one opening being communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate to comprise:
Described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate are formed the first opening that at least one is communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, and the degree of depth of the first opening wherein on described monocrystalline silicon wafer crystal substrate is less than the height of described MEMS structure;
Form protective layer at the inner surface of described first opening, and remove the described protective layer being positioned at described first opening lower surface;
Described first opening continues formation second opening, and the first opening degree of depth wherein on described monocrystalline silicon wafer crystal substrate and the second opening degree of depth sum are greater than the height of described MEMS structure.
Further, the thickness of described protective layer is less than the thickness sum of the first sacrifice layer and the second sacrifice layer.
Further, removing the method being positioned at the described protective layer of described first opening lower surface is autoregistration anisotropic etching method.
Further, described cover layer forms hermetically-sealed construction to comprise:
Described cover layer forms insulating barrier, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
Further, described electrode layer and cover layer are all epitaxially grown polysilicon layers, and doping type is identical.
Further, described cover layer forms hermetically-sealed construction to comprise:
Described cover layer forms sealant, and graphical described cover layer and sealant form hatch frame, and wherein said hatch frame aligns with described second sacrifice layer do not removed and the 3rd sacrifice layer;
Described sealant forms insulating barrier, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
Further, described electrode layer, cover layer and sealant are all epitaxially grown polysilicon layers, and doping type is identical.
The present invention discloses a kind of MEMS of integrated wafer-level vacuum packaged on the other hand, comprising:
Monocrystalline silicon wafer crystal substrate;
Etch the MEMS structure that described monocrystalline silicon wafer crystal substrate is formed;
Be arranged on the electrode layer in described MEMS structure, for controlling MEMS structure;
Be arranged on the cover layer above described electrode layer, the second cavity being formed in the first cavity between described cover layer and described MEMS structure and being formed between described MEMS structure and described monocrystalline silicon wafer crystal substrate, wherein said cover layer is connected with described electrode layer electricity, described cover layer and described electrode layer are formed with hatch frame, and described hatch frame is used for electric isolution;
Be arranged on the separation layer between described monocrystalline silicon wafer crystal substrate and cover layer, for sealing the side of described first cavity;
Be arranged on described supratectal hermetically-sealed construction, for sealing described tectal hatch frame, wherein said first cavity and the second cavity form sealed cavity, and described MEMS structure can be movable in described sealed cavity;
Be arranged on the metal lead wire on described hermetically-sealed construction.
Further, described electrode layer and cover layer are all epitaxially grown polysilicon layers, and doping type is identical.
The present invention directly forms MEMS structure on monocrystalline silicon wafer crystal substrate, and the monocrystalline silicon wafer crystal substrate below MEMS structure forms sealed cavity, electrode layer and hermetically-sealed construction is formed above MEMS structure, make MEMS structure be anchored to the top of encapsulating structure, reduce the residual stress effect that substrate brings.The present invention uses multiple sacrificial layer structure for the release of MEMS structure, makes the gap between electrode and MEMS movable structure very little, usually tens nanometers, can reduce the driving voltage of MEMS and then reduce total power consumption.MEMS structure is single crystal silicon material simultaneously, there is not structure cell boundary effect, reduce the energy loss of device, and MEMS has the Vacuum Package of wafer scale, achieve the MEMS manufacturing process of low cost, high-quality.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of first embodiment of the invention.
Fig. 2 A-2P is the process chart of the manufacture method of first embodiment of the invention.
Fig. 3 A-3C is the process chart of the manufacture method of second embodiment of the invention.
Fig. 4 is the structural representation of the MEMS of third embodiment of the invention.
Fig. 5 is the structural representation of the MEMS of fourth embodiment of the invention.
Detailed description of the invention
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing and not all.
First embodiment
Fig. 1 is the flow chart of the manufacture method of the MEMS of the integrated wafer-level vacuum packaged of first embodiment of the invention, and Fig. 2 A-2P is the process chart of the manufacture method of first embodiment of the invention.As shown in Figure 1, described manufacture method comprises:
Step 101, on monocrystalline silicon wafer crystal substrate, form MEMS structure.Described step 101 comprises three sub-steps:
Step 101A, on monocrystalline silicon wafer crystal substrate, form mask layer.
As shown in Figure 2 A, be deposit mask layer 202 on <111> monocrystalline silicon wafer crystal substrate 201 in crystal orientation, described mask layer 202 can be silica, low-pressure chemical vapor deposition (LPCVD) silica or plasma activated chemical vapour deposition (PECVD) silica that heat grows.
Crystal orientation is referred to and to be arranged by the atom of the different directions of crystal atomic centers.Because monocrystal is made up of the arrangement of atom periodic regular, therefore can mark off a series of crystal face parallel to each other in monocrystal, mark a crystal face traditionally by the indices of crystallographic plane, crystal orientation just can represent by the normal direction perpendicular to this crystal face.Because silicon belongs to cubic crystal structure, on different crystal face, the arranging density of atom is different, causes the anisotropy of silicon crystal, and therefore the diffusion velocity of impurity, corrosion rate are not identical yet.The atomic density of silicon single crystal on crystal face is at crystal orientation <111>, crystal orientation <110> and crystal orientation <100> successively decreases successively, therefore Impurity Diffusion speed is at crystal orientation <111>, crystal orientation <110> and crystal orientation <100> increases progressively successively, then corrosion rate is at crystal orientation <111>, crystal orientation <110> and crystal orientation <100> increases progressively successively.
Chemical vapor deposition, be called for short CVD (Chemical Vapor Deposition) and supply substrate containing one or several compounds or elementary gas of forming film element, required film is generated by gas phase action or at on-chip chemical reaction, concrete finger gas-phase reaction at high temperature, such as, metal halide, organic metal, hydrocarbon etc. thermal decomposition, hydrogen reduction or make its mist chemical reaction at high temperature occur with the method for the inorganic material such as precipitating metal, oxide, carbide.And low-pressure chemical vapor deposition, be called for short LPCVD(Low Pressure Chemical Vapor Deposition) refer to the chemical vapour deposition (CVD) carried out under lower than an atmospheric condition.Plasma activated chemical vapour deposition, is called for short PECVD(Plasma Enhanced Chemical Vapor Deposition) refer in low pressure chemical vapor deposition, to utilize glow discharge plasma affect growing film.
Chemical vapour deposition (CVD) has can deposit the plurality of advantages such as all kinds of film, film forming speed compactness that is fast, film is good, residual stress is little, film purity is high, so be widely used in the technical field such as refining, powder synthesis, semiconductive thin film of high purity metal.The effect of chemical vapour deposition (CVD) is exactly the various functional thin layer of deposit in an embodiment of the present invention, to realize the technological effect that the embodiment of the present invention will reach.
Mask layer described in step 101B, patterning forms hatch frame.
As shown in Figure 2 B, graphical described mask layer 202, specifically, on described mask layer 202, the techniques such as photoetching, dry etching or wet etching are adopted to remove the part-structure of described mask layer 202, to form the patterns of openings of needs on described mask layer 202 exactly.
Step 101C, carry out etching to form MEMS structure on described monocrystalline silicon wafer crystal substrate by the hatch frame on described mask layer.As shown in Figure 2 C, monocrystalline silicon wafer crystal substrate 201 adopts deep reactive ion silicon etching (DRIE) technique etch and obtain MEMS structure 203, and lift off mask layer.Can obtain some deep holes after etching, the size and shape of described deep hole needs to determine according to the design of MEMS.
Deep reactive ion silicon etching (DRIE) is the principle (being also referred to as " suitching type etching technics ") based on " Bosch technique ", can provide a kind of method of fabulous anisotropic high speed etch silicon, keep very high etching photoresistance Selection radio simultaneously.This method is in plasma etch system, repeats etching and polymer deposits step in proper order.Polymer deposits step can form protecting film on silicon guide hole sidewall, prevents side direction from etching.Etch step is optimised, first bottom etching structure, removes deposited polymer, then etches the silicon under it with high etch rate.In embodiments of the present invention, DRIE technique is for the formation of high-precision MEMS structure.
In a preferred embodiment of the embodiment of the present invention, preferred described mask layer 202 is photoresist, as the technological process of Fig. 2 A-2C, can realize, simplify procedure of processing by means of only a photoetching process.
Step 102, in described MEMS structure, form the first sacrifice layer.
As shown in Figure 2 D, described MEMS structure 203 is formed the first sacrifice layer 204, described MEMS structure is formed the first sacrifice layer and also comprises graphically described first sacrifice layer 204, described first sacrifice layer obtains hatch frame, and the hatch frame of wherein said first sacrifice layer 204 is for determining the anchor station of described MEMS structure.
Particularly, described first sacrifice layer 204 uses chemical vapor deposition method to be formed, and its material is silica.Graphically described first sacrifice layer 204 just refers to that techniques such as adopting photoetching, dry etching or wet etching removes the part-structure of described first sacrifice layer 204, to form the pattern of needs on described first sacrifice layer 204, the position of described pattern is exactly the position that MEMS structure 203 arranges anchor point.
It should be noted that, graphic method described in the embodiment of the present invention all refers to and adopts the technique removal unit separation structure such as photoetching, dry etching or wet etching, thus forms the method for required pattern, after will repeat no more.
Step 103, on described first sacrifice layer, form patterned electrode layer, as the electrode of MEMS.
As shown in Figure 2 E, described first sacrifice layer 204 forms patterned electrode layer 205.Specifically, described electrode layer 205 is formed by epitaxially grown polysilicon, and is in-situ doped into P type or N-type.Epitaxial growth just refers to the process in the upper growth of certain starting crystals (substrate) with the laminar crystalline of identical or close crystallographic orientation.Being used for each component of growth compound crystal and adulterant can pass in reative cell with gaseous form, can be controlled the characteristic such as component, conduction type, carrier concentration, thickness of epitaxial layer by the flow controlling various gas.Extension occurs on the surface of the substrate of heating, can control course of reaction by monitoring substrate temperature.
Step 104, on described patterned electrode layer, form the second sacrifice layer.
As shown in Figure 2 F, on described patterned electrode layer 205, deposit forms the second sacrifice layer 206, and the material of described second sacrifice layer 206 is silica.
In a preferred embodiment of the embodiment of the present invention, use LPCVD ethyl orthosilicate (TEOS) technique deposit second sacrifice layer 206.When using the reactant source of TEOS as chemical vapor deposition, because TEOS molecule does not have symmetrical structure completely, hydrogen bond can be formed at substrate surface and surface mobility is high, there is better step coverage characteristics.
Step 105, on described monocrystalline silicon wafer crystal substrate, form sealed cavity, wherein said sealed cavity is positioned at below MEMS structure, and described sealed cavity is sealed by the 3rd sacrifice layer be formed on described second sacrifice layer.Described step 105 comprises three sub-steps:
Step 105A, on described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, form at least one opening being communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, for monocrystalline silicon wafer crystal substrate described in expose portion.Described step 105A also comprises three sub-steps:
Step 105AI, on described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, form at least one first opening being communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, the degree of depth of the first opening wherein on described monocrystalline silicon wafer crystal substrate is less than the height of described MEMS structure.
As shown in Figure 2 G, described first sacrifice layer 204, second sacrifice layer 206 with monocrystalline silicon wafer crystal substrate 201 form the first opening that is communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate.Specifically, first on described first sacrifice layer 204 and second layer sacrifice layer 206, the opening that one runs through described first sacrifice layer 204 and second layer sacrifice layer 206 is etched, then the opening of the first sacrifice layer 204 and second layer sacrifice layer 206 is run through described in passing through, DRIE technique is adopted to continue the described monocrystalline silicon wafer crystal substrate 201 of etching thus obtain the first opening, the degree of depth of described first opening on described monocrystalline silicon wafer crystal substrate 201 is H1, and wherein H1 is less than the height D of described MEMS structure 203.
Step 105AII, form protective layer at the inner surface of described first opening, and remove and be positioned at the described protective layer of described first opening lower surface.
As illustrated in figure 2h, form protective layer 207 at the inner surface of described first opening, particularly, the described protective layer 207 obtained by thermal oxide growth method is silica material, and its thickness is T3.So, described first sacrifice layer 204, second sacrifice layer 206 and protective layer 207 are all silica, and the thickness T3 of described protective layer 207 will much smaller than the thickness T2 sum of the thickness T1 of described first sacrifice layer 204 and the second sacrifice layer 206.Therefore, autoregistration anisotropic oxide silicon dry etch process just can be adopted to remove the described protective layer 207 being positioned at described first opening lower surface.Like this, the part that described protective layer 207 is positioned at the first open side is retained, for the cross-protection of described first opening.
So-called self-aligned technology refers to that in microelectric technique, utilize element, device architecture feature to realize recovery prints self-aligning technology.When using the removal of autoregistration anisotropic oxide silicon dry etching to be positioned at the described protective layer 207 of described first opening lower surface; etching depth is the thickness T3 of described protective layer 207; because the thickness T1 of described first sacrifice layer 204 and the thickness T2 sum of the second sacrifice layer 206 are much larger than T3; so described Self-aligned etching does not affect described first sacrifice layer 204 and the second sacrifice layer 206 substantially, thus simplify etch step.
Step 105AIII, on described first opening, continue formation second opening, the first opening degree of depth wherein on described monocrystalline silicon wafer crystal substrate and the second opening degree of depth sum are greater than the height of described MEMS structure.
As shown in figure 2i, described first opening continues formation second opening, lithographic method still adopts DRIE technique, the degree of depth of described second opening is H2, and the first opening depth H 1 wherein on described monocrystalline silicon wafer crystal substrate 201 and the second opening depth H 2 sum are greater than the height D of described MEMS structure.
Step 105B, by described opening, on described monocrystalline silicon wafer crystal substrate formed a cavity, wherein said cavity is positioned at below MEMS structure, and the method that described monocrystalline silicon wafer crystal substrate is formed cavity is the anisotropic etching method of silicon.
As shown in fig. 2j, by the hatch frame on described monocrystalline silicon wafer crystal substrate 201, be positioned at a formation cavity on the described monocrystalline silicon wafer crystal substrate 201 below MEMS structure 203, the method wherein forming cavity is the anisotropic etching method of silicon, etching solution can be potassium hydroxide (KOH) or TMAH (TMAH), because the etching of etching solution to silicon crystal different crystal orientations has selective, and employ the monocrystalline silicon wafer crystal substrate 201 in <111> crystal orientation in embodiments of the present invention, so very smooth housing surface can be formed after etching.The degree of depth of described cavity is the height D that described first opening depth H 1 and the second opening depth H 2 sum deduct described MEMS structure.
Step 105C, on described second sacrifice layer formed the 3rd sacrifice layer, seal described opening, make described cavity form a sealed cavity.
As shown in figure 2k, on described second sacrifice layer 206, deposit forms the 3rd sacrifice layer 208, and seal described opening, make described cavity form a sealed cavity, the material of wherein said 3rd sacrifice layer 208 is silica.
Step 106, graphically described second sacrifice layer and the 3rd sacrifice layer, described second sacrifice layer and the 3rd sacrifice layer form hatch frame.
As shown in figure 2l, graphically described second sacrifice layer 206 and the 3rd sacrifice layer 208, on described second sacrifice layer 206 and the 3rd sacrifice layer 208, etching forms hatch frame.
Step 107, on described patterned 3rd sacrifice layer, form cover layer, described cover layer is connected by the opening of described second sacrifice layer with the 3rd sacrifice layer with described electrode layer.
As shown in figure 2m, described patterned second sacrifice layer 206 forms cover layer 209, and described cover layer 209 is connected with the opening of the 3rd sacrifice layer 208 by described second sacrifice layer 206 with described electrode layer 205.Specifically, described cover layer 209 is formed by epitaxially grown polysilicon, and is in-situ doped into P type or N-type, and its doping type is the same with the doping type of described electrode layer 205, and described like this cover layer 209 and described electrode layer 205 achieve electricity and be connected.
Step 108, graphical described cover layer, described cover layer forms hatch frame, and the part-structure of the part-structure of described first sacrifice layer, the part-structure of described second sacrifice layer and described 3rd sacrifice layer is removed by described tectal hatch frame, MEMS structure is discharged.
As shown in figure 2n, graphical described cover layer 209, namely on described cover layer 209, etching forms hatch frame, and pass through the hatch frame of described cover layer 209, use the first sacrifice layer 204, second sacrifice layer 206 and the 3rd sacrifice layer 208 described in gaseous state hf etching, MEMS structure is discharged.
It should be noted that, described first sacrifice layer 204, second sacrifice layer 206 and the 3rd sacrifice layer 208 are not etched removal completely, but remain a part and form as the part of follow-up vacuum encapsulation structure.Because described first sacrifice layer 204, second sacrifice layer 206 and the 3rd sacrifice layer 208 are all silica materials, structurally can regard an entirety as, so in the technique that the present embodiment is follow-up, unified use the 3rd sacrifice layer 208 is representatively described.
Step 109, on described cover layer, form hermetically-sealed construction, described hermetically-sealed construction has the hatch frame for Metal Contact.
As shown in Figure 2 O, on described cover layer 209, deposit forms insulating barrier 210, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier 210 is used for Metal Contact.
Step 110, on described hermetically-sealed construction, form metal lead wire, described metal lead wire is connected with external control circuit.
As shown in figure 2p, described hermetically-sealed construction forms metal lead wire 211.
Step 111, process annealing.
Finally, process annealing is carried out to the MEMS adopting above-mentioned technological process to make
The embodiment of the present invention forms MEMS structure by directly etching on monocrystalline silicon wafer crystal substrate, and the monocrystalline silicon wafer crystal substrate below MEMS structure forms sealed cavity, MEMS structure is made to be single crystal silicon material, there is not structure cell boundary effect, decrease the energy loss of MEMS, and MEMS structure is anchored to the top of encapsulating structure, reduce the stress effect that substrate brings.The present embodiment employs the release of multiple sacrificial layer structure for MEMS structure, makes the gap between electrode and MEMS movable structure very little, can reduce the driving voltage of MEMS and then reduce total power consumption.Monocrystalline silicon wafer crystal manufacturing process is simple, cheap simultaneously, thus reduces the production cost of MEMS.
Second embodiment
Fig. 3 A-3C is the process chart of the manufacture method of second embodiment of the invention.The technological process of described second embodiment of the invention is identical to the technique of step 108 with the step 101 in described first embodiment, repeats no more here, on the basis of described step 108, continues the technological process of described third embodiment of the invention, comprising:
Step 109 ＇, on described cover layer, form hermetically-sealed construction, described hermetically-sealed construction has the hatch frame for Metal Contact.Described step 109 ＇ comprises two sub-steps:
Step 109 ＇ A, on described cover layer, form sealant, graphical described cover layer and sealant form hatch frame, and wherein said hatch frame aligns with described second sacrifice layer do not removed and the 3rd sacrifice layer.
As shown in Figure 3A, described cover layer 209 forms sealant 212, graphical described cover layer 209 and sealant 212 form hatch frame, and wherein said hatch frame aligns with described second sacrifice layer 206 do not removed and the 3rd sacrifice layer 208.Specifically, described sealant 212 is formed by epitaxially grown polysilicon, and is in-situ doped into P type or N-type, and its doping type is the same with the doping type of described electrode layer 205 and described cover layer 209.Hatch frame is formed at described cover layer 209 and sealant 212 by etching technics, and described hatch frame aligns with described second sacrifice layer 206 do not removed and the 3rd sacrifice layer 208, achieve the electric isolution of described electrode layer 205 different piece like this at the seal ensureing not destroy sealed cavity simultaneously.
It should be noted that, described second sacrifice layer 206 and the 3rd sacrifice layer 208 are all silica materials, structurally can regard an entirety as, so in the technique that the present embodiment is follow-up, unified use the 3rd sacrifice layer 208 is representatively described.
Step 109 ＇ B, on described sealant, form insulating barrier, graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
As shown in Figure 3 B, on described sealant 212, deposit forms insulating barrier 213, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier 213 is used for Metal Contact.
Step 110 ＇, on described insulating barrier, form metal lead wire, described metal lead wire is connected with external control circuit.
As shown in Figure 3 C, described insulating barrier 213 forms metal lead wire 214.
Step 111 ＇, process annealing.
Finally, process annealing is carried out to the MEMS adopting above-mentioned technological process to make.
The embodiment of the present invention seals the cavity structure of MEMS by the mode of epitaxial growth polysilicon, like this in described sealed cavity remaining gas based on hydrogen, because hydrogen molecule is minimum, so in follow-up process annealing process, not only reduce the contact resistance of metal and polysilicon, and the remaining hydrogen in sealed cavity is all spread out, achieve the Vacuum Package of pressure millitorr level.
3rd embodiment
Fig. 4 is the structural representation of the MEMS of the integrated wafer-level vacuum packaged of third embodiment of the invention, and wherein said MEMS adopts the technological process manufacture of first embodiment of the invention to obtain.As shown in Figure 4, described device comprises:
Monocrystalline silicon wafer crystal substrate 41.
Etch the MEMS structure 42 that described monocrystalline silicon wafer crystal substrate 41 is formed.
Be arranged on the electrode layer 43 in described MEMS structure 42, for controlling MEMS structure 42.
Be arranged on the cover layer 44 above described electrode layer 43, the second cavity being formed in the first cavity between described cover layer 44 and described MEMS structure 42 and being formed between described MEMS structure 42 and described monocrystalline silicon wafer crystal substrate 41, wherein said cover layer 44 is connected with described electrode layer 43 electricity, described cover layer 44 and described electrode layer 43 are formed with hatch frame, described hatch frame is used for electric isolution, described electrode layer 43 and cover layer 44 are all epitaxially grown polysilicon layers, and doping type is identical.
Be arranged on the separation layer 45 between described monocrystalline silicon wafer crystal substrate 41 and cover layer 44, for sealing the side of described first cavity.
Be arranged on the hermetically-sealed construction 46 on described cover layer 44, for sealing the hatch frame of described cover layer 44, wherein said first cavity and the second cavity form sealed cavity, and described MEMS structure 42 can be movable in described sealed cavity.
Be arranged on the metal lead wire 47 on described hermetically-sealed construction 46, for connecting external control circuit.
The embodiment of the present invention arranges MEMS structure on monocrystalline silicon wafer crystal substrate, and the monocrystalline silicon wafer crystal substrate below MEMS structure arranges sealed cavity, MEMS structure is made to be single crystal silicon material, there is not structure cell boundary effect, decrease the energy loss of MEMS, and MEMS structure is anchored to the top of encapsulating structure, reduce the stress effect that substrate brings.Simultaneously because the manufacturing process of monocrystalline silicon wafer crystal is simple, cheap, thus reduce the production cost of MEMS.
4th embodiment
Fig. 5 is the structural representation of the MEMS of the integrated wafer-level vacuum packaged of fourth embodiment of the invention, and wherein said MEMS adopts the technological process manufacture of second embodiment of the invention to obtain.As shown in Figure 5, described device comprises:
Monocrystalline silicon wafer crystal substrate 51.
Etch the MEMS structure 52 that described monocrystalline silicon wafer crystal substrate 51 is formed.
Be arranged on the electrode layer 53 in described MEMS structure 52, for controlling MEMS structure 52.
Be arranged on the cover layer 54 above described electrode layer 53, the second cavity being formed in the first cavity between described cover layer 54 and described MEMS structure 52 and being formed between described MEMS structure 52 and described monocrystalline silicon wafer crystal substrate 51, wherein said cover layer 54 is connected with described electrode layer 53 electricity.
Be arranged on the separation layer 55 between described monocrystalline silicon wafer crystal substrate 51 and cover layer 54, for sealing the side of described first cavity.
Be arranged on the sealant 56 on described cover layer 54, for sealing the hatch frame of described cover layer 54, wherein said first cavity and the second cavity form sealed cavity, described MEMS structure 52 can be movable in described sealed cavity, described cover layer 54 and described sealant 56 are formed with hatch frame, and described hatch frame is used for electric isolution.
It should be noted that, described electrode layer 53, cover layer 54 and sealant 56 are all epitaxially grown polysilicon layers, and doping type is identical.Position and the separation layer 55 of described cover layer 54 and the hatch frame on described sealant 56 align, wherein separation layer 55 refers to the part between electrode layer 53 and cover layer 54, achieves the electric isolution of described electrode layer 205 different piece like this at the seal ensureing not destroy described sealed cavity simultaneously.
Be arranged on the insulating barrier 57 on described sealant 56, described sealant 56 and insulating barrier 57 constitute the hermetically-sealed construction of device.
Be arranged on the metal lead wire 58 on described insulating barrier 57, it is for connecting external control circuit.
The embodiment of the present invention uses epitaxially grown polysilicon to seal the cavity structure of MEMS, this makes gas remaining in the sealed cavity of MEMS based on hydrogen, because hydrogen molecule is minimum, so only surplus remaining hydrogen almost all spreads out in process annealing process, achieve the Vacuum Package of pressure millitorr level.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (12)
1. a MEMS manufacture method for integrated wafer-level vacuum packaged, is characterized in that, comprise the following steps:
On monocrystalline silicon wafer crystal substrate, etching forms MEMS structure;
Described MEMS structure is formed the first sacrifice layer;
Described first sacrifice layer forms patterned electrode layer;
Described patterned electrode layer forms the second sacrifice layer;
Described monocrystalline silicon wafer crystal substrate forms sealed cavity, and wherein said sealed cavity is positioned at below MEMS structure, and described sealed cavity is sealed by the 3rd sacrifice layer be formed on described second sacrifice layer;
Graphically described second sacrifice layer and the 3rd sacrifice layer, described second sacrifice layer and the 3rd sacrifice layer form hatch frame;
Described patterned 3rd sacrifice layer forms cover layer, and described cover layer is connected with the opening on the 3rd sacrifice layer by described second sacrifice layer with described electrode layer;
Graphical described cover layer, described cover layer forms hatch frame, and the part-structure of the part-structure of described first sacrifice layer, the part-structure of described second sacrifice layer and described 3rd sacrifice layer is removed by described tectal hatch frame, MEMS structure is discharged;
Described cover layer forms hermetically-sealed construction, described hermetically-sealed construction has the hatch frame for Metal Contact;
Described hermetically-sealed construction forms metal lead wire;
Process annealing;
Wherein, described monocrystalline silicon wafer crystal substrate forms sealed cavity specifically to comprise:
Described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate form the opening that at least one is communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, for monocrystalline silicon wafer crystal substrate described in expose portion;
By described opening, described monocrystalline silicon wafer crystal substrate forms a cavity, and wherein said cavity is positioned at below MEMS structure, and the method that described monocrystalline silicon wafer crystal substrate is formed cavity is the anisotropic etching method of silicon;
Described second sacrifice layer forms the 3rd sacrifice layer, seals described opening, make described cavity form a sealed cavity.
2. the method for claim 1, is characterized in that, the crystal orientation of described monocrystalline silicon wafer crystal substrate is <111>.
3. the method for claim 1, it is characterized in that, described MEMS structure is formed the first sacrifice layer and also comprises graphically described first sacrifice layer, described first sacrifice layer obtains hatch frame, and the hatch frame of wherein said first sacrifice layer is for determining the anchor station of described MEMS structure.
4. the method for claim 1, is characterized in that, described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate is formed at least one opening being communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate and comprises:
Described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate are formed the first opening that at least one is communicated with described first sacrifice layer, the second sacrifice layer and monocrystalline silicon wafer crystal substrate, and the degree of depth of the first opening wherein on described monocrystalline silicon wafer crystal substrate is less than the height of described MEMS structure;
Form protective layer at the inner surface of described first opening, and remove the described protective layer being positioned at described first opening lower surface;
Described first opening continues formation second opening, and the first opening degree of depth wherein on described monocrystalline silicon wafer crystal substrate and the second opening degree of depth sum are greater than the height of described MEMS structure.
5. method as claimed in claim 4, it is characterized in that, the thickness of described protective layer is less than the thickness sum of the first sacrifice layer and the second sacrifice layer.
6. method as claimed in claim 5, is characterized in that, removing the method being positioned at the described protective layer of described first opening lower surface is autoregistration anisotropic etching method.
7. the method for claim 1, is characterized in that, described cover layer forms hermetically-sealed construction and comprises:
Described cover layer forms insulating barrier, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
8. method as claimed in claim 7, it is characterized in that, described electrode layer and cover layer are all epitaxially grown polysilicon layers, and doping type is identical.
9. the method for claim 1, is characterized in that, described cover layer forms hermetically-sealed construction and comprises:
Described cover layer forms sealant, and graphical described cover layer and sealant form hatch frame, and wherein said hatch frame aligns with described second sacrifice layer do not removed and the 3rd sacrifice layer;
Described sealant forms insulating barrier, and graphical described insulating barrier forms hatch frame, and the hatch frame of wherein said insulating barrier is used for Metal Contact.
10. the method as described in claim 1 or 9, is characterized in that, described electrode layer, cover layer and sealant are all epitaxially grown polysilicon layers, and doping type is identical.
The MEMS of 11. 1 kinds of integrated wafer-level vacuum packageds, is characterized in that, comprising:
Monocrystalline silicon wafer crystal substrate;
Etch the MEMS structure that described monocrystalline silicon wafer crystal substrate is formed;
Be arranged on the patterned electrode layer in described MEMS structure, for controlling MEMS structure, described patterned electrode layer has different piece;
Be arranged on the cover layer above described electrode layer, the second cavity being formed in the first cavity between described cover layer and described MEMS structure and being formed between described MEMS structure and described monocrystalline silicon wafer crystal substrate, wherein said cover layer is connected with described electrode layer electricity, described cover layer is formed with hatch frame, and described hatch frame is used for carrying out electric isolution to the different piece of described electrode layer;
Be arranged on the separation layer between described monocrystalline silicon wafer crystal substrate and cover layer, for sealing the side of described first cavity;
Be arranged on described supratectal hermetically-sealed construction, for sealing described tectal hatch frame, wherein said first cavity and the second cavity form sealed cavity, and described MEMS structure can be movable in described sealed cavity;
Be arranged on the metal lead wire on described hermetically-sealed construction.
12. devices as claimed in claim 11, it is characterized in that, described electrode layer and cover layer are all epitaxially grown polysilicon layers, and doping type is identical.
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| CN105067165B (en) * | 2015-07-19 | 2018-02-02 | 江苏德尔森传感器科技有限公司 | The production technology of monocrystalline silicon sensors chip |
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| CN111362228B (en) * | 2018-12-25 | 2023-09-08 | 中芯集成电路（宁波）有限公司 | Packaging method and packaging structure |
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| CN111170266B (en) * | 2019-12-31 | 2023-07-21 | 杭州士兰集成电路有限公司 | Semiconductor device and method for manufacturing the same |
| CN111285326B (en) * | 2020-02-25 | 2023-08-25 | 绍兴中芯集成电路制造股份有限公司 | MEMS device and method of manufacturing the same |
| CN111825053B (en) * | 2020-07-03 | 2023-11-10 | 瑞声科技（南京）有限公司 | Capacitive system and preparation method thereof |
| CN114371551B (en) * | 2020-10-14 | 2022-11-22 | 中国科学院上海微系统与信息技术研究所 | Micro-mirror structure and preparation method thereof |
| CN116425110B (en) * | 2023-06-12 | 2023-09-19 | 之江实验室 | Wafer-level manufacturing method of high-temperature photoelectric pressure sensing chip with differential structure |
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