CN103325779A - 制造微电子封装的方法 - Google Patents

制造微电子封装的方法 Download PDF

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Publication number
CN103325779A
CN103325779A CN2013102642643A CN201310264264A CN103325779A CN 103325779 A CN103325779 A CN 103325779A CN 2013102642643 A CN2013102642643 A CN 2013102642643A CN 201310264264 A CN201310264264 A CN 201310264264A CN 103325779 A CN103325779 A CN 103325779A
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package substrate
trace
thin slice
dielectric
microelectronic element
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CN103325779B (zh
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贝尔加桑·哈巴
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

一种用于例如半导体芯片的微电子元件（48）的封装，具有介电体（86），该介电体（86）覆盖封装衬底（56）和微电子元件（48），且具有暴露在介电体（86）的顶部表面（94）处的顶部端子（38）。有利地，沿着介电体（86）的边缘表面（96、108）延伸的迹线（36a、36b）将顶部端子（38）连接到封装衬底（56）上的底部端子（64）。介电体（86）可以通过模制或者通过施加共形层（505）而形成。

Description

制造微电子封装的方法
本申请为2011年11月14日提交的申请号为201180022247.8且发明名称为“在介电体上具有端子的微电子封装”的专利申请的分案申请。
相关申请的交叉引用
本申请要求2010年11月15日申请的韩国专利申请No.10-2010-0113271的优先权，其公开此处以引用方式并入。
技术领域
本发明涉及微电子封装。
背景技术
例如半导体芯片的微电子元件通常设置有这样的元件，所述元件保护微电子元件且方便其连接到更大电路的其他元件。例如，典型地，半导体芯片提供为具有相反朝向的前表面和后表面以及暴露在前表面上的触点的小且扁平的元件。该触点电连接到在该芯片内一体形成的多个电路元件。这样的芯片最通常是设置在称为封装衬底的小型化电路面板的封装内。典型地，该芯片安装到这样的封装衬底，所述封装衬底的该前表面或者后表面覆盖该封装衬底的表面，且典型地该封装衬底具有暴露在衬底的表面处的端子。该端子电连接到该芯片的端子。典型地，该封装也包括一定形式的覆盖件，所述覆盖件覆盖与该封装衬底相反的该芯片的一侧上的芯片。该覆盖件用于保护芯片，且在一些情况下，保护封装衬底的芯片和导电元件之间的连接。这样的封装芯片可以通过将该封装衬底的端子连接到例如更大的电路面板上的接触焊盘的导电元件上而被安装到例如电路板的电路面板。
在特定的封装中，该芯片安装成其前表面或者后表面覆盖该封装衬底的上表面，而端子设置在相反面对的下表面上。介电材料体覆盖该芯片，且最典型地，覆盖该芯片和该封装衬底的导电元件之间的电连接。该介电体可以通过在芯片周围模制可流动介电复合物而形成，这样该介电复合物覆盖该芯片，且覆盖该封装衬底的所有或者部分的顶部表面。这样的封装通常称为“包注模（overmolded）”封装，且介电材料体称为“包胶模”（overmold）。包注模封装对于制造是经济的，且因而被广泛使用。
在一些应用中，将芯片封装堆叠（stack）在彼此的顶部上是有利的，这样多个芯片可以设置在更大的电路面板的表面上的相同空间内。特定的包注模封装包括这样的堆叠触点，所述堆叠触点暴露在由该芯片覆盖的区域之外（且典型地由包胶模覆盖的区域之外）的封装衬底的顶部表面处。这样的封装可以用例如焊球或者在堆叠（stack）中、下封装的叠置触点和下一个更高的封装的端子之间延伸的其他导电连接的互连元件而一个叠置在另一个的上面。在这样的布置中，堆叠中的所有封装被电连接到堆叠的底部处的封装上的端子。但是，在这样的布置中，所有的互连元件必须容纳在由包胶模所覆盖的区域之外的该封装衬底的受限区域内。此外，由于该堆叠中的更高的封装的封装衬底坐落在下一个更低封装内的介电包胶模之上，更高的封装的端子和更低的封装的堆叠触点之间沿着垂直方向存在明显的间隙。互连元件可以填补该间隙。这典型地需要互连元件之间以相对大的间隔分开。因此，使用给定尺寸的封装衬底，可以被容纳的互连元件的数目是受限的。
尽管对可堆叠封装以及具有顶表面安装焊盘的其他封装的开发在本领域已经投入了相当的努力，但是仍然需要进一步的改进。
发明内容
本发明的一方面提供了一种微电子封装。有利地，根据本发明的该方面的封装包括第一微电子元件和封装衬底，所述封装衬底具有在水平方向上延伸的上表面和下表面以及在所述上表面与所述下表面之间延伸的边缘。有利地，所述封装衬底具有导电元件，所述导电元件包括在所述封装衬底的所述下表面处暴露的底部端子。优选地，所述微电子元件设置在所述封装衬底的所述上表面之上，且连接至在所述封装衬底上的至少一些所述导电元件。根据本发明的该方面的封装优选地包括覆盖微电子元件和至少一部分的封装衬底的上表面的介电体。所述介电体限定远离所述封装衬底的、背朝所述封装衬底的顶部表面。优选地，所述至少一部分顶部表面在所述微电子元件之上延伸。有利地，所述介电体还限定从邻近所述介电体的所述顶部表面的顶部边沿向下延伸到邻近所述封装衬底的底部边沿，所述底部边沿设置在所述封装衬底的边缘之内。优选地，所述介电体进一步限定远离所述第一边缘表面的所述底部边沿邻近所述封装衬底的水平方向延伸的面朝上的第一凸缘表面。所述第一凸缘表面被设置为距离所述封装衬底的垂直距离小于所述封装衬底与所述顶部表面之间的垂直距离。
最优选地，所述封装包括：多个顶部端子，所述多个顶部端子在所述第一介电体的所述顶部表面处暴露；以及多个第一迹线，所述多个第一迹线从所述顶部端子沿着所述顶部表面延伸且沿着所述第一边缘表面延伸，所述第一迹线具有沿着所述第一凸缘表面延伸的底部部分，所述底部部分电连接至所述封装衬底的所述导电元件。
如下进一步讨论，根据本发明的该方面的特定封装可在封装衬底上提供连接至多个导电元件的多个顶部端子。例如，这些封装可以用在堆叠布置中，其中一个封装的顶部端子连接到另外一个封装的底部端子。
根据本发明的另一方面的封装有利地包括微电子元件和封装衬底，所述封装衬底具有在水平方向上延伸的上表面和下表面，所述微电子元件设置在所述封装衬底的所述上表面之上，所述微电子元件电连接到所述封装衬底上的至少一些导电元件。有利地，根据本发明的该方面的封装包括包胶模，所述包胶模覆盖所述微电子元件和所述微电子元件的至少一部分所述上表面，所述包胶模限定远离所述封装衬底的、背朝所述封装衬底的顶部表面，所述包胶模的至少一部分顶部表面的在所述微电子元件之上延伸。有利地，所述封装进一步包括：顶部端子，所述顶部端子在所述包胶模的所述顶部表面处暴露；以及多个迹线，所述迹线从所述顶部端子沿着所述包胶模的所述顶部表面延伸，所述顶部端子和所述迹线嵌入在所述包胶模内。最为优选地，所述迹线为固态金属迹线。
本发明的另外的方面提供了一种包括与其他电子装置结合的、根据本发明的前述方面的封装的系统。例如，所述系统可以设置在单个壳体内，所述壳体可以为便携式壳体。
本发明的再一方面提供了一种制造微电子封装的方法。一个这样的方法包括如下步骤：在具有导电元件的封装衬底以及覆盖所述封装衬底且电连接至所述导电元件的微电子元件的组装件（assemblage）之上定位承载多个迹线的、例如薄片的承载器（carrier），所述定位步骤被执行，这样至少一些所述迹线中的部分在所述微电子元件之上延伸。有利地，所述方法也包括：将可流动的组合物引入所述承载器与所述封装衬底之间以及所述微电子元件周围，且使所述组合物固化以形成覆盖所述微电子元件且具有至少部分地由所述承载器限定的形状的包胶模。优选地，所述方法也包括：去除所述承载器，以便留下在所述包胶模的背朝所述封装衬底的一个或多个表面之上延伸的所述迹线。
有利地，根据本发明的该方面的另外的方法包括：在具有导电元件的封装衬底以及覆盖所述封装衬底且电连接至所述导电元件的微电子元件的组装件之上定位承载多个迹线的例如薄片（sheet）的承载器（carrier）。在该方法中，所述定位步骤被进行，以便所述承载器的第一部分以及在所述承载器的所述第一部分之上的所述迹线的第一部分在所述微电子元件之上延伸，且所述薄片的第二部分以及在所述薄片的所述第二部分之上的所述迹线的第二部分从所述第一部分朝向所述封装衬底延伸。例如，所述承载器可以为其上具有迹线的薄片，且所述薄片可以被弯曲或者变形，这样所述承载器的第二部分从所述承载器的第一部分朝向所述封装衬底突出。
有利地，该方法也包括如下步骤：将可流动的组合物引入所述薄片与所述封装衬底之间以及所述微电子元件周围；使所述组合物固化以形成覆盖所述微电子元件且具有至少部分地由所述薄片限定的形状的包胶模。最优选地，所述方法包括：将所述迹线的所述第二部分与所述封装衬底的所述导电元件电连接。所述连接步骤可以在形成包胶模之前或者之后执行。在任一情况下，迹线的第二部分接近封装衬底方便了小连接的形成，这反过来有助于在有限尺寸的封装中提供多个迹线。
制造微电子封装的另外的方法包括：将共形介电层淀积到具有包括在所述封装衬底的下表面处暴露的底部端子的导电元件的封装衬底以及覆盖所述封装衬底的上表面且电连接至所述导电元件的微电子元件的组装件上。有利地，所述淀积步骤被进行以便所述共形层的第一部分限定远离所述封装衬底且在所述微电子元件之上延伸的顶部表面，且一个或多个另外的部分限定、向下延伸朝向被所述微电子组件覆盖的区域之外的所述封装衬底的一个或多个边缘表面。有利地，所述方法包括：将迹线和顶部端子设置在所述共形层上，以便所述迹线沿着所述顶部表面延伸且朝向所述封装衬底沿着至少一个边缘表面延伸，且所述迹线的底部部分被定位邻近所述封装衬底。有利地，所述方法进一步包括：将所述迹线的所述底部部分连接至在所述封装衬底上的至少一些所述导电元件。
附图说明
图1是在根据本发明的一个实施例的制造封装的方法中使用的部件的示意仰视平面图。
图2是图1中所描述的部件的示意正视图。
图3是描述使用图1、2中的部件的制造步骤的示意剖视图。
图4是与图3相似的示意剖视图，但是描述了在制造工艺中的稍后的阶段的所述部件和相关联的元件。
图5是与图3、4相似的示意剖视图，描述了在制造操作中稍后的阶段的所述步骤和相关联的元件。
图6是与图3-5相似的视图，但是描述了制造中再稍后的阶段。
图7是描述了在图3-6的制造工艺中所使用的封装的示意俯视平面图。
图8是沿着图7的线8-8所取的放大比例的部分剖视图。
图9是图7中所描述的封装结合另一封装的示意剖视图。
图10A是显示图9的封装的一部分的放大比例的部分剖视图。
图10B是描述根据本发明的另一实施例的封装的一部分的部分剖视图。
图11是描述根据本发明的另一实施例的制造工艺的一部分的部分剖视图。
图12是描述了在图11的工艺中所制造的封装的一部分的部分剖视图。
图13是描述了在根据本发明的又一实施例的制造工艺中的阶段的部分剖视图。
图14是描述了使用图13的工艺所制造的一部分的部分剖视图。
图15是描述根据本发明的又再一实施例的制造工艺中的阶段的部分剖视图。
图16是描述图15的工艺中所制造的封装的一部分的部分剖视图。
图17是描述根据本发明的又一实施例的制造工艺中的阶段的示意剖视图。
图18是图17的工艺中所制造的封装的剖视图。
图19是根据本发明的又再一实施例的封装的示意剖视图。
图20是根据本发明的又一实施例的封装的示意剖视图。
图21是描述根据本发明的又再一实施例的封装的示意剖视图。
图22是描述根据本发明的一个实施例的系统的示意图。
具体实施方式
在根据本发明的一个实施例的制造工艺中所利用的部件包括金属薄片30形式的承载器（carrier），例如为具有第一表面32和相对的第二表面34的铜薄片（图1、2）。第一表面32承载多个导电迹线36。该迹线形成为在薄片30的第一表面32上的导电材料细长条，所述导电材料优选地为固体金属，例如铜、金、镍及其组合。该迹线与由相似组合物的端子38一体地形成。该端子设置在薄片的第一部分40中，示意用虚线指示。该迹线从端子延伸到第二部分42。在该实施例中，第二部分42包括在第一部分40的相对侧上的区域。尽管在图1、2中只显示了一些端子38和一些迹线36，在实际中，可以有数百或者更多的端子和迹线。
端子38以“面阵”（area array）设置在第一部分40之内。如此公开中所使用，术语“面阵”指的是这样的端子阵列，其中端子基本上分散在二维区域之上，而不是集中成少数排，例如只在该区域的周边处的排或者只在该区域的中心的排。尽管在图1中显示的特定的面阵是矩形的均匀阵列，但这不是必要的。
端子和迹线可以用多种已知的金属加工方法来制造，例如通过刻蚀初始具有大于薄片30的厚度的薄片，以从由端子和迹线所占据的区域之外的区域移除金属，或者通过将端子和迹线镀到该薄片上。图1、2只描述了单个薄片，该薄片的尺寸适于制造单个封装。但是，在实际中，该薄片有利地设置成连续或者半连续的元件，所述元件包括多个部分，每个这样的部分构成如图1、2所示的薄片，这些部分彼此连续。
根据图1、2的薄片结合组装件（assemblage）46（图3）一起利用，该组装件46包括例如半导体芯片的微电子元件48，所述微电子元件48具有前表面50、后表面52、以及在前表面处暴露的触点54。组装件46也包括小电路面板形式的封装衬底，该小电路面板包括通常平面的介电结构56，该介电结构56具有顶部表面58和相对朝向的底部表面60。此处所使用的术语“顶部”和“底部”指的是所讨论的元件的参考坐标而不是正常的重力参考坐标。封装衬底56也包括：导电元件，在该示例中，导电元件包括在底部表面60上延伸的迹线62和端子64，所述端子64也在介电结构的底部表面处暴露且连接到迹线62。
组装件也包括将芯片48的触点54与封装衬底上的迹线62连接的线键合（wire bond）66。封装衬底具有孔68，孔68安置成迹线62通过孔68暴露在封装衬底的上表面处。在图3所描述的特定的实施例中，多个组装件的封装衬底设置成连续或者半连续元件，例如条、带或者薄片。这样，尽管在为了示意的简洁在图3的单独封装衬底56之间具有可见的边界，但是在实际中在该工艺的此阶段可以没有可分辨的边界。有利地，封装衬底46中的孔68被迹线62完全闭合。相似地，线键合66穿透到迹线的孔有利地完全被迹线覆盖，这样封装衬底是连续的、不可渗透的薄片。
在该方法的一个步骤中，包括多个承载器或者薄片30的元件被定位在包括封装衬底和芯片的多个组装件46的元件之上。每个承载器或者薄片30定位成使得承载迹线36和端子38的第一表面32面向封装衬底。在图3的实施例中，定位步骤包括使每个承载器薄片30从图1、2中所描述的扁平状态变形到其中每个薄片的第二部分42被弯曲出第一部分40的平面的变形状态，第二部分42沿着图2中以42’示意指示的第一表面32的方向突出。这可以由主要任何的传统成形技术来进行，例如通过使用冲压机中的匹配金属模。所成形的承载器薄片被定位在芯片和封装衬底的组装件之上，这样承载端子38的承载器薄片30（图1）的第一部分40在微电子元件或者芯片48之上延伸，且第二部分42从第一部分40朝向封装衬底46延伸。
在这种情况下，每个承载器薄片30的第二部分42限定从该薄片的第一部分40延伸的倾斜区域70，且也限定了从该倾斜区域70突出的凸缘部分74。第二部分42中的迹线沿着倾斜区域70延伸且也沿着凸缘区域74延伸。这样，该薄片的第二部分42中的这些部分的迹线36包括沿着倾斜区域70延伸的倾斜部分76和在凸缘部分74上延伸的底部部分78。
承载器薄片30定位在封装衬底46之上，迹线的底部部分78和薄片的凸缘区域74靠近封装衬底46设置。薄片上的迹线的底部部分78通过任何合适的连接（例如焊料键合80）连接到封装衬底上的迹线62。承载器薄片30上迹线的位置以及封装衬底56上的导电特征的位置可以用极好的精度进行控制。这方便了键合过程且方便了使用允许更小的迹线间隔的小直径键合的使用。
在承载器薄片上的迹线已经键合到封装衬底上的迹线之后，被组装的部分被放入模具中，这样模具的第一侧82支撑承载器薄片30，而模具的第二侧84支撑封装衬底46。尽管模具部分被描述为紧密地覆盖承载器薄片和封装衬底，在模具部分和承载器薄片30或者封装衬底46之间不需要密封结合。而是，模具部分用于物理地支撑承载器薄片和封装衬底且在如下所讨论的模制步骤期间防止这些元件的扭曲。
在下一步骤中（图4），例如环氧树脂的可流动组合物被引入到每个承载器薄片30和相关联的封装衬底46之间的空间内且围绕封装衬底上的芯片或者微电子元件48。该可流动组合物固化，以形成包胶模86（图4）。当引入可流动组合物时，该组合物接触承载器薄片且这样具有至少部分由承载器薄片所限定的形状。同样，该可流动组合物流入与迹线和端子紧密接触且部分围绕迹线和端子。但是，因为承载器薄片30与迹线（特别是端子38）的表面紧密接触，面向承载器薄片的端子的表面被完全防止与可流动组合物接触。同样，封装衬底46保护封装衬底上的端子64不受可流动组合物的污染。因为承载器薄片30和封装衬底46被提供为连续或者半连续的薄片，因此不需要模具部分在任何一个特定的承载器薄片或者封装衬底的边界处限定可流动组合物。可流动组合物可以引入到一个承载器薄片和封装衬底之间的空间内且可以流入其他承载器薄片和封装衬底之间的空间内。
在该过程的下一阶段，移除模具元件82、84，留下暴露在模制组装件的一侧上的承载器薄片30且留下暴露在相反的一侧上的该封装衬底上的端子64（图5）。在该过程的下一阶段，承载器薄片30通过例如将承载器薄片暴露给蚀刻剂而移除，该蚀刻剂对移除承载器薄片有效而让端子38和迹线36基本上保持完整。在蚀刻之后，组装件具有如图6中所示的构造。然后，组装件沿着分开线88分开，以产生单独的微电子封装90。
每个封装90（图7-9）包括封装衬底56，封装衬底56的上表面58和下表面60沿着水平方向延伸，边缘92在上表面和下表面之间延伸。封装90也具有导电元件，所述导电元件包括在下表面60处暴露的迹线62和端子64。在完成的封装中，端子64也称为“底部端子”。如参照例如端子或者迹线的导电元件此处所使用，术语在表面处“暴露”指的是，从该表面可获取导电元件。在所示的特定实施例中，底部端子64设置在下表面60上，这样底部端子从下表面稍微突出。但是，底部端子可以在下表面处暴露，即使底部端子嵌入在封装衬底56内或者设置在衬底的顶部表面58上，只要衬底中有允许获取的开口。
封装90也包括芯片形式的第一微电子元件48，这样的微电子元件被设置在封装衬底的上表面58之上并电连接到封装衬底上的导电元件、特定迹线62和底部端子64。
封装进一步包括在如上所讨论的模制工艺期间所形成的包胶模86形式的介电体，这样的介电体覆盖微电子元件48和封装衬底的至少部分的上表面。介电体或者包胶模86限定与封装衬底56远离的顶部表面94。至少一部分的顶部表面94在微电子元件48之上延伸。介电体或者包胶模86也限定从与顶部表面94邻近的顶部边沿98向下延伸到与封装衬底56相邻近且设置在封装衬底的边缘92之内的底部边沿100的第一边缘表面96。即，底部边沿100设置在由封装衬底的边缘92所限定的水平区域之内。介电体的第一边缘表面96沿着第一水平方向H1（图7、9和10A）倾斜远离微电子元件48，这样第一边缘表面的底部边沿100沿着水平方向H1距微电子元件比距顶部边沿98更远。第一边缘表面96成形为从封装衬底56以恒定的垂直距离沿着第一边缘表面延伸的任何直线在第一水平方向H1上设置在恒定的位置。例如，从封装衬底以恒定的垂直距离延伸的假想线102（图7）也将位于恒定的水平位置处。在所示的特定的实施例中，第一边缘表面基本上是平面的。
如图10A中最佳所示，介电体或者包胶模进一步限定远离封装衬底56、面向上的第一凸缘表面104。第一凸缘表面沿着第一水平方向H1远离第一边缘表面96的底部边沿100延伸。第一凸缘表面104邻近封装衬底56设置。封装衬底的第一凸缘表面104和顶部表面58之间的距离D1远小于介电体的顶部表面94和封装衬底的顶部表面58之间的距离DT。
如图7、9和10A中所示，端子38暴露在介电体的顶部表面94处。在所完成的封装中，端子94称为“顶部端子”。多个迹线36a从一些顶部端子38沿着顶部表面94延伸，且进一步横过顶部边沿96且沿着第一边缘表面96延伸。沿着第一边缘表面96延伸的这些部分的迹线大体上彼此平行。迹线包括底部部分78，所述底部部分78沿着第一凸缘表面104延伸。如此公开中所使用，迹线“沿着”表面延伸的陈述指的是，迹线靠近该表面且基本上平行于该表面延伸。在如图7、9和10A中所描述的特定的实施例中，迹线嵌入在顶部表面94、第一边缘表面96和凸缘表面104内，迹线的表面大体上与介电体或者包胶模86的表面齐平。例如，如图8中所示，迹线36a的表面与第一边缘表面96齐平。该特定的齐平设置是从如下事实获得：顶部表面94、第一边缘表面96和凸缘表面104通过承载器薄片所形成，且迹线在形成时承载在该承载器薄片的表面上。相似地，顶部端子38嵌入在介电体的顶部表面94内。所嵌入的迹线和端子可以由固态金属所形成，例如固态铜或者固态合金。典型地，固态金属提供比包括金属和粘合剂的复合物更高的导电率。迹线36a的底部部分78存在于凸缘表面104上，因为底部部分初始存在薄片的凸缘部分74上（图3）。当然，迹线的底部部分78保持连接到封装衬底的导电元件，且特别是连接到迹线62，这样迹线36a以及由此一些顶部端子38连接到一些底部端子64和连接到微电子元件48。
该封装进一步包括：第二边缘表面108，第二边缘表面108从顶部表面94向下延伸且沿着与第一水平方向H1相反的第二水平方向H2倾斜远离微电子元件48；以及第二凸缘表面110，所述第二凸缘表面110从第二边缘表面108的底部边沿沿着第二水平方向延伸。该封装进一步包括：迹线36b，所述迹线36b从一些顶部端子38沿着顶部表面94、第二边缘表面108和第二凸缘表面110延伸。这些特征与如上所述的第一边缘表面108、第二凸缘表面104和迹线36a的特征相同，除了该方向是相反的之外。迹线36b将一些顶部端子38通过封装衬底上的一些迹线62连接到一些底部端子64和微电子元件48。
在该布置中，一些或者所有的顶部端子38通过封装衬底上的导电元件连接到微电子元件或者芯片48的触点54，且一些或者所有的顶部端子38也连接到一些或者所有的底部端子64。顶部端子38以对应于底部端子64的图案布置。这样，如图9中所示，两个或者更多个封装90可以堆叠（stack；或者堆叠件）而叠置，堆叠中的底部封装90a的顶部端子连接到下一个更高的封装90b的底部端子64。堆叠的最下或者底部封装的底部端子64可以连接到更大的电路衬底114上的例如接触焊盘112的导电元件，这样整个堆叠被安装和连接到该电路面板。
焊料掩膜（未示出）可以施加在迹线36上，所述迹线36在包胶模或者介电体上延伸。相似地，焊料掩膜可以根据需要设置在封装衬底的导电特征上。这样的焊料掩膜可以任何传统的方式施加和形成图案。焊料掩膜用于限制焊料沿着迹线的表面扩展。
当然，参照图1-10A的如上所述的布置可以用许多方式进行变化。例如，诸如迹线62的导电特征被描述为位于封装衬底56的底部表面上。但是，该迹线可以设置在封装衬底的顶部表面上，或者甚至在封装衬底之内。此外，封装衬底可以包括多于一层的迹线。
在另一变型中，（图10B）如上所述的工艺的修改在于，在引入介电组合物以形成介电体之前，承载器薄片上的迹线未连接到封装衬底的导电特征。多个迹线36a沿着介电体的第一边缘表面96’延伸。迹线36’形成有沿着介电体的凸缘表面104’延伸的底部部分78’，但是在模制操作之前未连接到封装衬底56’上的例如迹线62’的导电特征。在移除承载器或者薄片（未示出）之前或者之后，通孔105被形成通过介电体的凸缘部分107，即设置在凸缘表面104’之下的部分。导体109设置在这些通孔之内且将迹线的底部部分78’连接到介电衬底56’的导电元件。在图10B中所描述的特定的实施例中，通孔从衬底的底部表面形成，且因此延伸通过所述衬底，也通过介电体或者包胶模的凸缘部分107，这样所述通孔从该封装衬底的底部表面上的迹线62’达到介电体上的迹线36’的底部部分78’。将迹线的底部部分78’定位靠近封装衬底极大地方便了通孔109的形成。换言之，凸缘表面104’和顶部表面之间的距离D1远小于封装衬底和顶部表面之间的距离DT。因此，必须由通孔所穿透的距离远小于在介电体具有在整个封装衬底之上延伸的扁平顶部表面的情况下的距离，这样整个介电体具有等于DT的厚度。这方便了对容纳相对紧密地分开的迹线所必须的相对小直径的通孔的形成。
在其他实施例中，通孔105不需要穿透封装衬底。例如，在导电元件包括在封装衬底56’的顶部表面上的迹线时，通孔可以从凸缘表面形成且只穿透介电体或者包胶模的凸缘部分107。
除了迹线236和顶部端子238承载在介电薄片230上之外，根据本发明的另一实施例的工艺（图11、12）与如上所讨论的工艺相似。介电薄片以与上述相似的方式被变形且定位在封装衬底256和微电子元件248的组装件之上。这样，承载器的第一部分240和迹线236的对应第一部分在微电子元件之上延伸，而承载器薄片的第二部分242和位于第二部分242上的这些部分的迹线236从第一部分240朝向封装衬底256延伸。再次地，在薄片和封装衬底之间以及微电子元件的周围引入可流动组合物并固化，以形成覆盖微电子元件并具有至少部分由薄片230所限定的形状的介电体或者包胶模286。此处再次地，介电体或者包胶模包括凸缘表面204和位于凸缘表面之下的凸缘部分。迹线236的部分278覆盖凸缘部分，且因而与封装衬底相邻设置且设置在比顶部端子238和所述迹线的相邻部分更靠近封装衬底的距离处。在该实施例中，在引入介电组合物之前，迹线的底部部分278未连接到封装衬底的导电特征。而是，通过介电体的凸缘部分和通过薄片230的对应部分形成通孔，且通孔导体209形成在这些通孔之内，以将迹线的底部部分278连接到例如迹线262的封装衬底的导电元件。
也在该实施例中，可以在薄片和封装衬底保留成连续的或者半连续的薄片或者带时，执行处理该薄片和模制该介电体的工艺，所述薄片或者带具有形成多个单独封装的元件。该封装可以在形成通孔和通孔导体209之前或者之后彼此分离。
如图12中所描述完成的封装包括部分的薄片230作为封装结构的一部分。有利地，薄片230粘接到介电体286。为了该目的，薄片230可以包括在表面231上的粘合剂，所述表面231在模制工艺其间朝向封装衬底。这样，介电薄片230形成靠近地覆盖介电体286且在最终的产品中粘接到该介电体286的一层。在其他实施例中，可流动介电材料本身可以用作将所形成的介电体粘接到该薄片的粘合剂。只是通过示例，该薄片可以包括通常用在柔性印刷电路板中的材料，例如聚酰亚胺和BT树脂。同样，在对薄片进行变形之前，焊料掩膜（未示出）可以施加在薄片上的迹线之上，只要该焊料掩膜可以承受在模制工艺其间所使用的温度和压力。
根据本发明的另一实施例的工艺（图13）使用一对模制元件382和384来形成介电体386。在该工艺中，在模制时，不存在承载器和迹线。介电体具有与如上所述的相似的构造，且再次地包括限定凸缘表面304的凸缘部分307以及顶部表面394和一个或者多个边缘表面396。此处再次地，边缘表面从顶部表面394处的顶部边沿延伸到设置在封装衬底356的区域之内的底部边沿398。如上所述，当封装衬底356从更大的薄片或者带分离时，封装衬底的边沿394可以在模制步骤之后被限定。
在模制工艺之后，承载迹线336和顶部端子338的薄片330施加在介电体的顶部表面394和边缘表面396和凸缘表面304之上。此处再次地，迹线的底部部分与封装衬底356相邻设置，这样通孔很容易通过介电体或者包胶模的相对薄的凸缘部分307形成。通孔导体309设置在通孔内并将薄片上的迹线336电连接到封装衬底的导电元件362。在如图14中所示的特定实施例中，薄片330通过粘合剂301薄层粘接到介电体。同样，该薄片承载焊料掩膜层303。
根据另一实施例的工艺使用与如上所述相似的组装件446，除了微电子元件或者芯片448相对于封装衬底456定位在“向下”的取向。封装衬底包括导电元件，所述导电元件包括在封装衬底的上表面上的迹线463、封装衬底的下表面上的额外迹线462、底部端子464和通过将上表面迹线463与下表面迹线和底部端子连接的导体465。微电子元件或者芯片448的触点454例如通过焊料键合（solder bond）而键合到上表面导电元件463。介电体或者包胶模486使用与如上所述参照图13的模具元件相似的模具元件来形成，且具有相似的构造。从面向上的凸缘表面404到上表面导电元件463，通孔405被形成通过介电体的凸缘部分。通孔405可以在模制工艺期间形成，例如通过与上表面导电元件结合的模具上的凸起或者突起。可选地，通孔405可以在模制之后通过例如激光烧蚀、蚀刻、喷砂等形成。在另一可选中，通孔463可以部分通过模具的特征、部分通过后模具工艺来形成。在形成介电体或者包胶模486和通孔405之后，承载迹线436和顶部端子438的介电薄片430使用粘合层（未示出）被安装在介电体上。在该实施例中，薄片430在朝向介电体的薄片的表面上承载迹线436。这样，端子438通过薄片中的开口439暴露在该介电体的顶部表面494处。这些开口可以在薄片430组装到包胶模之前或者之后来形成。迹线436的底部部分478通过设置在通孔404之内的键合（bond）409而键合到封装衬底456的上表面导电元件463。只是通过示例，这样的键合可以通过钎焊、共晶键合、热超声键合等来形成。键合材料可以承载在迹线436上或者可以淀积到通孔内。此处再次地，迹线底部部分478靠近封装衬底方便了键合工艺和使用小的键合，这反过来允许迹线底部部分的更紧密的间隔。多种迹线可以容纳在所述结构上。如图15、16中所示的类型的封装衬底和微电子元件可以在如上所述的工艺和结构中使用。同样，在面向封装衬底的侧面上具有迹线的介电薄片430可以在与图11、12相似的工艺中使用，在图11、12中薄片放入到模具中且介电体通过与薄片接触成形。在这种情况下，开口439有利地在模制工艺之后形成。
根据本发明的另一实施例的工艺（图17、18）在组装件546上形成介电体，与如上参照图15、16所讨论的组装件相似的是，所述组装件546具有面向下取向的微电子元件，触点554面向封装衬底556，这样触点结合到封装衬底556上的导电元件。此处再次地，组装件包括承载在封装衬底556的下表面上的底部端子564。图17中所描述的特定的组装件包括设置在微电子元件或者芯片548和封装衬底上表面之间的空间内的底部填充（或者底部填充剂；underfill）501。该底部填充有利地围绕微电子元件和封装衬底的导电元件之间的连接（或者连接件，connection）503。
在该工艺中使用具有第一表面507和第二表面509的共形介电层505。当共形层施加到组装件546时，共形层下陷与封装衬底556的上表面558、微电子元件548的被暴露表面以及底部填充501接触。这样，在共形层施加到组装件时，共形层必须足有足够的软度和可变形性以在该方式中顺应。只是为了示例，共形层可以为“B-级”或者部分固化环氧树脂组合物，这可以可选地包含微粒填充材料。在施加之后，共形层可以通过例如化学反应而硬化。当共形层变形以覆盖组装件546的被暴露元件时，共形层的第一部分限定远离封装衬底556且在微电子元件548之上延伸的顶部表面594（图18），而共形层的额外部分限定在由微电子元件548所覆盖的区域之外的封装衬底的区域内向下朝向封装衬底延伸的边缘表面596。
在施加和固化共形层之后，迹线536和顶部端子538形成在固化层上。例如，整个共形层可以被电镀、掩膜以及选择性蚀刻以形成顶部端子和迹线。可选地，共形层的表面可以覆盖有掩膜材料，然后选择性地暴露给激光辐射以切出通过该掩膜的槽。籽晶层可以施加在掩膜之上且施加到所述槽内，由此掩膜被移除以卸下（lift off）除了所述槽处的任何地方的籽晶层。然后该表面暴露给镀液，这样金属只淀积在存在籽晶的槽处。可以使用用于在介电体上形成金属特征的任何其他技术。此处再次地，顶部端子暴露在顶部表面594上且迹线536从至少一些顶部端子沿着顶部表面594延伸且也向下朝向封装表面556沿着边缘表面596延伸。也在该实施例中，迹线的底部部分578设置在离封装衬底距离D578处，所述距离D578小于封装衬底和顶部表面594之间的距离D594，且因此小于封装衬底和端子538之间的距离。此处再次地，高度的不同方便将底部部分连接到封装衬底的导电元件。在图18的特定实施例中，共形层形成限定凸缘表面504的凸缘部分507，迹线的底部部分578沿着凸缘表面延伸。底部部分通过形成通过凸缘部分的通孔且将通孔导体509淀积在这些通孔内而连接到衬底的导电元件。
如同上述讨论的其他工艺，可使用具有相同的封装衬底的、形成为大薄片的许多组装件的组装件、使用具有用于多个封装的迹线和端子的连续或者半连续共形层，而进行施加共形层的工艺。该组装件在施加共形层之后彼此分离。
必须理解的是，附图不是成比例的。例如，微电子元件548和共形层本身的垂直尺寸为了说明清楚极大地进行了夸张。实际中，从封装衬底到顶部表面和顶部端子的高度或者距离D594可以是几百微米或者更小的数量级，通常大约400微米或者更小，而迹线的底部部分548在封装衬底之上设置在更小的高度D578。共形层形成封装的介电体。就此而言，术语“介电体”并非隐含任何特定的最小厚度或者形状。
在参照附图17、18的如上所述的工艺的变型中，共形层施加到组装件546，迹线536和顶部触点538元件已经在共形层上就位。例如，共形层本身可以包括多个子层，例如承载顶部触点和端子的柔性顶层和例如B-级（B-stage）环氧树脂的共形底层。
可以利用如上所述的特征的多种另外的变型和组合。只是为了示例，介电体可以具有一个、两个、或者多于两个的边缘表面，迹线在边缘表面上延伸。同样，该封装可以包括多于一个的微电子元件。只是为了示例，在图19中所描述的封装与参照图1-10A在上述讨论的封装相似，但是在介电体786中包括了两个微电子元件748。
根据本发明的另一实施例的封装（图20）包括通常与参照图9-10A和10B所如上描述的封装的对应元件相似的微电子元件848和封装衬底856。也在该实施例中，微电子元件848电连接到封装衬底856上的导电元件且被第一介电体886覆盖。此处再次地，该介电体限定顶部表面894和从顶部表面894朝向封装衬底延伸的第一边缘表面896。介电体也包括在第一水平方向H1上向外突出（至图20中的右边）的凸缘部分804。
但是，在图20的实施例中，衬底856延伸超出凸缘部分804。辅助介电体847设置在封装衬底的该突出部分上。辅助介电体847限定与第一介电体886的顶部表面894共面的顶部表面897。辅助介电体也限定从顶部表面897朝向封装衬底向下延伸的边缘表面895。边缘表面895在与第一水平方向相反的第二水平方向H2上倾斜，这样第一介电体886的第一边缘表面896和辅助介电体897的边缘表面895沿着向下的方向朝向封装衬底856彼此会聚。这些边缘表面协作地限定从顶部表面894、897向下延伸的沟道。该沟道和边缘表面是延伸到和延伸出如图20中所示的附图的平面的细长结构。辅助介电体897限定从边缘表面895的底部边沿朝向微电子元件848向内突出的凸缘区域803。凸缘区域803与第一介电体886的凸缘区域804合并。必须理解的是，尽管这些介电体和部分单独地进行了描述，实际上这些介电体和部分是单个介电主体的部分。
如同在上述的实施例中，顶部端子838在第一介电体886的顶部表面894处暴露。连接到至少一些的顶部端子的迹线836沿着介电体886的第一边缘表面896延伸且具有连接到封装衬底的导电元件的底部部分。但是，在图20的实施例中，辅助顶部端子837在辅助介电体847的顶部表面897处暴露。迹线833从至少一些的该辅助顶部端子沿着辅助介电体的顶部表面897和沿着辅助介电体847的倾斜边缘表面895延伸。与封装衬底856相邻设置的迹线833的底部部分也连接到封装衬底的导电元件。在如上所讨论的实施例中，封装衬底限定了与第一介电体886对齐以及与由第一介电体所承载的顶部端子838对齐的底部端子阵列。在图20的实施例中，封装衬底也限定了承载在辅助介电体847上的与辅助顶部端子837对齐的辅助底部端子857。
在该实施例中，第一介电体886也具有在第二水平方向H2上倾斜的第二边缘表面808，且一些迹线836从一些顶部端子838沿着第二边缘表面808延伸。介电体包括在该介电体的顶部表面处暴露的辅助顶部端子811的第二辅助体809，且具有从所述第二辅助体的顶部表面向下延伸且在第一水平方向H1上倾斜的边缘表面813，这样边缘表面813与第一介电体886的第二边缘表面808会聚。这些边缘表面协作地限定延伸到如图20中所示的附图的平面内和离开所述平面的另一细长沟道。另外的辅助迹线815沿着另外的辅助体809的边缘表面延伸。这些迹线连接到封装衬底856的导电元件。该封装衬底限定与该另外的辅助顶部端子811对齐的另外的辅助底部端子817。辅助体809限定与第一介电体886的第二边缘表面808的底部处的凸缘区域会聚的凸缘区域。此处再次地，该另外的辅助体808和第一介电体886形成单一的介电体的一部分。
每个辅助介电体可以承载一排或者多于一排的顶部触点811、837。这些顶部触点和与这些顶部触点对齐的辅助底部触点857、817在封装的堆叠中提供了信号的额外连接和额外路由。如图20中所示的封装可以一个叠置在另一个上，辅助顶部触点与堆叠中的下一个更高的封装的辅助底部触点对齐。第一介电体的顶部触点838与堆叠中下一个更高封装的底部触点864对齐。
如图20中所描述的封装可以通过主要与如上所述的相同的方法来制造，且可以包括如上所述的特征。只是为了示例，用于形成封装的薄片或者承载器未出现在如图21中所描述的最终的封装中。但是，具有辅助介电体的封装可以包括例如如上参照图11、12和16所讨论的介电薄片的特征。在又一变型中，一个或者更多个微电子元件可以设置在一个或者更多个辅助体之内。
根据本发明的另一实施例的封装（图21）与图20的封装相似在于，图21的封装包括具有第一边缘表面696和第二边缘表面608的第一或者主介电体686。该封装进一步包括具有与第一介电体686的第一边缘表面696会聚的倾斜边缘表面695的第一辅助介电体647以及具有与第一介电体686的第二边缘表面608会聚的倾斜边缘表面613的第二辅助介电体。此处再次地，辅助顶部触点637和611设置在辅助介电体上，且辅助底部触点617和657设置在封装衬底的底部表面上，用于增加连通性。但是，图21的封装中的介电体不包括凸缘表面。这样，边缘表面696、608、695和613一直延伸到封装衬底656的上表面658。迹线沿着该边缘表面向下延伸，这样每个迹线的底部部分在该边缘表面的底部处终止，在该底部处该迹线结合到封装衬底的上表面上的导电元件663。
在另一变型中，用于保持迹线和顶部端子的承载器可以是除了薄片之外的元件。例如，迹线和端子可以淀积在模具元件上，所述模具元件然后被用于形成介电体的顶部表面和边缘表面。当移除模具时，以与如上参照图1-10A所讨论相同的方式，顶部端子和迹线保持嵌入在介电体内。
如上讨论的封装可以用于不同的电子系统的构造中。例如，根据本发明的另一实施例的系统900（图22）包括如上结合包括如上所述的两个封装的堆叠以及结合其他电子部件908和910所述的第一封装902。在所描述的示例中，部件908是半导体芯片，而部件910是显示屏，但是可以使用任何其他的部件。当然，尽管为了显示清楚在图22中只描述了两个额外的部件，但是，该系统可以包括任何数目的这样的部件。封装902和904以及部件908和910安装到如图中虚线示意描述的共同壳体901，且根据需要彼此电互连，以形成所需的电路。在所示的示例系统中，该系统包括例如柔性或者刚性印刷电路板的电路面板907，且电路面板包括将所述部件彼此互连的多个导体909，其中只有一个导体909在图22中进行了描述。外接（off-board）连接器911将部件910连接到电路面板。但是，这只是示意的，可以使用用于制造电连接的任何合适结构。壳体901描述为例如在手机或者个人数字助理中可使用的便携式壳体，且屏910在壳体的表面处暴露。再次地，如图22中所示的简化系统只是示例性的，包括通常视为固定结构的系统（例如台式计算机、路由器等）的其他系统可使用如上所讨论的封装来制造。
在不背离本发明的情况下可以利用如上所述的特征的这些和其他变型或者组合，本优选实施例的前述说明只是为了说明的目的，而不能认为是由权利要求所限定的本发明来进行限制。
工业实用性
本发明享有广泛的工业应用性，包括但是不限于提供用于微电子元件的封装的组件和方法。

Claims (12)

1.一种制造微电子封装的方法，包括以下步骤：
（a）在具有导电元件的封装衬底以及覆盖所述封装衬底且电连接至所述导电元件的微电子元件的组装件之上定位承载多个迹线的薄片，这样至少一些所述迹线中的部分在所述微电子元件之上延伸；
（b）将可流动的组合物引入所述薄片与所述封装衬底之间以及所述微电子元件周围，且使所述组合物固化以形成覆盖所述微电子元件且具有至少部分地由所述薄片限定的形状的包胶模；和
（c）去除所述薄片，以便留下在所述包胶模的背朝所述封装衬底的一个或多个表面之上延伸的所述迹线，
其中所述定位所述薄片的步骤包括：
定位在所述微电子元件之上延伸的所述薄片的第一部分以及在所述薄片的所述第一部分之上的所述迹线的第一部分，以及定位所述薄片的第二部分，这样所述薄片的所述第二部分以及在所述薄片的所述第二部分上的所述迹线的第二部分从所述薄片的所述第一部分朝向所述封装衬底延伸。
2.根据权利要求1所述的方法，其中，所述定位步骤包括：
使所述薄片变形。
3.根据权利要求1所述的方法，其中，所述定位步骤被进行以便承载所述迹线的所述薄片的表面朝向所述封装衬底，且所述引入步骤被进行以便所述可流动的组合物部分地围绕所述迹线。
4.根据权利要求3所述的方法，其中，所述薄片由金属材料形成，且所述去除所述薄片的步骤包括：刻蚀所述薄片的所述金属材料。
5.一种制造微电子封装的方法，包括以下步骤：
（a）在具有导电元件的封装衬底以及覆盖所述封装衬底且电连接至所述导电元件的微电子元件的组装件之上定位承载多个迹线的薄片，所述定位步骤被进行以便所述薄片的第一部分以及在所述薄片的所述第一部分之上的所述迹线的第一部分在所述微电子元件之上延伸且所述薄片的第二部分以及在所述薄片的所述第二部分之上的所述迹线的第二部分从所述第一部分朝向所述封装衬底延伸；
（b）将可流动的组合物引入所述薄片与所述封装衬底之间以及所述微电子元件周围；
（c）使所述组合物固化以形成覆盖所述微电子元件且具有至少部分地由所述薄片限定的形状的包胶模；和
（d）将所述迹线的所述第二部分与所述封装衬底的所述导电元件电连接。
6.根据权利要求5所述的方法，其中，在引入所述可流动的组合物的步骤之前进行所述将所述迹线的所述第二部分与所述导电元件电连接的步骤。
7.根据权利要求5所述的方法，其中，所述定位所述薄片以及引入和固化所述可流动的组合物的步骤被进行，以便所述包胶模包括限定在所述微电子元件之上延伸的顶部表面的主要部分、以所述主要部分为界且朝向所述微电子元件向下延伸的第一边缘表面以及从所述第一边缘表面向下延伸且比所述主要部分更薄的凸缘部分，且这样所述迹线的所述第二部分包括在所述凸缘部分之上延伸的底部部分，所述电连接所述第二部分的步骤包括：形成通过所述包胶模的所述凸缘部分的连接件。
8.根据权利要求7所述的方法，进一步包括以下步骤：
形成在所述迹线的所述底部部分与所述封装衬底之间延伸的、在所述包胶模的所述凸缘部分内的通孔，所述形成通过所述凸缘部分的连接的步骤包括：在所述通孔内形成通孔导体。
9.根据权利要求8所述的方法，其中，在所述引入和固化所述组合物之后进行在所述包胶模的所述凸缘部分内形成通孔的步骤。
10.一种制造微电子封装的方法，包括以下步骤：
（a）将共形介电层淀积到具有包括在所述封装衬底的下表面处暴露的底部端子的导电元件的封装衬底以及覆盖所述封装衬底的上表面且电连接至所述导电元件的微电子元件的组装件上，所述淀积步骤被进行以便所述共形层的第一部分限定远离所述封装衬底且在所述微电子元件之上延伸的顶部表面，且一个或多个另外的部分限定、向下延伸朝向被所述微电子组件覆盖的区域之外的所述封装衬底的一个或多个边缘表面；和
（b）将迹线和顶部端子设置在所述共形层上，以便所述迹线沿着所述顶部表面延伸且朝向所述封装衬底沿着至少一个边缘表面延伸，且所述迹线的底部部分被定位邻近所述封装衬底；和
（c）将所述迹线的所述底部部分连接至在所述封装衬底上的至少一些所述导电元件，
其中所述淀积共形层的步骤被进行以便所述共形层形成从至少一个边缘表面的底部边沿延伸的至少一个朝上的凸缘表面，这样每个凸缘表面被设置为距离所述封装衬底的垂直距离小于所述封装衬底与所述顶部表面之间的垂直距离，所述设置迹线的步骤被进行，这样所述迹线的所述底部部分在所述至少一个凸缘表面之上延伸，且所述连接所述迹线的所述底部部分的步骤包括：形成连接，这样所述连接延伸通过所述至少一个凸缘表面。
11.根据权利要求10所述的方法，其中，所述设置迹线和端子的步骤包括：
在将所述层淀积到所述组装件上之前，将所述迹线和所述端子设置在所述共形层之上。
12.根据权利要求11所述的方法，其中，所述设置迹线和端子的步骤包括：
在将所述层淀积到所述组装件上之后，将所述迹线淀积到所述共形层上。
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