CN103311214A - Base plate for stacked packaging - Google Patents
Base plate for stacked packaging Download PDFInfo
- Publication number
- CN103311214A CN103311214A CN2013101763689A CN201310176368A CN103311214A CN 103311214 A CN103311214 A CN 103311214A CN 2013101763689 A CN2013101763689 A CN 2013101763689A CN 201310176368 A CN201310176368 A CN 201310176368A CN 103311214 A CN103311214 A CN 103311214A
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- China
- Prior art keywords
- substrate
- stacked package
- cavity
- base plate
- dam
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a base plate for stacked packaging. The surface of the base plate comprises more than one concave cavity. According to the base plate for stacked packaging provided by the invention, concave cavities are arranged on one side or both sides of the base plate, and the cavities are used for assembling chips. A certain difference in heights of the interior of each cavity and the edge of the base plate exists, interconnection solder balls are arranged on the edge of the base plate, and the interconnection solder balls with narrow pitches and small diameters can be allowed to be adopted, so that the interconnection density between two layers of packaging units can be improved.
Description
Technical field
The present invention relates to the technical field of stacked package in the three-dimension packaging, particularly for the substrate of stacked package.
Background technology
Three-dimension packaging as a kind of consumer electronics of complying with towards high integration, multifunction, the packing forms of miniaturization development has obtained deep research, chip-stacked technology (stacked die) has appearred, stacked package technology (package-on-package, PoP), built-in encapsulation technology (package-in-package, PiP), silicon through hole (through silicon via, the multiple way of realization such as TSV), three-dimension packaging can the Effective Raise packaging density, save the assembling space on the PCB, can satisfy the consumer electronics apparent size and change integrated multi-purpose requirement in the little situation.Thereby stacked package is carried out the stacking new encapsulation integral body that forms in vertical direction by lower floor's encapsulation unit and upper strata encapsulation unit, relatively independent between each encapsulation unit, can test separately its levels packaging simultaneously, satisfy known good chip (know good die, KGD) demand has higher device package yields, can significantly reduce cost, and reliability is high, therefore uses very wide in three-dimension packaging.
The stacked package technology is quite ripe through the development in nearly ten years, traditional stacked package is by the mode that soldered ball interconnects the upper strata encapsulation to be encapsulated with lower floor to be stacked in vertical direction, but because lower floor is packaged with certain height, therefore diameter and the pitch of the interconnection soldered ball between the levels encapsulation are restricted, and also the number of pins of whole stacked package body, integral thickness etc. have been brought impact.In order to improve the interconnection density between the levels encapsulation, people have carried out a large amount of research, have also designed many novel structures.US Patent No. 20080157326 has increased one deck intermediary layer and has improved interconnection density between the levels encapsulation, increase intermediary layer and increased accordingly process complexity, also easily goes wrong aspect reliability, and cost is higher; A kind of lower floor's encapsulating structures that adopt metal interconnected post of proposition such as Japan M.Ishihara, improve interconnection density by the diameter of controlling metal interconnected post, and than the higher reliability of traditional soldered ball, but the hot matching problem of metal interconnected post and plastic packaging material, highly control etc. and to have increased equally the cost that encapsulates.In addition, U.S. Amkor company has invented and has crossed the mould through-hole structure, but because the interconnecting metal post is arranged in the plastic packaging hole, is difficult to adapt to traditional Rework Technics when increasing technology difficulty.Therefore the method that needs the new increase stacked package interconnection density of research is to overcome the problem of front.
Summary of the invention
Technical problem to be solved by this invention provides a kind of substrate for stacked package, has solved in traditional stacked package the limited problem of interconnection density between the levels encapsulation.
For solving the problems of the technologies described above, the invention provides a kind of substrate for stacked package, the surface of described substrate comprises the cavity of depression, and described cavity comprises more than one.
Further, described cavity is arranged on the one or both sides of described substrate.
Further, described cavity is used for assembling chip.
Further, described cavity comprises the dam of sealing or the dam that does not seal, and described dam is the edge of described cavity.
Further, be provided with the interconnection soldered ball on the described dam.
Further, described substrate comprises organic substrate or ceramic substrate.
Further, the exponent number of described cavity comprises more than the single order.
Further, described substrate can obtain the individual layer encapsulation unit in the stacked package after chipset installs into.
Further, described individual layer encapsulation unit can carry out two-layer above stacking.
Substrate for stacked package provided by the invention is provided with the cavity of depression in the one or both sides of substrate, this cavity is used for assembling chip.Because there are certain difference in height in inside cavity and substrate edges, the interconnection soldered ball arranges on the substrate edges, can allow to adopt the interconnection soldered ball of narrow pitch, minor diameter, thereby can improve the interconnection density between the two-layer encapsulation unit.
Description of drawings
Fig. 1 is the board structure schematic diagram that substrate one side that is used for stacked package that the embodiment of the invention provides has the single order cavity;
Fig. 2 is the board structure schematic diagram that all there is the single order cavity substrate both sides that are used for stacked package that the embodiment of the invention provides;
Fig. 3 is the board structure schematic diagram that substrate one side that is used for stacked package that the embodiment of the invention provides has the second order cavity;
Fig. 4 is the board structure schematic diagram under the substrate dam sealing situation that is used for stacked package that provides of the embodiment of the invention;
Fig. 5 is as the structural representation of stacked package upper strata encapsulation unit after the substrate chips assembling that is used for stacked package that the embodiment of the invention provides is finished;
Fig. 6 is as the structural representation of stacked package lower floor encapsulation unit after the substrate chips assembling that is used for stacked package that the embodiment of the invention provides is finished;
Fig. 7 is the substrate 2 layer laminate encapsulation that is used for stacked package that the embodiment of the invention provides;
Fig. 8 is the substrate 3 layer laminate encapsulation that is used for stacked package that the embodiment of the invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, mainly there is the substrate of single order cavity as example the technical scheme in the embodiment of the invention to be carried out clear, complete expression take a side, described embodiment only is a part of embodiment of the present invention.
Fig. 1 to 3 is several versions of substrate that are used for stacked package that the embodiment of the invention provides, and is respectively that substrate one side has the single order cavity successively, and both sides all have single order cavity and a side that the second order cavity is arranged.Fig. 4 is the board structure schematic diagram under the substrate dam sealing situation that is used for stacked package that provides of the embodiment of the invention.
The substrate that is used for stacked package that the embodiment of the invention provides can be organic substrate or ceramic substrate, is provided with the cavity of depression in the substrate one or both sides, and this cavity is used for assembling chip.Substrate comprises pad 10 on loading plate 1, dam 2, substrate internal wiring 3, chipset welding equipment dish 4, interconnect pad 9 and the loading plate, total is realized by substrate process, be an integral body, the distribution of the size of various piece, internal wiring and substrate surface pad etc. are according to the difference of assembling chip and difference.
With reference to figure 5, chipset welding equipment dish 4 is distributed in the substrate both sides, and by interconnect pad 4, chip 1 and chip 27 can be assembled on the substrate 1.Packaging technology is traditional flip chip bonding or routing technique, and the conditions such as required temperature, time of assembling are determined according to the material of the BGA ball material of chip self or required metal wire and diameter etc.
Assembling sequence generally is first assembling chip 27 and does plastic packaging protection 8, then assembling chip 1 and do plastic packaging protection 6.After chipset installs into, on interconnect pad 9, plant ball technique with routine and plant interconnection soldered ball 11, plant the process conditions such as the required reflux temperature of ball, time and determine according to the material of interconnection soldered ball 11.Can obtain at the middle and upper levels individual layer encapsulation unit of stacked package after above step is finished, can be assembled on other packaging bodies by interconnection soldered ball 11, realize stacked package.
With reference to figure 6; interconnect pad 9 and interconnect pad 10 are distributed in the substrate both sides; the processing steps such as chip assembling, plastic packaging protection and embodiment one are in like manner; plant interconnection soldered ball 11 at interconnect pad 9; can obtain the lower floor's encapsulation unit in the stacked package; other packaging bodies can be assembled on it by interconnect pad 10, realize stacked package.
With reference to figure 7 and 9, the processing step of individual layer encapsulation unit and embodiment two in like manner, the individual layer encapsulation unit of a plurality of this structures carries out stacking in vertical direction, can realize 2 layers, 3 layers and more multi-layered stacked package.
The substrate that is used for stacked package that the embodiment of the invention provides, the single order that there is depression a side of this substrate or both sides or multistage cavity; The dam that surrounds cavity can seal, and also can be not seal, and is distributed with interconnect pad on the dam in order to the adjacent two-layer encapsulation unit that interconnects; The technique assembling chips such as flip chip bonding, routing can be used in the substrate both sides, and the chip of every side can be monolayer distribution, also can be that lamination distributes; Chip assembling and carry out the plastic packaging protection after can obtain individual layer encapsulation unit in the stacked package; The individual layer encapsulation unit that a plurality of this structures obtain carries out stacking on the vertical direction, can realize multilayer laminated encapsulating structure.Since inside cavity with have certain difference in height as the dam of substrate edges, the interconnection soldered ball arranges on the dam, can allow to adopt the interconnection soldered ball of narrow pitch, minor diameter, thereby can improve the interconnection density between the two-layer encapsulation unit.Because the dam is the part of whole substrate, and one is finished when substrate manufacture, can not increase extra processing step during encapsulation, and cost is low, reliability is high simultaneously.In addition, interconnection between the stacked package different layers chip can be finished and needn't finish by motherboard at this laminar substrate, thereby increase effective input/output port of whole stacked package body, the encapsulation unit of a plurality of this structures carries out the stacked package of stacking easy realization more than 2 layers in vertical direction.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to example the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (9)
1. a substrate that is used for stacked package is characterized in that, the surface of described substrate comprises the cavity of depression, and described cavity comprises more than one.
2. substrate as claimed in claim 1 is characterized in that, described cavity is arranged on the one or both sides of described substrate.
3. substrate as claimed in claim 1 is characterized in that, described cavity is used for assembling chip.
4. such as each described substrate of claims 1 to 3, it is characterized in that, described cavity comprises the dam of sealing or the dam that does not seal, and described dam is the edge of described cavity.
5. substrate as claimed in claim 4 is characterized in that, is provided with the interconnection soldered ball on the described dam.
6. substrate as claimed in claim 5 is characterized in that, described substrate comprises organic substrate or ceramic substrate.
7. substrate as claimed in claim 5 is characterized in that, the exponent number of described cavity comprises more than the single order.
8. substrate as claimed in claim 5 is characterized in that, described substrate can obtain the individual layer encapsulation unit in the stacked package after chipset installs into.
9. substrate as claimed in claim 8 is characterized in that, described individual layer encapsulation unit can carry out two-layer above stacking.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101763689A CN103311214A (en) | 2013-05-14 | 2013-05-14 | Base plate for stacked packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013101763689A CN103311214A (en) | 2013-05-14 | 2013-05-14 | Base plate for stacked packaging |
Publications (1)
| Publication Number | Publication Date |
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| CN103311214A true CN103311214A (en) | 2013-09-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013101763689A Pending CN103311214A (en) | 2013-05-14 | 2013-05-14 | Base plate for stacked packaging |
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| Country | Link |
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| CN (1) | CN103311214A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017024854A1 (en) * | 2015-08-13 | 2017-02-16 | 上海航天电子通讯设备研究所 | Vertical interconnection structure for three-dimensional package based on aluminium substrates and preparation method therefor |
| CN108428672A (en) * | 2018-04-17 | 2018-08-21 | 中国电子科技集团公司第二十九研究所 | The two-sided three-dimensionally integrated framework of ceramics and packaging method of ultra-wide band radio-frequency micro-system |
| WO2019024813A1 (en) * | 2017-07-31 | 2019-02-07 | 华为技术有限公司 | Embedded substrate |
| CN111816577A (en) * | 2020-05-15 | 2020-10-23 | 甬矽电子(宁波)股份有限公司 | Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5043794A (en) * | 1990-09-24 | 1991-08-27 | At&T Bell Laboratories | Integrated circuit package and compact assemblies thereof |
| US5838060A (en) * | 1995-12-12 | 1998-11-17 | Comer; Alan E. | Stacked assemblies of semiconductor packages containing programmable interconnect |
| US6172423B1 (en) * | 1997-11-15 | 2001-01-09 | Hyundai Electronics Industries Co., Ltd. | Layer-type ball grid array semiconductor package and fabrication method thereof |
| US20020047214A1 (en) * | 2000-10-16 | 2002-04-25 | Yuichi Morinaga | Multi-chip package-type semiconductor device |
| CN101159259A (en) * | 2007-11-09 | 2008-04-09 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional multiple chips packaging module and preparation method |
| CN101436571A (en) * | 2007-11-16 | 2009-05-20 | 英飞凌科技股份有限公司 | Electrical device and method |
-
2013
- 2013-05-14 CN CN2013101763689A patent/CN103311214A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5043794A (en) * | 1990-09-24 | 1991-08-27 | At&T Bell Laboratories | Integrated circuit package and compact assemblies thereof |
| US5838060A (en) * | 1995-12-12 | 1998-11-17 | Comer; Alan E. | Stacked assemblies of semiconductor packages containing programmable interconnect |
| US6172423B1 (en) * | 1997-11-15 | 2001-01-09 | Hyundai Electronics Industries Co., Ltd. | Layer-type ball grid array semiconductor package and fabrication method thereof |
| US20020047214A1 (en) * | 2000-10-16 | 2002-04-25 | Yuichi Morinaga | Multi-chip package-type semiconductor device |
| CN101159259A (en) * | 2007-11-09 | 2008-04-09 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional multiple chips packaging module and preparation method |
| CN101436571A (en) * | 2007-11-16 | 2009-05-20 | 英飞凌科技股份有限公司 | Electrical device and method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017024854A1 (en) * | 2015-08-13 | 2017-02-16 | 上海航天电子通讯设备研究所 | Vertical interconnection structure for three-dimensional package based on aluminium substrates and preparation method therefor |
| WO2019024813A1 (en) * | 2017-07-31 | 2019-02-07 | 华为技术有限公司 | Embedded substrate |
| CN108428672A (en) * | 2018-04-17 | 2018-08-21 | 中国电子科技集团公司第二十九研究所 | The two-sided three-dimensionally integrated framework of ceramics and packaging method of ultra-wide band radio-frequency micro-system |
| CN111816577A (en) * | 2020-05-15 | 2020-10-23 | 甬矽电子(宁波)股份有限公司 | Method for packaging chip on double sides of substrate and structure of chip packaged on double sides of substrate |
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| ASS | Succession or assignment of patent right |
Owner name: NATIONAL CENTER FOR ADVANCED PACKAGING Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20150228 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: 100029 CHAOYANG, BEIJING TO: 214135 WUXI, JIANGSU PROVINCE |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20150228 Address after: Taihu international science and Technology Park in Jiangsu province Wuxi City Linghu road 214135 Wuxi national hi tech Industrial Development Zone No. 200 Chinese Sensor Network International Innovation Park building D1 Applicant after: National Center for Advanced Packaging Co., Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Applicant before: Institute of Microelectronics, Chinese Academy of Sciences |
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Application publication date: 20130918 |
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