CN103311192A - Thin-gap POP (Package on Package) type packaging structure and packaging method - Google Patents
Thin-gap POP (Package on Package) type packaging structure and packaging method Download PDFInfo
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- CN103311192A CN103311192A CN2013102569775A CN201310256977A CN103311192A CN 103311192 A CN103311192 A CN 103311192A CN 2013102569775 A CN2013102569775 A CN 2013102569775A CN 201310256977 A CN201310256977 A CN 201310256977A CN 103311192 A CN103311192 A CN 103311192A
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- infrabasal plate
- packaging body
- chip
- solder ball
- base plate
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Abstract
The invention discloses a thin-gap POP (Package on Package) type packaging structure and packaging method. The thin-gap POP type packaging structure comprises an upper packaging body and a lower packaging body which are connected with each other; a base plate of the upper packaging body is an upper base plate; a base plate of the lower packaging body is a lower base plate; solder balls are planted in a certain area of the lower base plate; the solder balls and the upper surface of the lower base plate portion which is arranged in a solder ball area are preformed plastic package in advance; tops of the solder balls are exposed to be used for interconnection with the upper packaging body; at least a chip is pasted above a lower base plate portion which is arranged outside the solder ball area and not being performed plastic package in an inversion mode; a chip area is not performed plastic package; epoxy welding-aid agent is filled between the upper base plate and the lower base plate; and exposed portions of the solder ball tops and a circuit terminal which is arranged under the upper base plate are formed into electrical interconnection in a certain way. Height of a welding area of the lower base plate is blocked up due to the solder balls and plastic package glue, so that influences from an upper chip package height of the lower base plate to the gap which is formed between the upper base plate and the lower plate are reduced, and when the solder balls are manufactured on the upper base plate, the solder ball diameters are reduced, and a thin-gap package purpose is achieved.
Description
Technical field
The present invention relates to the integrated circuit encapsulation field, particularly, is to form thin space encapsulating structure and method for packing in a kind of stacked package technology (POP).
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit is constantly dwindled, and interconnection density improves constantly.The user improves constantly the requirement of high-performance low power consumption simultaneously.In this case, the mode that improves performance by the live width of further dwindling interconnection line is subjected to the restriction of physical characteristics of materials and apparatus and process, and the resistance capacitance of two-dimentional interconnection line (RC) postpones to become gradually the bottleneck that restriction semiconductor core piece performance improves.
Piling up of chip is one of main path that improves highly denseization of Electronic Packaging, and as the highly dense integrated main mode of present encapsulation, POP (package on package, stacked package) is more and more paid attention to.A typical two-layer POP design as shown in Figure 1, the reflux course of following packaging body 13 by soldered ball 12 be welded to packaging body 11 below, more multi-layered POP designs can repeat as above process.Chip and last packaging body on following packaging body produce interference, soldered ball 12 diameters of following packaging body 13 peripheries generally are designed to the height greater than chip, but so design has just increased the size of soldered ball 12 and its spacing, and it is opposing that this and encapsulation technology highly dense integrated requires.
Therefore having put down in writing use TMV (Through Mold Via, embedding through hole) technology in the patent documentation of U.S. Patent number: US7671457 realizes thin space POP packaging technology.As shown in Figure 2, this encapsulating structure comprises packaging body 11 ', following packaging body 12 ', and at the plastic packaging glue 13 ' between the packaging body up and down.The TMV technology is by carrying out laser drilling at plastic packaging glue 13 ', produce running through the pore 30 ' of plastic packaging glue 13 ', carries out metal filledly then in pore 30 ', realizes the electrical connection of packaging body up and down.Yet the weak point of TMV technology is that do destructiveness to the intact product of plastic packaging with laser punches, and correlation step is more, comprises plastic packaging, punching, filling scolder, applying etc., and implementation procedure is complicated.
Therefore, be necessary to propose a kind of new thin space POP packaging technology, to solve implementation procedure past complicated problems in the prior art.
Summary of the invention
In view of this, the objective of the invention is to propose a kind of thin space POP formula encapsulating structure and method for packing, characteristics simple in structure, that be easy to make that this encapsulating structure and method for packing have.
A kind of thin space POP formula encapsulating structure according to purpose proposition of the present invention, comprise the packaging body of two interconnection up and down, on, between the following packaging body electric intercommunication is arranged, the described substrate of going up packaging body is upper substrate, the substrate of following packaging body is infrabasal plate, defined a weld zone that is used for that the chip encapsulation region of chip is installed and is used for carrying out with last packaging body electrical interconnection on the upper surface of described infrabasal plate, the chip encapsulation region is arranged on the zones of different beyond the weld zone, described infrabasal plate has been implanted some solder balls on the weld zone, infrabasal plate upper surface in described solder ball and the solder ball zone is by the pre-plastic packaging of plastic packaging glue, described chip encapsulation region is not by plastic packaging, expose outside described plastic packaging glue at the top of described solder ball, be used for the interconnection with last packaging body, one or more chips are mounted in the chip encapsulation region of infrabasal plate in the upside-down mounting mode, and form electric intercommunication with infrabasal plate, be provided with filler in the gap of upper substrate and infrabasal plate, form interconnection by soldered ball and the docking of described solder ball that is arranged at the upper substrate bottom surface between upper substrate and the infrabasal plate, this interconnection forms at least one electrical connection.
Preferably, at least one in described upper substrate, the infrabasal plate is provided with groove, and the chip of described infrabasal plate is mounted in the position of this groove correspondence in the upside-down mounting mode.
Preferably, described filler is the epoxy scaling powder.
Preferably, described upper substrate is provided with one or more chips, when a plurality of chip, described a plurality of chips with side by side or the mode of lamination be encapsulated in the upper surface of described upper substrate.
Preferably, described top of going up packaging body also is provided with one or more packaging bodies.
Preferably, the below of described down packaging body and another or the interconnection of a plurality of packaging body perhaps interconnect with a PCB, and form an electrical connection at least.
Preferably, the spacing of described solder ball is corresponding with the space between solder balls of described upper substrate bottom surface.
The invention allows for a kind of thin space POP formula method for packing simultaneously, comprise the manufacture craft of packaging body, the manufacture craft of following packaging body and the interconnection process of upper and lower encapsulation,
The described system of encapsulation down comprises step as technology:
Solder ball is implanted in weld zone on infrabasal plate;
Solder ball is carried out pre-plastic packaging, make the top of solder ball be exposed to the plastic packaging glue-line, and retain the substrate chip encapsulation region and do not covered by plastic packaging glue;
With the chip encapsulation region of one or more chip attachment at infrabasal plate, chip bottom is filled the end and is filled glue in the upside-down mounting mode;
Apply filler at the infrabasal plate upper surface, this filler is such as being epoxy scaling powder or other gentle matter colloid.
Preferably, the described manufacture craft that goes up packaging body comprises step:
Encapsulate one or more chips at the upper substrate upper surface;
Implant a plurality of thin space soldered balls in the bottom surface of upper substrate, the position correspondence of these soldered balls is above the solder ball of infrabasal plate.
Preferably, also be included in the step of making groove on infrabasal plate or upper substrate or the upper and lower substrate, the chip with infrabasal plate is encapsulated in the position of described groove correspondence then.
Thin space POP formula encapsulating structure of the present invention, by making solder ball at infrabasal plate and these solder balls being carried out pre-plastic packaging, bed hedgehopping the height of infrabasal plate weld zone, make chip packaging height on the infrabasal plate weaken for the spacing influence of upper and lower base plate, so can be when upper substrate be made soldered ball, dwindle the sphere diameter of soldered ball, thereby reach the purpose of thin space encapsulation.The prior art of comparing, the combination of solder ball+plastic packaging glue that the present invention adopts, omitted destructive punching and and irritate complicated technology such as scolder, have and make advantages such as simple, that production efficiency is high, technology is with low cost.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is existing two-layer POP encapsulating structure schematic diagram.
Fig. 2 is to use the POP encapsulating structure schematic diagram of TMV technology.
Fig. 3 is the thin space POP formula encapsulating structure schematic diagram of first embodiment of the invention.
Fig. 4 is the thin space POP formula encapsulating structure schematic diagram of second embodiment of the invention.
Fig. 5 A-5C is the thin space POP formula method for packing schematic flow sheet under the first embodiment of the invention.
Embodiment
Just as described in the background art, in the existing P OP encapsulation technology, therefore common process can't realize the encapsulation interconnection of thin space because pedestal need guarantee to be higher than chip thickness.And in TMV technology, by laser drilling, though can produce thinner conductive through hole at packaging plastic, but because laser drilling itself is a kind of destructive technology, add this Technology Need and use correlation step such as plastic packaging, punching, filling scolder, applying, make that the POP encapsulation technology under the whole TMV technology is too loaded down with trivial details, efficient and the cost of influence encapsulation.
Therefore, the present invention proposes a kind of encapsulating structure and the corresponding method for packing that can realize thin space POP encapsulation technology.This encapsulating structure is realized thin space between the pedestal by the size that reduces pedestal itself, and its technical problem that will overcome is how the size of pedestal to be dwindled.In the prior art, pedestal is subject to chip and is encapsulated in intrinsic height on the substrate, for instance, at present common chip thickness is greater than about 150um-200um, to lose money instead of making money encapsulation, chip height after the encapsulation is greatly about 200um-250um, and in order to guarantee the interconnection validity of packaging body up and down, often the sphere diameter with pedestal is set in about 300um.And when usually carrying out the interconnection of encapsulation point up and down with pedestal, the spacing between each salient point should be about 2 times of the own size of salient point, can prevent from occurring when reflow soldering the short circuit problem of adjacent salient point like this.So, the distance between the pad is near 500um-600um, even some is near 1mm, and such spacing obviously can't be competent at for the highly integrated encapsulation technology of present high density.In order to solve this technical problem, the technological means that the present invention adopts is: be implanted with solder ball in the certain zone of infrabasal plate, infrabasal plate upper surface in solder ball and the solder ball zone is by pre-plastic packaging, but the solder ball top expose for the interconnection of last packaging body, one or more chips are mounted on the solder ball zone in addition not by the infrabasal plate of pre-plastic packaging top in the upside-down mounting mode, chip area is not by plastic packaging, fill epoxy scaling powder or other filler between upper substrate and the infrabasal plate, the circuit terminal of solder ball top exposed portions serve and upper substrate bottom surface forms electrical interconnection by certain mode, on, form between the infrabasal plate and be electrically connected.
To be described in detail technical scheme of the present invention by embodiment below.
See also Fig. 3, Fig. 3 is the schematic diagram of the thin space POP formula encapsulating structure under the first embodiment of the invention.As shown in the figure, this encapsulating structure 100 comprises the packaging body 110,120 of two interconnection up and down, and electric intercommunication is arranged between the packaging body up and down.The substrate of last packaging body 110 is upper substrate 111, the substrate of packaging body 120 is infrabasal plate 121 down.Wherein defined a weld zone that is used for that the chip encapsulation region of chip is installed and is used for carrying out with last packaging body electrical interconnection on the upper surface of infrabasal plate 121, the chip encapsulation region is arranged on the zones of different beyond the weld zone, wherein implanted solder ball 123 on the weld zone, the spacing of each solder ball 123 is corresponding with the soldered ball 114 of upper substrate 111 bottom surfaces, infrabasal plate upper surface in solder ball 123 and solder ball 123 zones is by plastic packaging glue 124 pre-plastic packagings, but expose outside plastic packaging glue 124 at the top of solder ball 123, is used for the interconnection with last packaging body.Between upper substrate 111 and the infrabasal plate 121 by soldered ball 114 and solder ball 123 dock or alternate manner forms interconnection, this interconnection forms at least one effective electrical connection.One or more chips 122 are mounted in the chip encapsulation region of infrabasal plate 121 in the upside-down mounting mode, and form electric intercommunication with infrabasal plate 121.Chip 122 regions do not have pre-plastic packaging, but cover filler 125, this filler 125 can cover the upper surface of whole infrabasal plate 121, this moment is after last packaging body and following packaging body interconnect, namely be provided with this filler 125 in the gap of upper substrate 111 and infrabasal plate 121, this filler 125 is epoxy scaling powder or other filler.This POP formula encapsulating structure, the combination of the solder ball on the infrabasal plate+plastic packaging glue, similar with the effect of TMV technology in the prior art, be when packaging body carries out electrical interconnection up and down, the object of 114 1 welding of soldered ball on the upper substrate is provided, simultaneously because the existence of this solder ball+plastic packaging glue, bed hedgehopping the height of infrabasal plate weld zone, make chip packaging height on the infrabasal plate weaken for the spacing influence of upper and lower base plate, so can be when upper substrate be made soldered ball, dwindle the sphere diameter of soldered ball, thereby reach the purpose of thin space encapsulation.The existing TMV technology of comparing, the combination of solder ball+plastic packaging glue that the present invention adopts, omitted destructive punching and and irritate complicated technology such as scolder, make advantages such as simple, that production efficiency is high, technology is with low cost.
Above-mentioned last packaging body 110 might arrange one or more chips 112 on upper substrate 111, these chips 112 can be arranged on the upper surface of upper substrate 111 in mode side by side, also can be arranged on the upper surface of upper substrate 111 in the mode of piling up.Has electrical interconnection between these chips 112 and the upper substrate 111, the form of electrical interconnection can be passed through the form of lead-in wire as shown in FIG. and carry out, namely chip 112 and upper substrate 111 are provided with pad (pad), by wire bonds (wire bonding) pad of chip 112 and the pad of upper substrate 111 are connected then, realize electrical interconnection.Also can be undertaken by the form of ball grid array, namely in chip 112 bottom surfaces and upper substrate 111 upper surface correspondence positions pad is set separately, by soldered ball these pads be connected, realize electrical interconnection.Certainly, as the form of other known chip electrical interconnection of this area, also can be used as optional execution mode and be applied in herein.On upper substrate 111, be provided with the conductive through hole (not shown) that runs through whole base plate, the position of these conductive through holes can be set directly at upper substrate 111 and the pad below that chip 112 interconnects, and also can be connected to by the metal interconnecting layer on the substrate on these pads.The effect of these conductive through holes is that the chip with the upper surface of upper substrate is electrically connected at least one soldered ball 114 of bottom surface, thereby realizes effective electrical interconnection of packaging body up and down.In the outside of chip 112, cover one deck plastic packaging glue 113 and encapsulate fixing.
The top that should go up encapsulation 110 can also allow by certain approach interconnect another or a plurality of packaging body again, and forms at least one electrical connection.
Above-mentioned following packaging body 120, at the solder ball 123 that infrabasal plate 121 is implanted, it has highly determined the spacing between the upper and lower base plate.Consider the make efficiency of solder ball 123, in the present invention, its preferred sphere diameter is approximately between 100um-200um, so, chip 122 is encapsulated into after the infrabasal plate 121, and relatively exposing highly greatly about about 50 to 150um of solder ball 123, the sphere diameter of the soldered ball 114 on the upper substrate 111 can be made into greatly about 100um-200um, spacing between soldered ball can be produced on 200um-400um, reaches the purpose of thin space POP encapsulation.
Further, filler 123 is soft semi-fluid colloid in the normal state, and when soldered ball 114 welds when living in down packaging body by reflux technique, 123 in this filler is subjected to hot curing, forms the relatively encapsulated layer of hard.
Following packaging body 120 is the same with last packaging body 110, thereunder allows one or more packaging bodies that interconnect again, perhaps directly will descend packaging body 120 to be welded on the pcb board, forms at least one electrical connection.As described in Figure, this time packaging body directly can be interconnected with a pcb board by soldered ball 126, and form an electrical connection at least.
See also Fig. 4, Fig. 4 is the schematic diagram of the thin space POP encapsulating structure under the second embodiment of the invention.In this embodiment, offer a groove in the bottom surface of infrabasal plate 121, this groove correspondence is at infrabasal plate chip encapsulation region, and one or more chips 122 are mounted in this groove in the upside-down mounting mode.Because the existence of groove makes the packaging height of chip 122 further reduce, even make the packaging height of this chip 122 be lower than the height of solder ball 123, so, when packaging body carries out electrical interconnection up and down, can need not consider the influence of the packaging height of chip 122 fully, make that the sphere diameter design freedom big or small and spacing of soldered ball 114 is bigger.Certainly, the degree of depth of this groove also should not be dark excessively, otherwise can influence the substrate intensity at groove location place.
In several modes of texturing of second execution mode, also this groove can be produced on the upper substrate 111, make the position correspondence of groove above infrabasal plate chip 122, so also can reach above-mentioned effect.Certainly in the another kind distortion, can on upper and lower base plate, all make groove, reduce the effect that chip thickness limits the soldered ball sphere diameter thereby reach.
Below, be described in detail with regard to thin space POP method for packing of the present invention.
See also Fig. 5 A-5C, Fig. 5 A-5C is the thin space POP method for packing flow chart under the first embodiment of the invention.Fig. 5 A is the making of packaging body down, and Fig. 5 B is the making of going up packaging body, and Fig. 5 C will connect the schematic diagram that a packaging body interconnects up and down.
Wherein descend the making of packaging body to comprise step:
1.1) weld zone on infrabasal plate implants solder ball;
1.2) solder ball is carried out pre-plastic packaging, make the top of solder ball be exposed to the plastic packaging glue-line, and retain the substrate chip encapsulation region and do not covered by plastic packaging glue;
1.3) in the upside-down mounting mode with the chip encapsulation region of one or more chip attachment at infrabasal plate, chip bottom is filled the end and is filled glue;
1.4) applying filler at the infrabasal plate upper surface, this filler is such as being epoxy scaling powder or other gentle matter colloid;
The making of last packaging body comprises step:
2.1) encapsulate one or more chips at the upper substrate upper surface, comprise steps such as paster, bonding wire, plastic packaging.
2.2) implant a plurality of thin space soldered balls at the lower surface of upper substrate, the position correspondence of these soldered balls is on the zone outside the infrabasal plate groove.
The packaging body contraposition is fitted up and down at last, makes soldered ball with the upper and lower base plate solder interconnections by Reflow Soldering, forms a packaging body.And implant soldered ball at the following lower surface of packaging body, the effect of these soldered balls is that total encapsulating structure electrical interconnection that packaging body is up and down formed is to other packaging body or interconnect directly on the pcb board and go.
In some applications, also be included in the one or more packaging bodies of continuation interconnection on the packaging body.
During encapsulating structure in the corresponding above-mentioned execution mode two, also be included in the step of making groove on infrabasal plate or upper substrate or the upper and lower substrate, the chip with infrabasal plate is encapsulated in the position of groove correspondence then, makes the packaging height of chip further reduce.
In sum, the present invention proposes a kind of thin space POP encapsulating structure and method for packing, by making solder ball at infrabasal plate and these solder balls being carried out pre-plastic packaging, bed hedgehopping the height of infrabasal plate weld zone, make chip packaging height on the infrabasal plate weaken for the spacing influence of upper and lower base plate, so can when upper substrate is made soldered ball, dwindle the sphere diameter of soldered ball, thereby reach the purpose of thin space encapsulation.The prior art of comparing, the combination of solder ball+plastic packaging glue that the present invention adopts, omitted destructive punching and and irritate complicated technology such as scolder, have and make advantages such as simple, that production efficiency is high, technology is with low cost.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. thin space POP formula encapsulating structure, comprise the packaging body of two interconnection up and down, on, between the following packaging body electric intercommunication is arranged, the described substrate of going up packaging body is upper substrate, the substrate of following packaging body is infrabasal plate, defined a weld zone that is used for that the chip encapsulation region of chip is installed and is used for carrying out with last packaging body electrical interconnection on the upper surface of described infrabasal plate, the chip encapsulation region is arranged on the zones of different beyond the weld zone, it is characterized in that: described infrabasal plate has been implanted some solder balls on the weld zone, infrabasal plate upper surface in described solder ball and the solder ball zone is by the pre-plastic packaging of plastic packaging glue, described chip encapsulation region is not by plastic packaging, expose outside described plastic packaging glue at the top of described solder ball, be used for the interconnection with last packaging body, one or more chips are mounted in the chip encapsulation region of infrabasal plate in the upside-down mounting mode, and form electric intercommunication with infrabasal plate, be provided with filler in the gap of upper substrate and infrabasal plate, form interconnection by soldered ball and the docking of described solder ball that is arranged at the upper substrate bottom surface between upper substrate and the infrabasal plate, this interconnection forms at least one electrical connection.
2. thin space POP formula encapsulating structure as claimed in claim 1, it is characterized in that: at least one in described upper substrate, the infrabasal plate is provided with groove, and the chip of described infrabasal plate is mounted in the position of this groove correspondence in the upside-down mounting mode.
3. as any described thin space POP formula encapsulating structure of claim 1-2, it is characterized in that: described filler is the epoxy scaling powder.
4. as any described thin space POP formula encapsulating structure of claim 1-2, it is characterized in that: described upper substrate is provided with one or more chips, when a plurality of chip, described a plurality of chips with side by side or the mode of lamination be encapsulated in the upper surface of described upper substrate.
5. as any described thin space POP formula encapsulating structure of claim 1-2, it is characterized in that: described top of going up packaging body also is provided with one or more packaging bodies.
6. as any described thin space POP formula encapsulating structure of claim 1-2, it is characterized in that: the below of described down packaging body and another or the interconnection of a plurality of packaging body perhaps interconnect with a PCB, and form an electrical connection at least.
7. as any described thin space POP formula encapsulating structure of claim 1-2, it is characterized in that: the spacing of described solder ball is corresponding with the space between solder balls of described upper substrate bottom surface.
8. a thin space POP formula method for packing comprises the manufacture craft of packaging body, the manufacture craft of following packaging body and the interconnection process of upper and lower encapsulation, it is characterized in that:
The described system of encapsulation down comprises step as technology:
Solder ball is implanted in weld zone on infrabasal plate;
Solder ball is carried out pre-plastic packaging, make the top of solder ball be exposed to the plastic packaging glue-line, and retain the substrate chip encapsulation region and do not covered by plastic packaging glue;
With the chip encapsulation region of one or more chip attachment at infrabasal plate, chip bottom is filled the end and is filled glue in the upside-down mounting mode;
Apply filler at the infrabasal plate upper surface, this filler is such as being epoxy scaling powder or other gentle matter colloid.
9. thin space POP formula method for packing as claimed in claim 8 is characterized in that: the described manufacture craft that goes up packaging body comprises step:
Encapsulate one or more chips at the upper substrate upper surface;
Implant a plurality of thin space soldered balls in the bottom surface of upper substrate, the position correspondence of these soldered balls is above the solder ball of infrabasal plate.
10. thin space POP formula method for packing as claimed in claim 8 is characterized in that: also be included in the step of making groove on infrabasal plate or upper substrate or the upper and lower substrate, the chip with infrabasal plate is encapsulated in the position of described groove correspondence then.
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Application publication date: 20130918 |