CN103296202B - Phase change memory and manufacturing method thereof - Google Patents
Phase change memory and manufacturing method thereof Download PDFInfo
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- CN103296202B CN103296202B CN201210053864.0A CN201210053864A CN103296202B CN 103296202 B CN103296202 B CN 103296202B CN 201210053864 A CN201210053864 A CN 201210053864A CN 103296202 B CN103296202 B CN 103296202B
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Abstract
Provided are a phase change memory and a manufacturing method of the phase change memory. The manufacturing method of the phase change memory comprises the steps of (1) providing a semiconductor substrate which comprises a first area and a second area, (2) carrying out deposition to form a dielectric layer, forming a bottom electrode in the dielectric layer on the second area of the semiconductor substrate, (3) carrying out deposition to form a phase change material, carrying out etching on the phase change material, forming an imaging phase change material layer at the position, corresponding to the bottom electrode, of the upper portion of the dielectric layer, forming fake phase change pads at the partial position corresponding to the first area of the semiconductor substrate, wherein a gap exists between the imaging phase change material layer and each fake phase change pad, each fake phase change pad at least comprises two portions, and a gap exists between every two adjacent portions, and (4) carrying out cleaning processing on the semiconductor substrate after the fake phase change pads are formed. Due to the facts that the fake phase change pads are divided into a plurality of portions, and the gap exists between every two adjacent portions, the problem that the fake phase change pads are easy to peel off in the process of cleaning processing after etching of the phase change material is effectively solved.
Description
Technical field
The invention belongs to field of microelectronic fabrication, particularly a kind of phase transition storage and preparation method thereof.
Background technology
Phase transition storage (Phase Change Memory, PCM) there is the speciality such as reading speed is high, power is low, capacity is high, reliability is high, erasable number of times is high, operating voltage is low, and be applicable to very much being combined with CMOS technology, can be used for the stand alone type as higher density or Embedded memory application, is the memory of future generation be extremely expected at present.Due to the unique advantage of Phase change memory technology, also make it be considered to very likely replace the non-volatility memorizers (Non-volatile Memory) such as the volatile storages such as SRAM and DRAM highly competititve at present (Volatile Memory) and Flash, be expected to become following potential new generation semiconductor memory.
Phase transition storage utilizes the resistance difference of phase-change material under crystalline state and non-crystalline to store data, and it mainly utilizes the control of current impulse ripple to come write, erasing, read operation.Fig. 1 is a kind of rough schematic view of common phase transition storage, as shown in Figure 1, phase transition storage 11 comprises the bottom electrode 13 be formed in dielectric layer 12, phase-change material layers 14, top electrode 15 from the bottom to top successively, and the surface of bottom electrode 13 flushes with the surperficial 12a of dielectric layer 12.When write operation will be carried out, a short time (such as 50 nanoseconds) can be provided and relatively high electric current (such as 0.6 milliampere), the phase-change material layer segment 14a contacted is melted and cool and form amorphous phase-change material fast with bottom electrode 13.Because amorphous state phase-change material has higher resistance (such as 10
5~ 10
7ohm), making it when carrying out read operation, providing a reading electric current can obtain higher voltage.When erase operation will be carried out, a long period (such as 100 nanoseconds) can be provided and relatively low electric current (such as 0.3 milliampere), make Amorphous Phase change material layer part 14a convert the phase-change material of crystalline state to because of crystallization.Because crystalline state phase-change material has lower resistance (such as 10
2~ 10
4ohm), it is when carrying out read operation, provides a reading electric current can obtain relatively low voltage.Accordingly, the operation of phase transition storage can be carried out.
The preparation method of existing a kind of phase transition storage comprises as follows:
As shown in Figure 2, depositing first dielectric layer 2 on semiconductor substrate 1, as silica, silicon nitride or silicon oxynitride etc.Then, such as photoetching and etching technics is utilized to carry out graphical treatment to the first dielectric layer 2, to form through hole (not shown) in the first dielectric layer 2.Filled conductive material in through hole, to form the bottom electrode 3 of phase transition storage.The Semiconductor substrate 1 being formed with the first dielectric layer 2 and bottom electrode 3 forms phase-change material layers 4, as Ge-Sb-Te chalcogenide.Then, in order to the needs of subsequent technique, phase-change material layers 4 forms barrier layer (barrier layer) 5, it may be used for protecting phase-change material layers 4.
As shown in Figure 3, the Semiconductor substrate 1 being formed with phase-change material layers 4 and barrier layer 5 forms photoresist 6, utilize photoetching process to carry out graphical treatment to photoresist 6, to form window 7 in photoresist 6, guarantee to be coated with photoresist 6 in the position of corresponding bottom electrode 3 above barrier layer 5.
As shown in Figure 4, the phase-change material layers 4 of the barrier layer 5 do not covered by photoresist 6 and below thereof is etched, after etching, be coated with phase-change material above barrier layer 5 in the position of corresponding bottom electrode 3, this part phase-change material forms the patterned phase change material layer 4 ' of memory.In etching process, Semiconductor substrate 1 surface can form in some semiconductor technologies the accessory substance 8 not wishing to obtain, as polymer (polymer).Therefore, cleaning treatment need be carried out to the Semiconductor substrate 1 after etching.
As shown in Figure 5, photoresist 6 is removed.The HF acid solution containing water is utilized to clean, to remove accessory substance 8.
After cleaning, according to subsequent technique needs, as shown in Figure 6, the second dielectric layer 9 can be formed on semiconductor substrate 1, as silica, silicon nitride, silicon oxynitride etc.Then, utilize cmp (CMP) technique to carry out polishing until expose the surface on barrier layer 5 to the second dielectric layer 9, barrier layer 5 can be used as polishing stop layer in this process, so that the second dielectric layer 9 is ground to predetermined thickness.And then forming the top electrode (not shown) of phase transition storage, top electrode, bottom electrode 3, patterned phase change material layer 4 ' between top electrode and bottom electrode 3 form phase transition storage.
When carrying out above-mentioned cmp to the second dielectric layer 9, following situation may be there is: as shown in Figure 7, (Fig. 7 is for left side to be arranged in patterned phase change material layer 4 ' left side, also can be right side) the first dielectric layer 2 on do not form any graphic structure, so that after described chemical mechanical milling tech, can pit be formed in second dielectric layer 9, cause polishing uneven.
For solving the uneven problem of above-mentioned polishing, shown in ginseng Fig. 4, while etch to be formed the patterned phase change material layer 4 ' of phase transition storage to phase-change material layers 4, pseudo-phase transformation pad (dummy pad) 10 can be formed, to improve the polishing uniformity of subsequent chemical mechanical grinding technics in the side (for left side in figure) of patterned phase change material layer 4 '.
Because the bonding force between phase-change material layers and its lower dielectric layer is not strong, when carrying out above-mentioned cleaning treatment to Semiconductor substrate, pseudo-phase transformation pad 10 usually can be caused to peel off, as shown in Fig. 5, Fig. 8 (Fig. 8 is the partial top view of Fig. 5).After being representative cleaning with the pseudo-phase transformation pad 10 that the pseudo-phase transformation pad 10 of dotted lines, barrier layer 5 and Fig. 8 medium dip are placed in Fig. 5, pseudo-phase transformation pad 10 is no longer adsorbed on Semiconductor substrate.More seriously, though when the concentration of cleaning solution little to 3000: 1 (volume ratio of water and HF acid) time, the problem that pseudo-phase transformation pad peels off still can not improve.
Summary of the invention
The problem to be solved in the present invention is to provide a kind of preparation method of phase transition storage, peels off to prevent pseudo-phase transformation pad in the cleaning treatment process after phase-change material layers etching.
For solving the problem, the invention provides a kind of preparation method of phase transition storage, described method comprises:
There is provided Semiconductor substrate, it comprises first area, second area;
Dielectric layer, forms bottom electrode in the dielectric layer of second area;
Depositing phase change material, then it is etched, to form pseudo-phase transformation pad at the local location of the position formation patterned phase change material layer of the corresponding bottom electrode of described dielectric layer, corresponding first area, interval is there is between described patterned phase change material layer and described pseudo-phase transformation pad, described pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part;
To being formed with described patterned phase change material layer, the dielectric layer of pseudo-phase transformation pad carries out cleaning treatment.
Alternatively, the surface of described bottom electrode flushes with described dielectric layer surface or lower than described dielectric layer surface.
Alternatively, the making step of described bottom electrode comprises:
Through hole is formed in dielectric layer on Semiconductor substrate second area;
Deposits conductive material, makes described through hole be entirely filled therewith;
Cmp is carried out to described conductive material, until expose described dielectric layer;
Remove the partially conductive material in described through hole, residual conductive material forms bottom electrode.
Alternatively, the making step of described patterned phase change material layer, pseudo-phase transformation pad comprises:
Depositing phase change material layer, barrier layer successively in the Semiconductor substrate being formed with bottom electrode;
Described barrier layer forms graphical photoresist, makes to be coated with photoresist at the local location of the position of corresponding bottom electrode and corresponding Semiconductor substrate first area above described barrier layer;
Remove barrier layer not covered by photoresist, phase-change material layers, described bottom electrode is formed patterned phase change material layer, and the dielectric layer on Semiconductor substrate first area forms pseudo-phase transformation pad, interval is there is between described pseudo-phase transformation pad and patterned phase change material layer, described pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part.
Alternatively, the material on described barrier layer is TiN.
Alternatively, between described part and adjacent part, the width at interval is 40nm ~ 180nm.
Alternatively, the width of described pseudo-phase transformation pad is 1 μm ~ 10 μm, length is 1 μm ~ 10 μm.
Alternatively, utilize the HF acid containing water to carry out described cleaning treatment step, the volume ratio of water and HF acid is 1000: 1 ~ 15000: 1.
Alternatively, the time of described cleaning treatment is 20s ~ 120s.
Alternatively, described dielectric layer is PETEOS.
Meanwhile, present invention also offers a kind of phase transition storage, comprising:
Dielectric layer, its be positioned at comprise first area, second area Semiconductor substrate on;
Bottom electrode, it is located in the dielectric layer on Semiconductor substrate second area;
Patterned phase change material layer, it is positioned at above bottom electrode;
Pseudo-phase transformation pad, it is positioned at the dielectric layer on Semiconductor substrate first area, there is interval between described pseudo-phase transformation pad and described patterned phase change material layer, and described pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part.
Alternatively, the upper surface of described bottom electrode flushes with described dielectric layer surface or lower than described dielectric layer surface.
Alternatively, barrier layer is provided with above described patterned phase change material layer, pseudo-phase transformation pad.
Alternatively, the material on described barrier layer is TiN.
Alternatively, between described part and adjacent part, the width at interval is 40nm ~ 180nm.
Alternatively, the width of described pseudo-phase transformation pad is 1 μm ~ 10 μm, length is 1 μm ~ 10 μm.
Alternatively, described dielectric layer is PETEOS.
Compared with prior art, after pseudo-phase transformation pad is divided into the multiple parts that there is interval each other by the present invention, effectively improve the flaky problem of pseudo-phase transformation pad in the cleaning treatment process after phase-change material layers etching.
Accompanying drawing explanation
Fig. 1 is a kind of rough schematic view of common phase transition storage.
Fig. 2 to Fig. 6 is the making schematic diagram of existing a kind of phase transition storage.
Fig. 7 is when the side of patterned phase change material layer does not form pseudo-phase transformation pad, carries out cmp so that occur the schematic diagram that polishing is uneven to dielectric layer.
Fig. 8 is the schematic diagram that in the cleaning process of existing phase transition storage after phase-change material layers etching, pseudo-phase transformation pad peels off.
Fig. 9 is the Making programme figure of phase transition storage in an embodiment of phase transition storage preparation method of the present invention.
Figure 10 to Figure 16, Figure 18, Figure 19 are the sectional views of phase transition storage in an embodiment of phase transition storage preparation method of the present invention.
Figure 17 is that in the cleaning process of the present invention after phase-change material etching, pseudo-phase transformation pad does not exist the schematic diagram peeled off.
Detailed description of the invention
The problem to be solved in the present invention is to provide a kind of preparation method of phase transition storage, peels off to prevent pseudo-phase transformation pad in the cleaning treatment process after phase-change material layers etching.
For solving the problem, inventor finds, after pseudo-phase transformation pad being divided into the multiple parts that there is interval each other, bonding force between pseudo-phase transformation pad and its lower dielectric layer can been significantly enhanced, and effectively improves the flaky problem of pseudo-phase transformation pad in the cleaning treatment process after phase-change material layers etching.
Below in conjunction with accompanying drawing, by specific embodiment, carry out clear, complete description to technical scheme of the present invention, obviously, described embodiment is only a part for embodiment of the present invention, instead of they are whole.According to these embodiments, those of ordinary skill in the art's obtainable other embodiments all under without the need to the prerequisite of creative work, all belong to protection scope of the present invention.
Fig. 9 is the Making programme figure of phase transition storage in an embodiment of phase transition storage preparation method of the present invention.As described in Figure 9, described method comprises:
Step S100: provide Semiconductor substrate, it comprises first area, second area.
Step S200: dielectric layer, forms bottom electrode in the dielectric layer on Semiconductor substrate second area.
Step S300: depositing phase change material, it is etched, so that the position formation patterned phase change material layer of the corresponding bottom electrode in side, the local location of corresponding semiconductor first area form pseudo-phase transformation pad on the dielectric layer, interval is there is between patterned phase change material layer and pseudo-phase transformation pad, pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part.
Step S400: to being formed with patterned phase change material layer, the dielectric layer of pseudo-phase transformation pad carries out cleaning treatment.
Figure 10 to Figure 19 is the sectional view of phase transition storage in an embodiment of phase transition storage preparation method of the present invention, is combined by Figure 10 to Figure 19 be below described the preparation method of phase transition storage of the present invention with Fig. 9.
First step S100 is performed: provide Semiconductor substrate, it comprises first area, second area.
As shown in Figure 10, provide Semiconductor substrate 20, it is at least divided into two regions: first area I, second area II.In other embodiments of the invention, Semiconductor substrate also can be divided into the region of three or more, for other semiconductor devices forming integrated circuit.In a preferred embodiment of the invention, Semiconductor substrate 20 is silicon substrate, but the present invention is not limited to this, and Semiconductor substrate 20 can be made up of other semi-conducting material.Semiconductor substrate 20 can be the substrate having completed CMOS FEOL, namely may comprise isolation structure, electric capacity, diode or similar semiconductor device structure in Semiconductor substrate.
In order to control the operation of phase transition storage, before forming the bottom electrode of phase transition storage on a semiconductor substrate, switch element (not shown) need be formed on a semiconductor substrate, the phase transition storage of switch element and follow-up formation is electrically connected, to heat the electrode of phase transition storage, the crystalline state of partial phase change material layer (the part phase-change material layers contacted with bottom electrode) is changed.Switch element comprises the vertical diode (vertical diode) that p type semiconductor layer and n type semiconductor layer form, but the present invention is not limited to this, described switch element can also be bipolar junction transistor (bipolar junction transistor, or mos field effect transistor (metal oxide semiconductor field effect transistor, MOSFET) BJT).
Then perform step S200: dielectric layer, forms bottom electrode in the dielectric layer on Semiconductor substrate second area, the surface of bottom electrode flushes with dielectric layer surface or lower than dielectric layer surface.
As shown in figure 11, dielectric layer 21 in Semiconductor substrate 20, dielectric layer 21 can be oxide skin(coating) or nitride layer.Described oxide skin(coating) can comprise silica (SiO
2), boron phosphorus silicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), unadulterated silicate glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on-dielectric (SOD).Nitride layer can comprise silicon nitride (silicon nitride Si
3n
4) or silicon oxynitride (SiON).In a preferred embodiment of the invention, the SiO of dielectric layer 21 for utilizing TEOS to be formed
2, i.e. PETEOS.Utilize PETEOS method deposit SiO
2speed relatively high, in integrated circuits raising silicon chip output is benefited.
In one embodiment of the invention, as shown in figure 11, such as photoetching and etching technics is utilized to carry out graphical treatment to dielectric layer 21, to form through hole (not shown) in the dielectric layer 21 on Semiconductor substrate second area II, the position of described through hole is corresponding with the switch element in Semiconductor substrate 20, can be electrically connected to make phase transition storage with switch element.Then, deposits conductive material in Semiconductor substrate 20, until described through hole is filled up by described conductive material.Described conductive material can be Ti, W, Ta, TiN, TiW, TaN, TiAl, TiWN, TiAlN etc.In a preferred embodiment of the invention, described conductive material is W.Before the described conductive material of deposition, one deck diffusion impervious layer (not shown) can be deposited on the sidewall of described through hole and bottom, as TiN, diffuse in dielectric layer to prevent subsequent deposition conductive material in through-holes.Then, cmp is carried out to conductive material, until dielectric layer 21 exposes.So far, shown in ginseng Figure 11, bottom electrode 22 can be formed in the dielectric layer 21 on Semiconductor substrate second area II, and the surperficial 22a of bottom electrode 22 flushes with the surperficial 21a of dielectric layer 21.
Shown in ginseng Fig. 1, when phase transition storage will realize the conversion between logical value 0 to logical value 1, fusion temperature must be risen to by the temperature of enough energy-activation phase-change material layer segment 14a, while heating phase-change material layer segment 14a, the phase-change material around heating phase-change material layer segment 14a need be avoided, then, carry out rapid quenching process, make phase-change material layer segment 14a become amorphous state by crystalline state, thus realize data storage.But, can be there are some problems in this phase change memory structure: when heating phase-change material layer segment 14a, heat is easy to be delivered to the phase-change material around phase-change material layer segment 14a, causes the conversion that phase transition storage cannot realize between logical value 0 to logical value 1.
For improving the problems referred to above, in a preferred embodiment of the invention, after forming the surperficial bottom electrode 22 flushed with dielectric layer surface 21a, as shown in figure 12, remove the partially conductive material in described through hole, residual conductive material forms final bottom electrode.Therefore, in this kind of phase change memory structure, the surperficial 22a of bottom electrode can lower than dielectric layer surface 21a.Described minimizing technology can be dry etching, wet etching or both the common semiconductor etching method such as to combine.In one embodiment of the invention, the conductive material in through hole about half can be removed.
Then step S300 is performed: depositing phase change material, it is etched, so that the position formation patterned phase change material layer of the corresponding bottom electrode in side, the local location of corresponding semiconductor first area form pseudo-phase transformation pad on the dielectric layer, interval is there is between patterned phase change material layer and pseudo-phase transformation pad, pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part.
As shown in figure 13, depositing phase change material layer 23 in the Semiconductor substrate 20 being formed with bottom electrode 22, phase-change material layers 23 can comprise chalcogenide, as germanium-antimony-tellurium (Ge-Sb-Te), arsenic-antimony-tellurium (As-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), tin-indium-antimony-tellurium (Sn-In-Sb-Te), arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te), tantalum-antimony-tellurium (Ta-Sb-Te), niobium-antimony-tellurium (Nb-Sb-Te), vanadium-antimony-tellurium (V-Sb-Te), tungsten-antimony-tellurium (W-Sb-Te), molybdenum-antimony-tellurium (Mo-Sb-Te), chromium-antimony-tellurium (Cr-Sb-Te), tungsten-antimony-selenium (W-Sb-Se), molybdenum antimony selenium (Mo-Sb-Se), chromium-antimony-selenium (Cr-Sb-Se), Ga-Sb, In-Sb, In-Se, Sb-Te, Ge-Te, Ag-In-Sb-Te etc.In a preferred embodiment of the invention, phase-change material layers 23 is germanium-antimony-tellurium (Ge-Sb-Te, GST).Certainly, phase-change material layers 23 also can comprise other phase-change material well-known to those skilled in the art.
Continue shown in ginseng Figure 13; in one embodiment of the invention; according to the needs of subsequent technique; after depositing phase change material layer 23; meeting deposited barrier layer (barrier layer) 24 on phase-change material layers 23, the phase-change material layers 23 be positioned at below it is protected in one of effect that barrier layer 24 is played.Barrier layer 24 can comprise the suitable conductive material such as TiN, TiW.In a preferred embodiment of the invention, barrier layer 24 is TiN.
As shown in figure 14, barrier layer 24 forms graphical photoresist, make to be coated with photoresist 25a in the position of corresponding bottom electrode 22 above barrier layer 24, and make to be coated with photoresist 25b at the local location of corresponding Semiconductor substrate first area I above barrier layer 24.Wherein, there is interval between the photoresist 25b on the photoresist 25a above bottom electrode 22 and Semiconductor substrate first area I, the photoresist 25b on the I of Semiconductor substrate first area at least comprises two parts, there is interval between adjacent part.
As shown in figure 15, with graphical photoresist for mask, remove barrier layer 24 not covered by photoresist, phase-change material layers 23, bottom electrode 22 is formed patterned phase change material layer 26, and form pseudo-phase transformation pad 27 above dielectric layer 21 on the I of Semiconductor substrate first area, there is interval between pseudo-phase transformation pad 27 and patterned phase change material layer 26.Wherein, pseudo-phase transformation pad 27 does not possess device function, and below does not need and Electrode connection, also can not connect top electrode in subsequent technique above it.The minimizing technology of barrier layer 24, phase-change material layers 23 has multiple, as dry etching, wet etching or both combinations.For obtaining better CMP effect in subsequent treatment, multiple pseudo-phase transformation pad 27 is arranged evenly with phase-change material layers 26 entirety.Each pseudo-phase transformation pad 27 at least comprise two with the part A of dielectric layer 21 surface contact, there is interval B between adjacent part A.In a preferred embodiment of the invention, the width W of interval B in pseudo-phase transformation pad 27
1for 40nm ~ 180nm, the width W of part A
2for 40nm ~ 180nm, can ensure, between pseudo-phase transformation pad 27 and its lower dielectric layer 21, there is enough bonding forces like this, pseudo-phase transformation pad in follow-up cleaning treatment process be there will not be and peel off.
Continue shown in ginseng Figure 15, when the lower electrode surface 22a formed in above-mentioned steps S200 is lower than dielectric layer surface 21a, the phase-change material layers 23 of deposition not only covers above dielectric layer 21, and have partial phase change material layer 23 and be filled in the through hole at bottom electrode 22 place, and contact with bottom electrode 22.During phase transition storage work, bottom electrode can heat phase-change material layers, due to be filled in phase-change material layer segment 23a in described through hole can with bottom electrode 22 close contact, and the surrounding of phase-change material layer segment 23a by dielectric layer 21 around, when therefore carrying out described heating process, phase-change material layer segment 23a is only had to be heated, phase-change material around phase-change material layer segment 23a can not be heated, make phase transition storage be readily embodied in conversion between logical value 0 to logical value 1, and the power consumption of phase transition storage can be reduced.
The present embodiment forms pseudo-phase transformation pad for the wherein side (left side) at patterned phase change material layer, in other embodiments of the invention, according to the needs of integrated circuit manufacture process, also can all form described pseudo-phase transformation pad in the both sides (left side, right side) of patterned phase change material layer, and the quantity of described pseudo-phase transformation pad can adjust according to actual fabrication situation simultaneously.
Compared with prior art, the pseudo-phase transformation pad in the present invention is divided into the multiple parts that there is interval each other, but the segmentation form of pseudo-phase transformation pad only should not be confined to accompanying drawing, and other similar segmentation form is also within protection scope of the present invention.
The present embodiment is after depositing phase change material layer, according to the needs of subsequent manufacturing processes, can on phase-change material layers deposited barrier layer again, therefore, when forming patterned phase change material layer, pseudo-phase transformation pad, above pseudo-phase transformation pad, meeting covering barrier layer, at this moment, also can regard as a part for pseudo-phase transformation pad by barrier layer.In other embodiments of the invention, according to the change of phase transition storage preparation method, after depositing phase change material layer, the material layer (except barrier layer) being used as other purposes may be formed on phase-change material layers, as the conductive material for the formation of top electrode, then etch to form patterned phase change material layer, pseudo-phase transformation pad to material layer, phase-change material layers, at this moment, meeting layer of cover material above pseudo-phase transformation pad, and described material layer can form a part for pseudo-phase transformation pad.
Continue shown in ginseng Figure 15, in the process removing phase-change material layers, Semiconductor substrate 20 surface can form in some semiconductor technologies the accessory substance 28 not wishing to obtain, as polymer (polymer), in order to avoid the electric property of accessory substance to phase transition storage causes adverse effect, cleaning treatment need be carried out to Semiconductor substrate.
Finally perform step S400: to being formed with patterned phase change material layer, the dielectric layer of pseudo-phase transformation pad carries out cleaning treatment.
As shown in figure 16, remove photoresist, then utilize the HF acid solution containing water to carry out cleaning treatment to Semiconductor substrate 20, to remove residual accessory substance 28.In a preferred embodiment of the invention, in described solution, the volume ratio of water and HF acid is 1000: 1 ~ 15000: 1.When cleaning time be 20s ~ 120s, residual accessory substance 28 can be ensured to remove.
Inventor utilizes the HF acid solution containing water of multiple variable concentrations successively to carry out cleaning treatment to Semiconductor substrate, and the sticky and state after detecting cleaning between pseudo-phase transformation pad and Semiconductor substrate, draw through test of many times, after pseudo-phase transformation pad 27 is split into the multiple parts that there is interval each other, bonding force between pseudo-phase transformation pad 27 and the dielectric layer 21 below it obviously strengthens, pseudo-phase transformation pad 27 is there will not be to peel off the phenomenon of (as shown in Figure 8) after carrying out cleaning treatment to substrate 20, as shown in figure 17.
After carrying out described cleaning treatment step, in one embodiment of the invention, as shown in figure 18, can in Semiconductor substrate 20 dielectric layer 29, then cmp process is carried out until expose the surface on barrier layer 24 to dielectric layer 29.In this step, barrier layer 24 can be used as the stop layer of cmp.Although pseudo-phase transformation pad 27 is divided into the multiple part A that there is interval B each other, due to the width W of interval A
2very little, thus naked eyes it seems that pseudo-phase transformation pad 27 remains an entirety.Pseudo-phase transformation pad 27 can improve the polishing uniformity in above-mentioned chemical mechanical milling tech.The overall dimensions of pseudo-phase transformation pad has material impact to polishing uniformity.In a preferred embodiment of the invention, shown in Figure 17, the width of pseudo-phase transformation pad 27 (be size same direction on part A, gap B width) W
3be 1 μm ~ 10 μm (the width summations of part A, gap B), length (size perpendicular on part A, gap B width) W
4it is 1 μm ~ 10 μm.
After described cmp process, as shown in figure 19, Semiconductor substrate 20 deposits one dielectric layer 30 again, then graphical treatment is carried out to dielectric layer 30, through hole is formed with the position of described bottom electrode 22 corresponding in dielectric layer 30, then to filled conductive metal in through hole, as Cu, to form the top electrode 31 of phase transition storage.
Meanwhile, present invention also offers a kind of phase transition storage, shown in Figure 11, Figure 12, Figure 16, it comprises:
Dielectric layer 21, its be positioned at comprise first area I, second area II Semiconductor substrate 20 on, in a preferred embodiment of the invention, the material of dielectric layer 21 is PETEOS;
Bottom electrode 22, it is located in the dielectric layer 21 on Semiconductor substrate second area II;
Patterned phase change material layer 26, it is positioned at above bottom electrode 22;
Pseudo-phase transformation pad 27, it is positioned at above the dielectric layer 21 on the I of Semiconductor substrate first area, interval is there is between pseudo-phase transformation pad 27 and patterned phase change material layer 26, and pseudo-phase transformation pad 27 at least comprises two part A contacted with dielectric layer 21, interval B is there is between adjacent part A, in a preferred embodiment of the invention, the width W of interval B between part A and adjacent part A
2, W
1for 40nm ~ 180nm, the width W of pseudo-phase transformation pad
3be 1 μm ~ 10 μm, length W
4it is 1 μm ~ 10 μm.
Optionally, be provided with barrier layer 24 above patterned phase change material layer 26, pseudo-phase transformation pad 27, its material can be TiN.
Compared with prior art, the present invention by pseudo-phase transformation pad is divided into there is interval each other multiple parts after, effectively improve phase-change material etching after cleaning treatment process in the flaky problem of pseudo-phase transformation pad.
Above by the explanation of embodiment, professional and technical personnel in the field should be able to be made to understand the present invention better, and can reproduce and use the present invention.Those skilled in the art can be apparent to above-described embodiment do various changes and modifications when not departing from the spirit and scope of the invention according to principle described herein.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection domain should be defined by appending claims.
Claims (17)
1. a preparation method for phase transition storage, is characterized in that, described preparation method comprises:
There is provided Semiconductor substrate, it comprises first area, second area;
Dielectric layer, forms bottom electrode in the dielectric layer of second area;
Depositing phase change material, then it is etched, to form pseudo-phase transformation pad at the local location of the position formation patterned phase change material layer of the corresponding bottom electrode of described dielectric layer, corresponding first area, interval is there is between described patterned phase change material layer and described pseudo-phase transformation pad, described pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part;
To being formed with described patterned phase change material layer, the dielectric layer of pseudo-phase transformation pad carries out cleaning treatment.
2. preparation method according to claim 1, is characterized in that, the surface of described bottom electrode flushes with described dielectric layer surface or lower than described dielectric layer surface.
3. preparation method according to claim 2, is characterized in that, the making step of described bottom electrode comprises:
Through hole is formed in dielectric layer on Semiconductor substrate second area;
Deposits conductive material, makes described through hole be entirely filled therewith;
Cmp is carried out to described conductive material, until expose described dielectric layer;
Remove the partially conductive material in described through hole, residual conductive material forms bottom electrode.
4. preparation method according to claim 1 and 2, is characterized in that, the making step of described patterned phase change material layer, pseudo-phase transformation pad comprises:
Depositing phase change material layer, barrier layer successively in the Semiconductor substrate being formed with bottom electrode;
Described barrier layer forms graphical photoresist, makes to be coated with photoresist at the local location of the position of corresponding bottom electrode and corresponding Semiconductor substrate first area above described barrier layer;
Remove barrier layer not covered by photoresist, phase-change material layers, described bottom electrode is formed patterned phase change material layer, and the dielectric layer on Semiconductor substrate first area forms pseudo-phase transformation pad, interval is there is between described pseudo-phase transformation pad and patterned phase change material layer, described pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part.
5. preparation method according to claim 4, is characterized in that, the material on described barrier layer is TiN.
6. preparation method according to claim 1, is characterized in that, between described part and adjacent part, the width at interval is 40nm ~ 180nm.
7. preparation method according to claim 1, is characterized in that, the width of described pseudo-phase transformation pad is 1 μm ~ 10 μm, length is 1 μm ~ 10 μm.
8. preparation method according to claim 1, is characterized in that, utilize the HF acid containing water to carry out described cleaning treatment step, the volume ratio of water and HF acid is 1000: 1 ~ 15000: 1.
9. preparation method according to claim 1, is characterized in that, the time of described cleaning treatment is 20s ~ 120s.
10. preparation method according to claim 1, is characterized in that, described dielectric layer is PETEOS.
11. 1 kinds of phase transition storages, is characterized in that, comprising:
Dielectric layer, its be positioned at comprise first area, second area Semiconductor substrate on;
Bottom electrode, it is located in the dielectric layer on Semiconductor substrate second area;
Patterned phase change material layer, it is positioned at above bottom electrode;
Pseudo-phase transformation pad, it is positioned at the dielectric layer on Semiconductor substrate first area, there is interval between described pseudo-phase transformation pad and described patterned phase change material layer, and described pseudo-phase transformation pad at least comprises two parts, there is interval between adjacent part.
12. phase transition storages according to claim 11, is characterized in that, the upper surface of described bottom electrode flushes with described dielectric layer surface or lower than described dielectric layer surface.
13. phase transition storages according to claim 11, is characterized in that, are provided with barrier layer above described patterned phase change material layer, pseudo-phase transformation pad.
14. phase transition storages according to claim 13, is characterized in that, the material on described barrier layer is TiN.
15. phase transition storages according to claim 11, is characterized in that, between described part and adjacent part, the width at interval is 40nm ~ 180nm.
16. phase transition storages according to claim 11, is characterized in that, the width of described pseudo-phase transformation pad is 1 μm ~ 10 μm, length is 1 μm ~ 10 μm.
17. phase transition storages according to claim 11, is characterized in that, described dielectric layer is PETEOS.
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| TW530350B (en) * | 2002-01-11 | 2003-05-01 | Chartered Semiconductor Mfg | Better copper CMP process utilizing dummy plugs in damascene process |
| CN101477967A (en) * | 2009-01-13 | 2009-07-08 | 南京大学 | Process for preparing vertical structure phase-change memory |
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| TW530350B (en) * | 2002-01-11 | 2003-05-01 | Chartered Semiconductor Mfg | Better copper CMP process utilizing dummy plugs in damascene process |
| CN101477967A (en) * | 2009-01-13 | 2009-07-08 | 南京大学 | Process for preparing vertical structure phase-change memory |
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