CN103296202A - Phase change memory and manufacturing method thereof - Google Patents
Phase change memory and manufacturing method thereof Download PDFInfo
- Publication number
- CN103296202A CN103296202A CN2012100538640A CN201210053864A CN103296202A CN 103296202 A CN103296202 A CN 103296202A CN 2012100538640 A CN2012100538640 A CN 2012100538640A CN 201210053864 A CN201210053864 A CN 201210053864A CN 103296202 A CN103296202 A CN 103296202A
- Authority
- CN
- China
- Prior art keywords
- phase
- change material
- dielectric layer
- pseudo
- phase change
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
Provided are a phase change memory and a manufacturing method of the phase change memory. The manufacturing method of the phase change memory comprises the steps of (1) providing a semiconductor substrate which comprises a first area and a second area, (2) carrying out deposition to form a dielectric layer, forming a bottom electrode in the dielectric layer on the second area of the semiconductor substrate, (3) carrying out deposition to form a phase change material, carrying out etching on the phase change material, forming an imaging phase change material layer at the position, corresponding to the bottom electrode, of the upper portion of the dielectric layer, forming fake phase change pads at the partial position corresponding to the first area of the semiconductor substrate, wherein a gap exists between the imaging phase change material layer and each fake phase change pad, each fake phase change pad at least comprises two portions, and a gap exists between every two adjacent portions, and (4) carrying out cleaning processing on the semiconductor substrate after the fake phase change pads are formed. Due to the facts that the fake phase change pads are divided into a plurality of portions, and the gap exists between every two adjacent portions, the problem that the fake phase change pads are easy to peel off in the process of cleaning processing after etching of the phase change material is effectively solved.
Description
Technical field
The invention belongs to field of microelectronic fabrication, particularly a kind of phase transition storage and preparation method thereof.
Background technology
Phase transition storage (Phase Change Memory, PCM) have reading speed height, speciality such as power is low, capacity is high, reliability is high, erasable number of times height, operating voltage are low, and be fit to very much be combined with CMOS technology, can be used for stand alone type or Embedded memory application as higher density, is the memory of future generation that very is expected at present.Because the unique advantage of phase transition storage technology, also make it be considered to might to replace very much non-volatility memorizers (Non-volatile Memory) such as volatile storage (Volatile Memory) such as at present highly competititve SRAM and DRAM and Flash, be expected to become following potential new generation semiconductor memory.
Phase transition storage utilizes the resistance difference of phase-change material under crystalline state and noncrystalline attitude to store data, and it mainly utilizes the control of current impulse ripple to finish and write, wipes, read operation.Fig. 1 is a kind of rough schematic view of common phase transition storage, as shown in Figure 1, phase transition storage 11 comprises bottom electrode 13, phase-change material layers 14, the top electrode 15 that is formed in the dielectric layer 12 from the bottom to top successively, and the surface of bottom electrode 13 flushes with the surperficial 12a of dielectric layer 12.In the time will carrying out write operation, a short time (for example 50 nanoseconds) and higher relatively electric current (for example 0.6 milliampere) can be provided, make with bottom electrode 13 phase change material contacting layer segment 14a and melt also cooling fast and form amorphous phase-change material.Because the amorphous state phase-change material has higher resistance (for example 10
5～10
7Ohm), make it when carrying out read operation, provide one to read electric current and can obtain higher voltage.In the time will carrying out erase operation, a long period (for example 100 nanoseconds) and relatively low electric current (for example 0.3 milliampere) can be provided, make amorphous state phase-change material layer segment 14a convert the phase-change material of crystalline state to because of crystallization.Because the crystalline state phase-change material has lower resistance (for example 10
2～10
4Ohm), it provides one to read electric current and can obtain relatively low voltage when carrying out read operation.Accordingly, can carry out the operation of phase transition storage.
The manufacture method of existing a kind of phase transition storage comprises as follows:
As shown in Figure 2, at Semiconductor substrate 1 deposition first dielectric layer 2, as silica, silicon nitride or silicon oxynitride etc.Then, utilize for example photoetching and etching technics that first dielectric layer 2 is carried out graphical treatment, in first dielectric layer 2, to form through hole (not shown).Filled conductive material in the through hole is to form the bottom electrode 3 of phase transition storage.Form phase-change material layers 4 in the Semiconductor substrate 1 that is formed with first dielectric layer 2 and bottom electrode 3, as the Ge-Sb-Te chalcogenide.Then, for the needs of subsequent technique, form barrier layer (barrier layer) 5 at phase-change material layers 4, it can be for the protection of phase-change material layers 4.
As shown in Figure 3, form photoresist 6 in the Semiconductor substrate 1 that is formed with phase-change material layers 4 and barrier layer 5, utilize photoetching process that photoresist 6 is carried out graphical treatment, in photoresist 6, to form window 7, guarantee that 5 tops, barrier layer are coated with photoresist 6 in the position of corresponding bottom electrode 3.
As shown in Figure 4, etching is carried out on the barrier layer 5 that do not covered by photoresist 6 and the phase-change material layers 4 of below thereof, after the etching, 5 tops, barrier layer are coated with phase-change material in the position of corresponding bottom electrode 3, and this part phase-change material constitutes the patterned phase change material layer 4 ' of memory.In etching process, Semiconductor substrate 1 surface can form does not wish the accessory substance 8 that obtains in some semiconductor technologies, as polymer (polymer).Therefore, need the Semiconductor substrate 1 after the etching is carried out clean.
As shown in Figure 5, remove photoresist 6.The HF acid solution that utilization contains water cleans, to remove accessory substance 8.
After the cleaning, according to the subsequent technique needs, as shown in Figure 6, can form second dielectric layer 9 in Semiconductor substrate 1, as silica, silicon nitride, silicon oxynitride etc.Then, utilize cmp (CMP) technology that second dielectric layer 9 is carried out polishing until the surface of exposing barrier layer 5, barrier layer 5 can be used as the polishing stop layer in this process, so that second dielectric layer 9 is ground to predetermined thickness.And then the top electrode (not shown) of formation phase transition storage, top electrode, bottom electrode 3, the patterned phase change material layer between top electrode and bottom electrode 34 ' constitute phase transition storage.
When second dielectric layer 9 is carried out above-mentioned cmp, may there be following situation: as shown in Figure 7, (Fig. 7 is example with the left side to be arranged in patterned phase change material layer 4 ' left side, also can be the right side) first dielectric layer 2 on do not form any graphic structure, so that through after the described chemical mechanical milling tech, can form pit in second dielectric layer 9, cause polishing inhomogeneous.
For solving the inhomogeneous problem of above-mentioned polishing, join shown in Figure 4, when phase-change material layers 4 being carried out the patterned phase change material layer 4 ' of etching with the formation phase transition storage, can form pseudo-phase transformation pad (dummy pad) 10 at a side of patterned phase change material layer 4 ' (among the figure be example with the left side), to improve the polishing uniformity of subsequent chemistry mechanical milling tech.
Because the bonding force between phase-change material layers and its below dielectric layer is not strong, when Semiconductor substrate is carried out above-mentioned clean, usually can cause pseudo-phase transformation pad 10 to peel off, shown in Fig. 5, Fig. 8 (Fig. 8 is the partial top view of Fig. 5).The pseudo-phase transformation pad 10 that the pseudo-phase transformation pad 10 that with dashed lines is drawn among Fig. 5, barrier layer 5 and Fig. 8 medium dip are placed is that pseudo-phase transformation pad 10 no longer was adsorbed on the Semiconductor substrate after representative was cleaned.More seriously, though when the concentration of cleaning solution little during to 3000: 1 (volume ratio of water and HF acid), the problem that pseudo-phase transformation pad peels off still can not improve.
Summary of the invention
The problem to be solved in the present invention provides a kind of manufacture method of phase transition storage, to prevent that pseudo-phase transformation pad peels off in the clean process after the phase-change material layers etching.
For addressing the above problem, the invention provides a kind of manufacture method of phase transition storage, described method comprises:
Semiconductor substrate is provided, and it comprises first area, second area;
Dielectric layer forms bottom electrode in the dielectric layer of second area;
The sediment phase change material, then it is carried out etching, form pseudo-phase transformation pad with the position formation patterned phase change material layer of corresponding bottom electrode above described dielectric layer, the local location of corresponding first area, exist between described patterned phase change material layer and the described pseudo-phase transformation pad at interval, described pseudo-phase transformation pad comprises two parts at least, exists between the adjacent part at interval;
The dielectric layer that is formed with described patterned phase change material layer, pseudo-phase transformation pad is carried out clean.
Alternatively, the surface of described bottom electrode and described dielectric layer flush or be lower than described dielectric layer surface.
Alternatively, the making step of described bottom electrode comprises:
Form through hole in the dielectric layer on the Semiconductor substrate second area;
Deposits conductive material makes described through hole be filled up by electric conducting material;
Described electric conducting material is carried out cmp, until exposing described dielectric layer;
Remove the partially conductive material in the described through hole, residual electric conducting material forms bottom electrode.
Alternatively, the making step of described patterned phase change material layer, pseudo-phase transformation pad comprises:
Be formed with on the Semiconductor substrate of bottom electrode sediment phase change material layer, barrier layer successively;
Form graphical photoresist on described barrier layer, make top, described barrier layer be coated with photoresist in the position of corresponding bottom electrode and the local location of corresponding Semiconductor substrate first area;
Remove the barrier layer, the phase-change material layers that are not covered by photoresist, form the patterned phase change material layer at described bottom electrode, and above the dielectric layer on the Semiconductor substrate first area, form pseudo-phase transformation pad, exist between described pseudo-phase transformation pad and the patterned phase change material layer at interval, described pseudo-phase transformation pad comprises two parts at least, exists at interval between the adjacent part.
Alternatively, the material on described barrier layer is TiN.
Alternatively, the width at interval is 40nm～180nm between described part and the adjacent part.
Alternatively, the width of described pseudo-phase transformation pad is that 1 μ m～10 μ m, length are 1 μ m～10 μ m.
Alternatively, utilize the HF acid that contains water to carry out described clean step, the volume ratio of water and HF acid is 1000: 1～15000: 1.
Alternatively, the time of described clean is 20s～120s.
Alternatively, described dielectric layer is PETEOS.
Simultaneously, the present invention also provides a kind of phase transition storage, comprising:
Dielectric layer, it is positioned on the Semiconductor substrate that comprises first area, second area;
Bottom electrode, it is located in the dielectric layer on the Semiconductor substrate second area;
The patterned phase change material layer, it is positioned at the bottom electrode top;
Puppet phase transformation pad, the dielectric layer top that it is positioned on the Semiconductor substrate first area exists at interval between described pseudo-phase transformation pad and the described patterned phase change material layer, and described pseudo-phase transformation pad comprises two parts, existence interval between the adjacent part at least.
Alternatively, the upper surface of described bottom electrode and described dielectric layer flush or be lower than described dielectric layer surface.
Alternatively, described patterned phase change material layer, pseudo-phase transformation pad top are provided with the barrier layer.
Alternatively, the material on described barrier layer is TiN.
Alternatively, the width at interval is 40nm～180nm between described part and the adjacent part.
Alternatively, the width of described pseudo-phase transformation pad is that 1 μ m～10 μ m, length are 1 μ m～10 μ m.
Alternatively, described dielectric layer is PETEOS.
Compared with prior art, the present invention is divided into pseudo-phase transformation pad after a plurality of parts that have the interval each other, has effectively improved the flaky problem of pseudo-phase transformation pad in the clean process after the phase-change material layers etching.
Description of drawings
Fig. 1 is a kind of rough schematic view of common phase transition storage.
Fig. 2 to Fig. 6 is the making schematic diagram of existing a kind of phase transition storage.
Fig. 7 is that the side at the patterned phase change material layer does not form under the situation of pseudo-phase transformation pad, and dielectric layer is carried out cmp so that the inhomogeneous schematic diagram of polishing occurs.
Fig. 8 is the schematic diagram that pseudo-phase transformation pad peels off in the existing cleaning process of phase transition storage after the phase-change material layers etching.
Fig. 9 is the making flow chart of phase transition storage among the embodiment of phase transition storage manufacture method of the present invention.
Figure 10 to Figure 16, Figure 18, Figure 19 are the cutaway views of phase transition storage among the embodiment of phase transition storage manufacture method of the present invention.
Figure 17 is that there is not the schematic diagram that peels off in pseudo-phase transformation pad in the cleaning process of the present invention after the phase-change material etching.
Embodiment
The problem to be solved in the present invention provides a kind of manufacture method of phase transition storage, to prevent that pseudo-phase transformation pad peels off in the clean process after the phase-change material layers etching.
For addressing the above problem, the inventor finds, after pseudo-phase transformation pad being divided into a plurality of parts that have the interval each other, bonding force between pseudo-phase transformation pad and its below dielectric layer can significantly be strengthened, and has effectively improved the flaky problem of pseudo-phase transformation pad in the clean process after the phase-change material layers etching.
Below in conjunction with accompanying drawing, by specific embodiment, technical scheme of the present invention is carried out clear, complete description, obviously, described embodiment only is the part of embodiment of the present invention, rather than they are whole.According to these embodiment, those of ordinary skill in the art belongs to protection scope of the present invention need not obtainable all other execution modes under the prerequisite of creative work.
Fig. 9 is the making flow chart of phase transition storage among the embodiment of phase transition storage manufacture method of the present invention.As described in Figure 9, described method comprises:
Step S100: Semiconductor substrate is provided, and it comprises first area, second area.
Step S200: dielectric layer forms bottom electrode in the dielectric layer on the Semiconductor substrate second area.
Step S300: sediment phase change material, it is carried out etching, form pseudo-phase transformation pad with the position formation patterned phase change material layer of corresponding bottom electrode above dielectric layer, the local location of corresponding semiconductor first area, exist between patterned phase change material layer and the pseudo-phase transformation pad at interval, pseudo-phase transformation pad comprises two parts at least, exists at interval between the adjacent part.
Step S400: the dielectric layer that is formed with patterned phase change material layer, pseudo-phase transformation pad is carried out clean.
Figure 10 to Figure 19 is the cutaway view of phase transition storage among the embodiment of phase transition storage manufacture method of the present invention, and the manufacture method that Figure 10 to Figure 19 and Fig. 9 are combined phase transition storage of the present invention describes below.
Execution in step S100 at first: Semiconductor substrate is provided, and it comprises first area, second area.
As shown in figure 10, provide Semiconductor substrate 20, it is divided into two zones at least: first area I, second area II.In other embodiments of the invention, Semiconductor substrate also can be divided into three or above zone, to be used to form other semiconductor device of integrated circuit.In the preferred embodiment of the present invention, Semiconductor substrate 20 is silicon substrate, but the present invention is not limited to this, and Semiconductor substrate 20 can be made up of other semi-conducting material.Semiconductor substrate 20 can be to have finished the substrate of CMOS FEOL, namely may comprise isolation structure, electric capacity, diode or similar semiconductor device structure in the Semiconductor substrate.
In order to control the operation of phase transition storage, form in Semiconductor substrate before the bottom electrode of phase transition storage, need to form switch element (not shown) in Semiconductor substrate, the phase transition storage of switch element and follow-up formation electrically connects, heat with the electrode to phase transition storage, the crystalline state of partial phase change material layer (that part of phase-change material layers that contacts with bottom electrode) is changed.Switch element comprises the vertical diode (vertical diode) that p type semiconductor layer and n type semiconductor layer are formed, but the present invention is not limited to this, described switch element can also be bipolar junction transistor (bipolar junction transistor, BJT) or mos field effect transistor (metal oxide semiconductor field effect transistor, MOSFET).
Then execution in step S200: dielectric layer forms bottom electrode in the dielectric layer on the Semiconductor substrate second area, the surface of bottom electrode and dielectric layer flush or be lower than the dielectric layer surface.
As shown in figure 11, dielectric layer 21 on Semiconductor substrate 20, and dielectric layer 21 can be oxide skin(coating) or nitride layer.Described oxide skin(coating) can comprise silica (SiO
2), boron phosphorus silicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), unadulterated silicate glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin coating dielectric medium (SOD).Nitride layer can comprise silicon nitride (silicon nitride Si
3N
4) or silicon oxynitride (SiON).In a preferred embodiment of the invention, the SiO of dielectric layer 21 for utilizing TEOS to form
2, i.e. PETEOS.Utilize PETEOS method deposit SiO
2Speed higher relatively, in integrated circuit, benefit for improving silicon chip output.
In one embodiment of the invention, as shown in figure 11, utilize for example photoetching and etching technics that dielectric layer 21 is carried out graphical treatment, to form through hole (not shown) in the dielectric layer 21 on Semiconductor substrate second area II, the position of described through hole is corresponding with the switch element in the Semiconductor substrate 20, so that phase transition storage can be electrically connected with switch element.Then, deposits conductive material on Semiconductor substrate 20 is filled up by described electric conducting material until described through hole.Described electric conducting material can be Ti, W, Ta, TiN, TiW, TaN, TiAl, TiWN, TiAlN etc.In a preferred embodiment of the invention, described electric conducting material is W.Before the described electric conducting material of deposition, can as TiN, diffuse in the dielectric layer to prevent the electric conducting material of subsequent deposition in through hole at sidewall and bottom deposition one deck diffusion impervious layer (not shown) of described through hole.Then, electric conducting material is carried out cmp, expose until dielectric layer 21.So far, join shown in Figure 11ly, form bottom electrode 22 in can the dielectric layer 21 on Semiconductor substrate second area II, and the surperficial 22a of bottom electrode 22 flushes with the surperficial 21a of dielectric layer 21.
Join shown in Figure 1, when phase transition storage will be implemented in logical value 0 to the conversion between the logical value 1, must rise to fusion temperature with the temperature of enough energy excitation phase-change material layer segment 14a, in heating phase-change material layer segment 14a, need avoid heating phase-change material layer segment 14a phase-change material on every side, then, carry out rapid quenching and handle, make phase-change material layer segment 14a become amorphous state by crystalline state, thereby realize the data storage.But, can there be some problems in this phase change memory structure: when phase-change material layer segment 14a is heated, heat is easy to be delivered to phase-change material layer segment 14a phase-change material on every side, causes phase transition storage can't be implemented in logical value 0 to the conversion between the logical value 1.
For improving the problems referred to above, in a preferred embodiment of the invention, after the bottom electrode 22 that formation is surperficial with dielectric layer surface 21a flushes, as shown in figure 12, remove the partially conductive material in the described through hole, residual electric conducting material forms final bottom electrode.Therefore, in this kind phase change memory structure, the surperficial 22a of bottom electrode can be lower than dielectric layer surface 21a.Described removal method can be common semiconductor etching methods such as dry etching, wet etching or both combinations.In one embodiment of the invention, can remove the electric conducting material about half in the through hole.
Follow execution in step S300: the sediment phase change material, it is carried out etching, form pseudo-phase transformation pad with the position formation patterned phase change material layer of corresponding bottom electrode above dielectric layer, the local location of corresponding semiconductor first area, exist between patterned phase change material layer and the pseudo-phase transformation pad at interval, pseudo-phase transformation pad comprises two parts at least, exists at interval between the adjacent part.
As shown in figure 13, sediment phase change material layer 23 on the Semiconductor substrate 20 that is formed with bottom electrode 22, phase-change material layers 23 can comprise chalcogenide, as germanium-antimony-tellurium (Ge-Sb-Te), arsenic-antimony-tellurium (As-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), tin-indium-antimony-tellurium (Sn-In-Sb-Te), arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te), tantalum-antimony-tellurium (Ta-Sb-Te), niobium-antimony-tellurium (Nb-Sb-Te), vanadium-antimony-tellurium (V-Sb-Te), tungsten-antimony-tellurium (W-Sb-Te), molybdenum-antimony-tellurium (Mo-Sb-Te), chromium-antimony-tellurium (Cr-Sb-Te), tungsten-antimony-selenium (W-Sb-Se), molybdenum antimony selenium (Mo-Sb-Se), chromium-antimony-selenium (Cr-Sb-Se), Ga-Sb, In-Sb, In-Se, Sb-Te, Ge-Te, Ag-In-Sb-Te etc.In a preferred embodiment of the invention, phase-change material layers 23 be germanium-antimony-tellurium (Ge-Sb-Te, GST).Certainly, phase-change material layers 23 also can comprise other phase-change material well-known to those skilled in the art.
It is shown in Figure 13 to continue ginseng; in one embodiment of the invention; needs according to subsequent technique; after the sediment phase change material layer 23; meeting deposited barrier layer (barrier layer) 24 on phase-change material layers 23, one of effect that play on barrier layer 24 are the phase-change material layers 23 that protection is positioned at its below.Barrier layer 24 can comprise suitable electric conducting materials such as TiN, TiW.In a preferred embodiment of the invention, barrier layer 24 is TiN.
As shown in figure 14,24 form graphical photoresist on the barrier layer, make 24 tops, barrier layer be coated with photoresist 25a in the position of corresponding bottom electrode 22, and make 24 tops, barrier layer be coated with photoresist 25b at the local location of corresponding Semiconductor substrate first area I.Wherein, exist at interval between the photoresist 25b on the photoresist 25a of bottom electrode 22 tops and the Semiconductor substrate first area I, the photoresist 25b on the I of Semiconductor substrate first area comprises two parts at least, exists at interval between the adjacent part.
As shown in figure 15, be mask with graphical photoresist, remove the barrier layer 24, the phase-change material layers 23 that are not covered by photoresist, form patterned phase change material layer 26 at bottom electrode 22, and above the dielectric layer 21 on the I of Semiconductor substrate first area, form pseudo-phase transformation pad 27, exist at interval between pseudo-phase transformation pad 27 and the patterned phase change material layer 26.Wherein, pseudo-phase transformation pad 27 does not possess device function, and the below does not need to be connected with electrode, its top utmost point that yet can not Connect Power in the subsequent technique.The removal method of barrier layer 24, phase-change material layers 23 has multiple, as dry etching, wet etching or both combinations.For obtain better CMP effect in subsequent treatment, a plurality of pseudo-phase transformation pads 27 are arranged evenly with phase-change material layers 26 integral body.Each pseudo-phase transformation pad 27 comprises two part A that contact with dielectric layer 21 surfaces at least, has B at interval between the adjacent part A.In a preferred embodiment of the invention, the width W of interval B in the pseudo-phase transformation pad 27
1Be 40nm～180nm, the width W of part A
2Be 40nm～180nm, can guarantee to have enough bonding forces between the dielectric layer 21 of pseudo-phase transformation pad 27 and its below like this, make that peeling off can not appear in pseudo-phase transformation pad in follow-up clean process.
It is shown in Figure 15 to continue ginseng, when the lower electrode surface 22a that forms among the above-mentioned steps S200 is lower than dielectric layer surface 21a, the phase-change material layers 23 of deposition not only covers dielectric layer 21 tops, and have in the through hole that partial phase change material layer 23 is filled in bottom electrode 22 places, and contact with bottom electrode 22.During phase transition storage work, bottom electrode can heat phase-change material layers, because the phase-change material layer segment 23a that is filled in the described through hole can closely contact with bottom electrode 22, and centered on by dielectric layer 21 around the phase-change material layer segment 23a, therefore when carrying out described heating process, have only phase-change material layer segment 23a to be heated, phase-change material around the phase-change material layer segment 23a can not be heated, make phase transition storage be readily embodied in logical value 0 to the conversion between the logical value 1, and can reduce the power consumption of phase transition storage.
It is example that present embodiment forms pseudo-phase transformation pad with the wherein side (left side) at the patterned phase change material layer, in other embodiments of the invention, needs according to integrated circuit manufacture process, also can all form described pseudo-phase transformation pad in the both sides (left side, right side) of patterned phase change material layer simultaneously, and the quantity of described pseudo-phase transformation pad can be adjusted according to the actual fabrication situation.
Compared with prior art, the pseudo-phase transformation pad among the present invention is divided into each other and has a plurality of parts at interval, but the cutting apart form and should only not be confined to accompanying drawing of pseudo-phase transformation pad, other similarly cuts apart form also within protection scope of the present invention.
Present embodiment is after the sediment phase change material layer, needs according to follow-up manufacture craft, can be on phase-change material layers deposited barrier layer again, therefore, when forming patterned phase change material layer, pseudo-phase transformation pad, at this moment pseudo-phase transformation pad top meeting covering barrier layer, can also regard the barrier layer as the part of pseudo-phase transformation pad.In other embodiments of the invention, variation according to the phase transition storage manufacture method, after the sediment phase change material layer, may form the material layer (except the barrier layer) that is used as other purposes at phase-change material layers, as be used to form the electric conducting material of top electrode, then material layer, phase-change material layers are carried out etching to form patterned phase change material layer, pseudo-phase transformation pad, at this moment, pseudo-phase transformation pad top meeting layer of cover material, and described material layer can constitute the part of pseudo-phase transformation pad.
It is shown in Figure 15 to continue ginseng, in the process of removing phase-change material layers, Semiconductor substrate 20 surface can form does not wish the accessory substance 28 that obtains in some semiconductor technologies, as polymer (polymer), for fear of accessory substance the electric property of phase transition storage is caused adverse effect, need carry out clean to Semiconductor substrate.
Last execution in step S400: the dielectric layer that is formed with patterned phase change material layer, pseudo-phase transformation pad is carried out clean.
As shown in figure 16, remove photoresist, utilize the HF acid solution that contains water that Semiconductor substrate 20 is carried out clean then, to remove residual accessory substance 28.In a preferred embodiment of the invention, the volume ratio of water and HF acid is 1000: 1～15000: 1 in the described solution.Be 20s～120s when the time of cleaning, can guarantee residual accessory substance 28 is removed.
The inventor utilizes the HF acid solution that contains water of a plurality of variable concentrations one by one Semiconductor substrate to be carried out clean, and the sticking and state between pseudo-phase transformation pad and the Semiconductor substrate after detect cleaning, draw through test of many times, pseudo-phase transformation pad 27 is split into and exists each other after a plurality of parts at interval, bonding force between the dielectric layer 21 of pseudo-phase transformation pad 27 and its below obviously strengthens, substrate 20 is carried out the phenomenon that pseudo-phase transformation pad 27 peels off (as shown in Figure 8) can not occurring after the clean, as shown in figure 17.
Carry out after the described clean step, in one embodiment of the invention, as shown in figure 18, can be on Semiconductor substrate 20 dielectric layer 29, then dielectric layer 29 is carried out cmp and handles until the surface of exposing barrier layer 24.In this step, barrier layer 24 can be used as the stop layer of cmp.Though being divided into, pseudo-phase transformation pad 27 has a plurality of part A of B at interval each other, because the width W of interval A
2Very little, thus naked eyes it seems that pseudo-phase transformation pad 27 remains an integral body.The polishing uniformity that pseudo-phase transformation pad 27 can improve in the above-mentioned chemical mechanical milling tech.The overall dimensions of pseudo-phase transformation pad has material impact to polishing uniformity.In a preferred embodiment of the invention, in conjunction with shown in Figure 17, the width of pseudo-phase transformation pad 27 (with part A, gap B width be the size on the same direction) W
3Be 1 μ m～10 μ m (the width summation of part A, gap B), length (perpendicular to the size on part A, the gap B Width) W
4Be 1 μ m～10 μ m.
After described cmp is handled, as shown in figure 19, on Semiconductor substrate 20, deposit one dielectric layer 30 again, then dielectric layer 30 is carried out graphical treatment, position with corresponding described bottom electrode 22 in dielectric layer 30 forms through hole, filled conductive metal in the through hole then is as Cu, to form the top electrode 31 of phase transition storage.
Simultaneously, the present invention also provides a kind of phase transition storage, and in conjunction with Figure 11, Figure 12, shown in Figure 16, it comprises:
Patterned phase change material layer 26, it is positioned at bottom electrode 22 tops;
Optionally, patterned phase change material layer 26, pseudo-phase transformation pad 27 tops are provided with barrier layer 24, and its material can be TiN.
Compared with prior art, the present invention exists after a plurality of parts at interval by pseudo-phase transformation pad being divided into each other, has effectively improved the flaky problem of pseudo-phase transformation pad in the clean process after the phase-change material etching.
Above-mentioned explanation by embodiment should be able to make this area professional and technical personnel understand the present invention better, and can reproduce and use the present invention.Those skilled in the art can do various changes to above-described embodiment under the situation that does not break away from the spirit and scope of the invention according to described principle herein and modification is apparent.Therefore, the present invention should not be understood that to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (17)
1. the manufacture method of a phase transition storage is characterized in that, described manufacture method comprises:
Semiconductor substrate is provided, and it comprises first area, second area;
Dielectric layer forms bottom electrode in the dielectric layer of second area;
The sediment phase change material, then it is carried out etching, form pseudo-phase transformation pad with the position formation patterned phase change material layer of corresponding bottom electrode above described dielectric layer, the local location of corresponding first area, exist between described patterned phase change material layer and the described pseudo-phase transformation pad at interval, described pseudo-phase transformation pad comprises two parts at least, exists between the adjacent part at interval;
The dielectric layer that is formed with described patterned phase change material layer, pseudo-phase transformation pad is carried out clean.
2. manufacture method according to claim 1 is characterized in that, the surface of described bottom electrode and described dielectric layer flush or be lower than described dielectric layer surface.
3. manufacture method according to claim 2 is characterized in that, the making step of described bottom electrode comprises:
Form through hole in the dielectric layer on the Semiconductor substrate second area;
Deposits conductive material makes described through hole be filled up by electric conducting material;
Described electric conducting material is carried out cmp, until exposing described dielectric layer;
Remove the partially conductive material in the described through hole, residual electric conducting material forms bottom electrode.
4. manufacture method according to claim 1 and 2 is characterized in that, the making step of described patterned phase change material layer, pseudo-phase transformation pad comprises:
Be formed with on the Semiconductor substrate of bottom electrode sediment phase change material layer, barrier layer successively;
Form graphical photoresist on described barrier layer, make top, described barrier layer be coated with photoresist in the position of corresponding bottom electrode and the local location of corresponding Semiconductor substrate first area;
Remove the barrier layer, the phase-change material layers that are not covered by photoresist, form the patterned phase change material layer at described bottom electrode, and above the dielectric layer on the Semiconductor substrate first area, form pseudo-phase transformation pad, exist between described pseudo-phase transformation pad and the patterned phase change material layer at interval, described pseudo-phase transformation pad comprises two parts at least, exists at interval between the adjacent part.
5. manufacture method according to claim 4 is characterized in that, the material on described barrier layer is TiN.
6. manufacture method according to claim 1 is characterized in that, the width at interval is 40nm～180nm between described part and the adjacent part.
7. manufacture method according to claim 1 is characterized in that, the width of described pseudo-phase transformation pad is that 1 μ m～10 μ m, length are 1 μ m～10 μ m.
8. manufacture method according to claim 1 is characterized in that, utilizes the HF acid that contains water to carry out described clean step, and the volume ratio of water and HF acid is 1000: 1～15000: 1.
9. manufacture method according to claim 1 is characterized in that, the time of described clean is 20s～120s.
10. manufacture method according to claim 1 is characterized in that, described dielectric layer is PETEOS.
11. a phase transition storage is characterized in that, comprising:
Dielectric layer, it is positioned on the Semiconductor substrate that comprises first area, second area;
Bottom electrode, it is located in the dielectric layer on the Semiconductor substrate second area;
The patterned phase change material layer, it is positioned at the bottom electrode top;
Puppet phase transformation pad, the dielectric layer top that it is positioned on the Semiconductor substrate first area exists at interval between described pseudo-phase transformation pad and the described patterned phase change material layer, and described pseudo-phase transformation pad comprises two parts, existence interval between the adjacent part at least.
12. phase transition storage according to claim 11 is characterized in that, the upper surface of described bottom electrode and described dielectric layer flush or be lower than described dielectric layer surface.
13. phase transition storage according to claim 11 is characterized in that, described patterned phase change material layer, pseudo-phase transformation pad top are provided with the barrier layer.
14. phase transition storage according to claim 13 is characterized in that, the material on described barrier layer is TiN.
15. phase transition storage according to claim 11 is characterized in that, the width at interval is 40nm～180nm between described part and the adjacent part.
16. phase transition storage according to claim 11 is characterized in that, the width of described pseudo-phase transformation pad is that 1 μ m～10 μ m, length are 1 μ m～10 μ m.
17. phase transition storage according to claim 11 is characterized in that, described dielectric layer is PETEOS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210053864.0A CN103296202B (en) | 2012-03-02 | 2012-03-02 | Phase change memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210053864.0A CN103296202B (en) | 2012-03-02 | 2012-03-02 | Phase change memory and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103296202A true CN103296202A (en) | 2013-09-11 |
| CN103296202B CN103296202B (en) | 2015-04-29 |
Family
ID=49096770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210053864.0A Active CN103296202B (en) | 2012-03-02 | 2012-03-02 | Phase change memory and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103296202B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106159085A (en) * | 2015-04-01 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Phase-change memory cell and preparation method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5885856A (en) * | 1996-08-21 | 1999-03-23 | Motorola, Inc. | Integrated circuit having a dummy structure and method of making |
| US20010030368A1 (en) * | 2000-04-14 | 2001-10-18 | Kazuhiro Tasaka | Semiconductor device and fabrication method |
| TW530350B (en) * | 2002-01-11 | 2003-05-01 | Chartered Semiconductor Mfg | Better copper CMP process utilizing dummy plugs in damascene process |
| JP2004048025A (en) * | 1997-03-31 | 2004-02-12 | Renesas Technology Corp | Semiconductor integrated circuit device |
| US20070015368A1 (en) * | 2005-07-15 | 2007-01-18 | You-Di Jhang | Method of reducing silicon damage around laser marking region of wafers in sti cmp process |
| JP2008041984A (en) * | 2006-08-08 | 2008-02-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| US20090085024A1 (en) * | 2007-09-28 | 2009-04-02 | Ramachandran Muralidhar | Phase change memory structures |
| CN101477967A (en) * | 2009-01-13 | 2009-07-08 | 南京大学 | Process for preparing vertical structure phase-change memory |
-
2012
- 2012-03-02 CN CN201210053864.0A patent/CN103296202B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5885856A (en) * | 1996-08-21 | 1999-03-23 | Motorola, Inc. | Integrated circuit having a dummy structure and method of making |
| JP2004048025A (en) * | 1997-03-31 | 2004-02-12 | Renesas Technology Corp | Semiconductor integrated circuit device |
| US20010030368A1 (en) * | 2000-04-14 | 2001-10-18 | Kazuhiro Tasaka | Semiconductor device and fabrication method |
| TW530350B (en) * | 2002-01-11 | 2003-05-01 | Chartered Semiconductor Mfg | Better copper CMP process utilizing dummy plugs in damascene process |
| US20070015368A1 (en) * | 2005-07-15 | 2007-01-18 | You-Di Jhang | Method of reducing silicon damage around laser marking region of wafers in sti cmp process |
| JP2008041984A (en) * | 2006-08-08 | 2008-02-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| US20090085024A1 (en) * | 2007-09-28 | 2009-04-02 | Ramachandran Muralidhar | Phase change memory structures |
| CN101477967A (en) * | 2009-01-13 | 2009-07-08 | 南京大学 | Process for preparing vertical structure phase-change memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106159085A (en) * | 2015-04-01 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Phase-change memory cell and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103296202B (en) | 2015-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100418244C (en) | Thin film fuse phase change ram and manufacturing method | |
| CN101047230B (en) | Phase change memory unit structure, phase change memory unit and its forming method | |
| CN100418245C (en) | Manufacturing methods for thin film fuse phase change ram | |
| CN101369597B (en) | Multi-level memory cell having phase change element and asymmetrical thermal boundary | |
| CN100495756C (en) | Phase change memory and its forming method | |
| CN1967896B (en) | Insulated phase change memory device and method for manufacturing the same | |
| US7619237B2 (en) | Programmable resistive memory cell with self-forming gap | |
| US7772581B2 (en) | Memory device having wide area phase change element and small electrode contact area | |
| US7459717B2 (en) | Phase change memory cell and manufacturing method | |
| US7105870B2 (en) | Phase-changeable memory devices | |
| CN102460684B (en) | Encapsulated phase change cell structures and methods | |
| CN105118917B (en) | The forming method of phase change memory cell | |
| CN101958398A (en) | Thermal protect pcram structure and methods for making | |
| TW200832694A (en) | Phase change memory and manufacturing method thereof | |
| US7989920B2 (en) | Phase change memory | |
| CN103296202B (en) | Phase change memory and manufacturing method thereof | |
| CN103187525B (en) | Phase change resistor in phase transition storage and forming method thereof | |
| CN105405972A (en) | Preparation method of three-dimensional resistive random access memory retaining air layer | |
| CN106298481A (en) | Phase transition storage and forming method thereof | |
| CN105098071A (en) | Method for manufacturing phase-change memory | |
| CN100585900C (en) | Phase changeable storage device and manufacture method thereof | |
| CN103840078B (en) | Method for manufacturing phase change memory | |
| CN105405861A (en) | Preparation method of three-dimensional resistive random access memory | |
| CN103187524B (en) | The formation method of phase change resistor in phase transition storage | |
| CN105514136A (en) | Method for preparing three-dimensional resistive random access memorizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |